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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 62; RUN: opt -S -passes=gvn < %s | FileCheck %s3 4define i32 @main(i64 %x, ptr %d, ptr noalias %p) {5; CHECK-LABEL: define i32 @main(6; CHECK-SAME: i64 [[X:%.*]], ptr [[D:%.*]], ptr noalias [[P:%.*]]) {7; CHECK-NEXT: [[ENTRY:.*]]:8; CHECK-NEXT: [[T1_PRE_PRE_PRE:%.*]] = load ptr, ptr [[P]], align 89; CHECK-NEXT: [[T2_PRE_PRE_PRE:%.*]] = load ptr, ptr [[T1_PRE_PRE_PRE]], align 8, !tbaa [[ANYPTR_TBAA0:![0-9]+]]10; CHECK-NEXT: [[T3_PRE_PRE_PRE:%.*]] = load ptr, ptr [[T2_PRE_PRE_PRE]], align 811; CHECK-NEXT: br label %[[LOOP:.*]]12; CHECK: [[LOOP]]:13; CHECK-NEXT: [[T2_PRE_PRE:%.*]] = phi ptr [ [[T2_PRE_PRE23:%.*]], %[[LOOP_LATCH:.*]] ], [ [[T2_PRE_PRE_PRE]], %[[ENTRY]] ]14; CHECK-NEXT: [[T1_PRE_PRE:%.*]] = phi ptr [ [[T1_PRE_PRE19:%.*]], %[[LOOP_LATCH]] ], [ [[T1_PRE_PRE_PRE]], %[[ENTRY]] ]15; CHECK-NEXT: br label %[[LOOP2:.*]]16; CHECK: [[LOOP2]]:17; CHECK-NEXT: [[T2_PRE_PRE25:%.*]] = phi ptr [ [[T2_PRE_PRE23]], %[[LOOP2_LATCH_LOOP2_CRIT_EDGE:.*]] ], [ [[T2_PRE_PRE]], %[[LOOP]] ]18; CHECK-NEXT: [[T1_PRE_PRE21:%.*]] = phi ptr [ [[T1_PRE_PRE19]], %[[LOOP2_LATCH_LOOP2_CRIT_EDGE]] ], [ [[T1_PRE_PRE]], %[[LOOP]] ]19; CHECK-NEXT: [[T3_PRE:%.*]] = phi ptr [ [[T3_PRE16:%.*]], %[[LOOP2_LATCH_LOOP2_CRIT_EDGE]] ], [ [[T3_PRE_PRE_PRE]], %[[LOOP]] ]20; CHECK-NEXT: [[T2_PRE:%.*]] = phi ptr [ [[T2_PRE13:%.*]], %[[LOOP2_LATCH_LOOP2_CRIT_EDGE]] ], [ [[T2_PRE_PRE]], %[[LOOP]] ]21; CHECK-NEXT: [[T1_PRE:%.*]] = phi ptr [ [[T1_PRE10:%.*]], %[[LOOP2_LATCH_LOOP2_CRIT_EDGE]] ], [ [[T1_PRE_PRE]], %[[LOOP]] ]22; CHECK-NEXT: br label %[[LOOP3:.*]]23; CHECK: [[LOOP3]]:24; CHECK-NEXT: [[T2_PRE_PRE24:%.*]] = phi ptr [ [[T2_PRE_PRE23]], %[[LOOP3_LATCH:.*]] ], [ [[T2_PRE_PRE25]], %[[LOOP2]] ]25; CHECK-NEXT: [[T1_PRE_PRE20:%.*]] = phi ptr [ [[T1_PRE_PRE19]], %[[LOOP3_LATCH]] ], [ [[T1_PRE_PRE21]], %[[LOOP2]] ]26; CHECK-NEXT: [[T3_PRE17:%.*]] = phi ptr [ [[T3_PRE16]], %[[LOOP3_LATCH]] ], [ [[T3_PRE]], %[[LOOP2]] ]27; CHECK-NEXT: [[T2_PRE14:%.*]] = phi ptr [ [[T2_PRE13]], %[[LOOP3_LATCH]] ], [ [[T2_PRE]], %[[LOOP2]] ]28; CHECK-NEXT: [[T1_PRE11:%.*]] = phi ptr [ [[T1_PRE10]], %[[LOOP3_LATCH]] ], [ [[T1_PRE]], %[[LOOP2]] ]29; CHECK-NEXT: [[T78:%.*]] = phi ptr [ [[T7:%.*]], %[[LOOP3_LATCH]] ], [ [[T3_PRE]], %[[LOOP2]] ]30; CHECK-NEXT: [[T66:%.*]] = phi ptr [ [[T6:%.*]], %[[LOOP3_LATCH]] ], [ [[T2_PRE]], %[[LOOP2]] ]31; CHECK-NEXT: [[T54:%.*]] = phi ptr [ [[T5:%.*]], %[[LOOP3_LATCH]] ], [ [[T1_PRE]], %[[LOOP2]] ]32; CHECK-NEXT: [[TOBOOL_NOT2_I:%.*]] = icmp eq i64 [[X]], 033; CHECK-NEXT: br i1 false, label %[[LOOP3_LOOP3_LATCH_CRIT_EDGE:.*]], label %[[FOR_BODY_LR_PH_I:.*]]34; CHECK: [[LOOP3_LOOP3_LATCH_CRIT_EDGE]]:35; CHECK-NEXT: br label %[[LOOP3_LATCH]]36; CHECK: [[FOR_BODY_LR_PH_I]]:37; CHECK-NEXT: store i32 0, ptr [[P]], align 438; CHECK-NEXT: [[T5_PRE:%.*]] = load ptr, ptr [[P]], align 839; CHECK-NEXT: [[T6_PRE:%.*]] = load ptr, ptr [[T5_PRE]], align 8, !tbaa [[ANYPTR_TBAA0]]40; CHECK-NEXT: [[T7_PRE:%.*]] = load ptr, ptr [[T6_PRE]], align 841; CHECK-NEXT: br label %[[LOOP3_LATCH]]42; CHECK: [[LOOP3_LATCH]]:43; CHECK-NEXT: [[T2_PRE_PRE23]] = phi ptr [ [[T2_PRE_PRE24]], %[[LOOP3_LOOP3_LATCH_CRIT_EDGE]] ], [ [[T6_PRE]], %[[FOR_BODY_LR_PH_I]] ]44; CHECK-NEXT: [[T1_PRE_PRE19]] = phi ptr [ [[T1_PRE_PRE20]], %[[LOOP3_LOOP3_LATCH_CRIT_EDGE]] ], [ [[T5_PRE]], %[[FOR_BODY_LR_PH_I]] ]45; CHECK-NEXT: [[T3_PRE16]] = phi ptr [ [[T3_PRE17]], %[[LOOP3_LOOP3_LATCH_CRIT_EDGE]] ], [ [[T7_PRE]], %[[FOR_BODY_LR_PH_I]] ]46; CHECK-NEXT: [[T2_PRE13]] = phi ptr [ [[T2_PRE14]], %[[LOOP3_LOOP3_LATCH_CRIT_EDGE]] ], [ [[T6_PRE]], %[[FOR_BODY_LR_PH_I]] ]47; CHECK-NEXT: [[T1_PRE10]] = phi ptr [ [[T1_PRE11]], %[[LOOP3_LOOP3_LATCH_CRIT_EDGE]] ], [ [[T5_PRE]], %[[FOR_BODY_LR_PH_I]] ]48; CHECK-NEXT: [[T7]] = phi ptr [ [[T78]], %[[LOOP3_LOOP3_LATCH_CRIT_EDGE]] ], [ [[T7_PRE]], %[[FOR_BODY_LR_PH_I]] ]49; CHECK-NEXT: [[T6]] = phi ptr [ [[T66]], %[[LOOP3_LOOP3_LATCH_CRIT_EDGE]] ], [ [[T6_PRE]], %[[FOR_BODY_LR_PH_I]] ]50; CHECK-NEXT: [[T5]] = phi ptr [ [[T54]], %[[LOOP3_LOOP3_LATCH_CRIT_EDGE]] ], [ [[T5_PRE]], %[[FOR_BODY_LR_PH_I]] ]51; CHECK-NEXT: br i1 false, label %[[LOOP2_LATCH:.*]], label %[[LOOP3]]52; CHECK: [[LOOP2_LATCH]]:53; CHECK-NEXT: br i1 false, label %[[LOOP2_LATCH_LOOP2_CRIT_EDGE]], label %[[LOOP_LATCH]]54; CHECK: [[LOOP2_LATCH_LOOP2_CRIT_EDGE]]:55; CHECK-NEXT: br label %[[LOOP2]]56; CHECK: [[LOOP_LATCH]]:57; CHECK-NEXT: store i32 0, ptr [[D]], align 4, !tbaa [[INT_TBAA4:![0-9]+]]58; CHECK-NEXT: br label %[[LOOP]]59;60entry:61 br label %loop62 63loop:64 br label %loop265 66loop2:67 br label %loop368 69loop3:70 %t1 = load ptr, ptr %p, align 871 %t2 = load ptr, ptr %t1, align 8, !tbaa !072 %t3 = load ptr, ptr %t2, align 873 %t4 = load i8, ptr %t3, align 174 %tobool.not2.i = icmp eq i64 %x, 075 br i1 false, label %loop3.latch, label %for.body.lr.ph.i76 77for.body.lr.ph.i:78 store i32 0, ptr %p, align 479 br label %w.exit.loopexit80 81w.exit.loopexit:82 br label %loop3.latch83 84loop3.latch:85 %t5 = load ptr, ptr %p, align 886 %t6 = load ptr, ptr %t5, align 8, !tbaa !087 %t7 = load ptr, ptr %t6, align 888 br i1 false, label %loop2.latch, label %loop389 90loop2.latch:91 br i1 false, label %loop2, label %loop.latch92 93loop.latch:94 store i32 0, ptr %d, align 4, !tbaa !495 br label %loop96}97 98!0 = !{!1, !1, i64 0}99!1 = !{!"any pointer", !2, i64 0}100!2 = !{!"omnipotent char", !3, i64 0}101!3 = !{!"Simple C/C++ TBAA"}102!4 = !{!5, !5, i64 0}103!5 = !{!"int", !2, i64 0}104;.105; CHECK: [[ANYPTR_TBAA0]] = !{[[META1:![0-9]+]], [[META1]], i64 0}106; CHECK: [[META1]] = !{!"any pointer", [[META2:![0-9]+]], i64 0}107; CHECK: [[META2]] = !{!"omnipotent char", [[META3:![0-9]+]], i64 0}108; CHECK: [[META3]] = !{!"Simple C/C++ TBAA"}109; CHECK: [[INT_TBAA4]] = !{[[META5:![0-9]+]], [[META5]], i64 0}110; CHECK: [[META5]] = !{!"int", [[META2]], i64 0}111;.112