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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -passes=irce,verify -verify-loop-info < %s 2>&1 | FileCheck %s3; RUN: opt -S -verify-loop-info -passes=irce,verify < %s 2>&1 | FileCheck %s4 5define i32 @test_01(i32 %A, i64 %Len, ptr %array) {6; CHECK-LABEL: @test_01(7; CHECK-NEXT: preheader:8; CHECK-NEXT: [[TRIPCHECK:%.*]] = icmp sgt i64 [[LEN:%.*]], 29; CHECK-NEXT: br i1 [[TRIPCHECK]], label [[LOOP_PREHEADER:%.*]], label [[ZERO:%.*]]10; CHECK: loop.preheader:11; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[A:%.*]] to i6412; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[TMP0]], 113; CHECK-NEXT: [[SMIN:%.*]] = call i64 @llvm.smin.i64(i64 [[LEN]], i64 0)14; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[LEN]], [[SMIN]]15; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP1]])16; CHECK-NEXT: [[EXIT_MAINLOOP_AT:%.*]] = call i64 @llvm.umax.i64(i64 [[UMIN]], i64 1)17; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 1, [[EXIT_MAINLOOP_AT]]18; CHECK-NEXT: br i1 [[TMP3]], label [[LOOP_PREHEADER2:%.*]], label [[MAIN_PSEUDO_EXIT:%.*]]19; CHECK: loop.preheader2:20; CHECK-NEXT: br label [[LOOP:%.*]]21; CHECK: loop:22; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ [[INDVAR_NEXT:%.*]], [[LATCH:%.*]] ], [ 1, [[LOOP_PREHEADER2]] ]23; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i64 [[INDVAR]], [[LEN]]24; CHECK-NEXT: br i1 true, label [[GUARDED:%.*]], label [[DEOPT_LOOPEXIT3:%.*]]25; CHECK: guarded:26; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i32, ptr [[ARRAY:%.*]], i64 [[INDVAR]]27; CHECK-NEXT: [[RES:%.*]] = load i32, ptr [[ADDR]], align 428; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[RES]], 029; CHECK-NEXT: br i1 [[CMP]], label [[LATCH]], label [[ZERO_LOOPEXIT_LOOPEXIT4:%.*]]30; CHECK: latch:31; CHECK-NEXT: [[INDVAR_NEXT]] = add nuw nsw i64 [[INDVAR]], 232; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], 333; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[A]] to i6434; CHECK-NEXT: [[CMP2:%.*]] = icmp ugt i64 [[INDVAR_NEXT]], [[TMP5]]35; CHECK-NEXT: [[TMP6:%.*]] = icmp ult i64 [[INDVAR_NEXT]], [[EXIT_MAINLOOP_AT]]36; CHECK-NEXT: [[TMP7:%.*]] = xor i1 [[TMP6]], true37; CHECK-NEXT: br i1 [[TMP7]], label [[MAIN_EXIT_SELECTOR:%.*]], label [[LOOP]]38; CHECK: main.exit.selector:39; CHECK-NEXT: [[INDVAR_NEXT_LCSSA:%.*]] = phi i64 [ [[INDVAR_NEXT]], [[LATCH]] ]40; CHECK-NEXT: [[RES2_LCSSA1:%.*]] = phi i32 [ [[RES2]], [[LATCH]] ]41; CHECK-NEXT: [[TMP8:%.*]] = icmp ult i64 [[INDVAR_NEXT_LCSSA]], [[TMP1]]42; CHECK-NEXT: br i1 [[TMP8]], label [[MAIN_PSEUDO_EXIT]], label [[LOOPEXIT:%.*]]43; CHECK: main.pseudo.exit:44; CHECK-NEXT: [[INDVAR_COPY:%.*]] = phi i64 [ 1, [[LOOP_PREHEADER]] ], [ [[INDVAR_NEXT_LCSSA]], [[MAIN_EXIT_SELECTOR]] ]45; CHECK-NEXT: [[INDVAR_END:%.*]] = phi i64 [ 1, [[LOOP_PREHEADER]] ], [ [[INDVAR_NEXT_LCSSA]], [[MAIN_EXIT_SELECTOR]] ]46; CHECK-NEXT: br label [[POSTLOOP:%.*]]47; CHECK: loopexit.loopexit:48; CHECK-NEXT: [[RES2_LCSSA_PH:%.*]] = phi i32 [ [[RES2_POSTLOOP:%.*]], [[LATCH_POSTLOOP:%.*]] ]49; CHECK-NEXT: br label [[LOOPEXIT]]50; CHECK: loopexit:51; CHECK-NEXT: [[RES2_LCSSA:%.*]] = phi i32 [ [[RES2_LCSSA1]], [[MAIN_EXIT_SELECTOR]] ], [ [[RES2_LCSSA_PH]], [[LOOPEXIT_LOOPEXIT:%.*]] ]52; CHECK-NEXT: ret i32 [[RES2_LCSSA]]53; CHECK: zero.loopexit.loopexit:54; CHECK-NEXT: br label [[ZERO_LOOPEXIT:%.*]]55; CHECK: zero.loopexit.loopexit4:56; CHECK-NEXT: br label [[ZERO_LOOPEXIT]]57; CHECK: zero.loopexit:58; CHECK-NEXT: br label [[ZERO]]59; CHECK: zero:60; CHECK-NEXT: ret i32 061; CHECK: deopt.loopexit:62; CHECK-NEXT: br label [[DEOPT:%.*]]63; CHECK: deopt.loopexit3:64; CHECK-NEXT: br label [[DEOPT]]65; CHECK: deopt:66; CHECK-NEXT: ret i32 167; CHECK: postloop:68; CHECK-NEXT: br label [[LOOP_POSTLOOP:%.*]]69; CHECK: loop.postloop:70; CHECK-NEXT: [[INDVAR_POSTLOOP:%.*]] = phi i64 [ [[INDVAR_NEXT_POSTLOOP:%.*]], [[LATCH_POSTLOOP]] ], [ [[INDVAR_COPY]], [[POSTLOOP]] ]71; CHECK-NEXT: [[TMP9:%.*]] = icmp ult i64 [[INDVAR_POSTLOOP]], [[LEN]]72; CHECK-NEXT: br i1 [[TMP9]], label [[GUARDED_POSTLOOP:%.*]], label [[DEOPT_LOOPEXIT:%.*]]73; CHECK: guarded.postloop:74; CHECK-NEXT: [[ADDR_POSTLOOP:%.*]] = getelementptr inbounds i32, ptr [[ARRAY]], i64 [[INDVAR_POSTLOOP]]75; CHECK-NEXT: [[RES_POSTLOOP:%.*]] = load i32, ptr [[ADDR_POSTLOOP]], align 476; CHECK-NEXT: [[CMP_POSTLOOP:%.*]] = icmp ne i32 [[RES_POSTLOOP]], 077; CHECK-NEXT: br i1 [[CMP_POSTLOOP]], label [[LATCH_POSTLOOP]], label [[ZERO_LOOPEXIT_LOOPEXIT:%.*]]78; CHECK: latch.postloop:79; CHECK-NEXT: [[INDVAR_NEXT_POSTLOOP]] = add nuw nsw i64 [[INDVAR_POSTLOOP]], 280; CHECK-NEXT: [[RES2_POSTLOOP]] = mul i32 [[RES_POSTLOOP]], 381; CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[A]] to i6482; CHECK-NEXT: [[CMP2_POSTLOOP:%.*]] = icmp ugt i64 [[INDVAR_NEXT_POSTLOOP]], [[TMP10]]83; CHECK-NEXT: br i1 [[CMP2_POSTLOOP]], label [[LOOPEXIT_LOOPEXIT]], label [[LOOP_POSTLOOP]], !llvm.loop [[LOOP0:![0-9]+]], !loop_constrainer.loop.clone !584;85preheader:86 %tripcheck = icmp sgt i64 %Len, 287 br i1 %tripcheck, label %loop, label %zero88 89loop:90 %indvar = phi i64 [ 1, %preheader ], [ %indvar.next, %latch ]91 %0 = icmp ult i64 %indvar, %Len92 br i1 %0, label %guarded, label %deopt93 94guarded:95 %addr = getelementptr inbounds i32, ptr %array, i64 %indvar96 %res = load i32, ptr %addr97 %cmp = icmp eq i32 %res, 098 br i1 %cmp, label %zero, label %latch99 100latch:101 %indvar.next = add nuw nsw i64 %indvar, 2102 %res2 = mul i32 %res, 3103; NOTE: this is loop invariant value, but not loop invariant instruction!104 %1 = zext i32 %A to i64105 %cmp2 = icmp ugt i64 %indvar.next, %1106 br i1 %cmp2, label %loopexit, label %loop107 108loopexit:109 ret i32 %res2110 111zero:112 ret i32 0113 114deopt:115 ret i32 1116 117}118