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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --include-generated-funcs2; RUN: opt -S -passes=verify,iroutliner -ir-outlining-no-cost < %s | FileCheck %s3 4; Check that differently ordered phi nodes are not matched when merged, instead5; generating two output paths.6 7define void @f1() {8bb1:9 %0 = add i32 1, 210 %1 = add i32 3, 411 %2 = add i32 5, 612 %3 = add i32 7, 813 br i1 true, label %bb2, label %bb514bb2:15 %4 = mul i32 5, 416 br label %bb517 18placeholder:19 %a = sub i32 5, 420 ret void21 22bb5:23 %phinode = phi i32 [%3, %bb1], [%2, %bb2]24 ret void25}26 27define void @f2() {28bb1:29 %0 = add i32 1, 230 %1 = add i32 3, 431 %2 = add i32 5, 632 %3 = add i32 7, 833 br i1 true, label %bb2, label %bb534bb2:35 %4 = mul i32 5, 436 br label %bb537 38placeholder:39 %a = sub i32 5, 440 ret void41 42bb5:43 %phinode = phi i32 [%2, %bb1], [%3, %bb2]44 ret void45}46; CHECK-LABEL: @f1(47; CHECK-NEXT: bb1:48; CHECK-NEXT: [[PHINODE_CE_LOC:%.*]] = alloca i32, align 449; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[PHINODE_CE_LOC]])50; CHECK-NEXT: [[TMP0:%.*]] = call i1 @outlined_ir_func_0(ptr [[PHINODE_CE_LOC]], i32 0)51; CHECK-NEXT: [[PHINODE_CE_RELOAD:%.*]] = load i32, ptr [[PHINODE_CE_LOC]], align 452; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[PHINODE_CE_LOC]])53; CHECK-NEXT: br i1 [[TMP0]], label [[BB5:%.*]], label [[BB1_AFTER_OUTLINE:%.*]]54; CHECK: bb1_after_outline:55; CHECK-NEXT: ret void56; CHECK: bb5:57; CHECK-NEXT: [[PHINODE:%.*]] = phi i32 [ [[PHINODE_CE_RELOAD]], [[BB1:%.*]] ]58; CHECK-NEXT: ret void59;60;61; CHECK-LABEL: @f2(62; CHECK-NEXT: bb1:63; CHECK-NEXT: [[PHINODE_CE_LOC:%.*]] = alloca i32, align 464; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[PHINODE_CE_LOC]])65; CHECK-NEXT: [[TMP0:%.*]] = call i1 @outlined_ir_func_0(ptr [[PHINODE_CE_LOC]], i32 1)66; CHECK-NEXT: [[PHINODE_CE_RELOAD:%.*]] = load i32, ptr [[PHINODE_CE_LOC]], align 467; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[PHINODE_CE_LOC]])68; CHECK-NEXT: br i1 [[TMP0]], label [[BB5:%.*]], label [[BB1_AFTER_OUTLINE:%.*]]69; CHECK: bb1_after_outline:70; CHECK-NEXT: ret void71; CHECK: bb5:72; CHECK-NEXT: [[PHINODE:%.*]] = phi i32 [ [[PHINODE_CE_RELOAD]], [[BB1:%.*]] ]73; CHECK-NEXT: ret void74;75;76; CHECK-LABEL: define internal i1 @outlined_ir_func_0(77; CHECK-NEXT: newFuncRoot:78; CHECK-NEXT: br label [[BB1_TO_OUTLINE:%.*]]79; CHECK: bb1_to_outline:80; CHECK-NEXT: [[TMP2:%.*]] = add i32 1, 281; CHECK-NEXT: [[TMP3:%.*]] = add i32 3, 482; CHECK-NEXT: [[TMP4:%.*]] = add i32 5, 683; CHECK-NEXT: [[TMP5:%.*]] = add i32 7, 884; CHECK-NEXT: br i1 true, label [[BB2:%.*]], label [[BB5_SPLIT:%.*]]85; CHECK: bb2:86; CHECK-NEXT: [[TMP6:%.*]] = mul i32 5, 487; CHECK-NEXT: br label [[BB5_SPLIT]]88; CHECK: placeholder:89; CHECK-NEXT: [[A:%.*]] = sub i32 5, 490; CHECK-NEXT: br label [[BB1_AFTER_OUTLINE_EXITSTUB:%.*]]91; CHECK: bb5.split:92; CHECK-NEXT: [[TMP7:%.*]] = phi i32 [ [[TMP4]], [[BB1_TO_OUTLINE]] ], [ [[TMP5]], [[BB2]] ]93; CHECK-NEXT: [[PHINODE_CE:%.*]] = phi i32 [ [[TMP5]], [[BB1_TO_OUTLINE]] ], [ [[TMP4]], [[BB2]] ]94; CHECK-NEXT: br label [[BB5_EXITSTUB:%.*]]95; CHECK: bb5.exitStub:96; CHECK-NEXT: switch i32 [[TMP1:%.*]], label [[FINAL_BLOCK_1:%.*]] [97; CHECK-NEXT: i32 0, label [[OUTPUT_BLOCK_0_1:%.*]]98; CHECK-NEXT: i32 1, label [[OUTPUT_BLOCK_1_1:%.*]]99; CHECK-NEXT: ]100; CHECK: bb1_after_outline.exitStub:101; CHECK-NEXT: switch i32 [[TMP1]], label [[FINAL_BLOCK_0:%.*]] [102; CHECK-NEXT: ]103; CHECK: output_block_0_1:104; CHECK-NEXT: store i32 [[PHINODE_CE]], ptr [[TMP0:%.*]], align 4105; CHECK-NEXT: br label [[FINAL_BLOCK_1]]106; CHECK: output_block_1_1:107; CHECK-NEXT: store i32 [[TMP7]], ptr [[TMP0]], align 4108; CHECK-NEXT: br label [[FINAL_BLOCK_1]]109; CHECK: final_block_0:110; CHECK-NEXT: ret i1 false111; CHECK: final_block_1:112; CHECK-NEXT: ret i1 true113;114