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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --include-generated-funcs2; RUN: opt -S -passes=verify,iroutliner -ir-outlining-no-cost < %s | FileCheck %s3 4; When the an outlined section contains a PHINode no incoming blocks outside5; the region, we need to make sure that we do not try to reassign6; the incoming blocks when splitting and reattaching the region.7 8define void @fn1() local_unnamed_addr #0 {9entry:10 br label %block_211 12block_1:13 %a = phi i32 [ 0, %block_2], [ 1, %intermediate_block_1 ]14 br i1 0, label %block_3, label %block_215intermediate_block_1:16 br label %block_117block_2:18 br i1 0, label %block_3, label %block_119 20block_3:21 %b = phi i32 [ 0, %block_2 ], [ 1, %block_1 ]22 br label %block_523 24block_4:25 %c = phi i32 [ 0, %block_5 ], [ 1, %intermediate_block_2 ]26 br i1 0, label %block_6, label %block_527intermediate_block_2:28 br label %block_429block_5:30 br i1 0, label %block_6, label %block_431 32block_6:33 unreachable34}35; CHECK-LABEL: @fn1(36; CHECK-NEXT: entry:37; CHECK-NEXT: [[B_CE_LOC:%.*]] = alloca i32, align 438; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[B_CE_LOC]])39; CHECK-NEXT: call void @outlined_ir_func_0(ptr [[B_CE_LOC]], i32 0)40; CHECK-NEXT: [[B_CE_RELOAD:%.*]] = load i32, ptr [[B_CE_LOC]], align 441; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[B_CE_LOC]])42; CHECK-NEXT: br label [[BLOCK_3:%.*]]43; CHECK: block_3:44; CHECK-NEXT: [[B:%.*]] = phi i32 [ [[B_CE_RELOAD]], [[ENTRY:%.*]] ]45; CHECK-NEXT: call void @outlined_ir_func_0(ptr null, i32 -1)46; CHECK-NEXT: br label [[BLOCK_6:%.*]]47; CHECK: block_6:48; CHECK-NEXT: unreachable49;50;51; CHECK-LABEL: define internal void @outlined_ir_func_0(52; CHECK-NEXT: newFuncRoot:53; CHECK-NEXT: br label [[ENTRY_TO_OUTLINE:%.*]]54; CHECK: entry_to_outline:55; CHECK-NEXT: br label [[BLOCK_2:%.*]]56; CHECK: block_1:57; CHECK-NEXT: [[A:%.*]] = phi i32 [ 0, [[BLOCK_2]] ], [ 1, [[INTERMEDIATE_BLOCK_1:%.*]] ]58; CHECK-NEXT: br i1 false, label [[BLOCK_3_SPLIT:%.*]], label [[BLOCK_2]]59; CHECK: intermediate_block_1:60; CHECK-NEXT: br label [[BLOCK_1:%.*]]61; CHECK: block_2:62; CHECK-NEXT: br i1 false, label [[BLOCK_3_SPLIT]], label [[BLOCK_1]]63; CHECK: block_3.split:64; CHECK-NEXT: [[B_CE:%.*]] = phi i32 [ 0, [[BLOCK_2]] ], [ 1, [[BLOCK_1]] ]65; CHECK-NEXT: br label [[BLOCK_3_EXITSTUB:%.*]]66; CHECK: block_3.exitStub:67; CHECK-NEXT: switch i32 [[TMP1:%.*]], label [[FINAL_BLOCK_0:%.*]] [68; CHECK-NEXT: i32 0, label [[OUTPUT_BLOCK_0_0:%.*]]69; CHECK-NEXT: ]70; CHECK: output_block_0_0:71; CHECK-NEXT: store i32 [[B_CE]], ptr [[TMP0:%.*]], align 472; CHECK-NEXT: br label [[FINAL_BLOCK_0]]73; CHECK: final_block_0:74; CHECK-NEXT: ret void75;76