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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --include-generated-funcs2; RUN: opt -S -passes=verify,iroutliner -ir-outlining-no-cost < %s | FileCheck %s3 4; Here we have multiple exits, but the different sources, same outputs are5; needed, this checks that they are compressed, and moved into the appropriate6; output blocks.7 8define void @outline_outputs1() #0 {9entry:10 %output = alloca i32, align 411 %result = alloca i32, align 412 %output2 = alloca i32, align 413 %result2 = alloca i32, align 414 %a = alloca i32, align 415 %b = alloca i32, align 416 br label %block_217block_1:18 %a2 = alloca i32, align 419 %b2 = alloca i32, align 420 br label %block_221block_2:22 %a2val = load i32, ptr %a23 %b2val = load i32, ptr %b24 %add2 = add i32 2, %a2val25 %mul2 = mul i32 2, %b2val26 br label %block_527block_3:28 %aval = load i32, ptr %a29 %bval = load i32, ptr %b30 %add = add i32 2, %aval31 %mul = mul i32 2, %bval32 br label %block_433block_4:34 store i32 %add, ptr %output, align 435 store i32 %mul, ptr %result, align 436 br label %block_637block_5:38 store i32 %add2, ptr %output, align 439 store i32 %mul2, ptr %result, align 440 br label %block_641dummy:42 ret void43block_6:44 %diff = phi i32 [%aval, %block_4], [%a2val, %block_5]45 ret void46}47 48define void @outline_outputs2() #0 {49entry:50 %output = alloca i32, align 451 %result = alloca i32, align 452 %output2 = alloca i32, align 453 %result2 = alloca i32, align 454 %a = alloca i32, align 455 %b = alloca i32, align 456 br label %block_257block_1:58 %a2 = alloca i32, align 459 %b2 = alloca i32, align 460 br label %block_261block_2:62 %a2val = load i32, ptr %a63 %b2val = load i32, ptr %b64 %add2 = add i32 2, %a2val65 %mul2 = mul i32 2, %b2val66 br label %block_567block_3:68 %aval = load i32, ptr %a69 %bval = load i32, ptr %b70 %add = add i32 2, %aval71 %mul = mul i32 2, %bval72 br label %block_473block_4:74 store i32 %add, ptr %output, align 475 store i32 %mul, ptr %result, align 476 br label %block_677block_5:78 store i32 %add2, ptr %output, align 479 store i32 %mul2, ptr %result, align 480 br label %block_681dummy:82 ret void83block_6:84 %diff = phi i32 [%aval, %block_4], [%a2val, %block_5]85 ret void86}87 88; CHECK-LABEL: @outline_outputs1(89; CHECK-NEXT: entry:90; CHECK-NEXT: [[DIFF_CE_LOC:%.*]] = alloca i32, align 491; CHECK-NEXT: [[OUTPUT:%.*]] = alloca i32, align 492; CHECK-NEXT: [[RESULT:%.*]] = alloca i32, align 493; CHECK-NEXT: [[OUTPUT2:%.*]] = alloca i32, align 494; CHECK-NEXT: [[RESULT2:%.*]] = alloca i32, align 495; CHECK-NEXT: [[A:%.*]] = alloca i32, align 496; CHECK-NEXT: [[B:%.*]] = alloca i32, align 497; CHECK-NEXT: br label [[BLOCK_2:%.*]]98; CHECK: block_1:99; CHECK-NEXT: [[A2:%.*]] = alloca i32, align 4100; CHECK-NEXT: [[B2:%.*]] = alloca i32, align 4101; CHECK-NEXT: br label [[BLOCK_2]]102; CHECK: block_2:103; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[DIFF_CE_LOC]])104; CHECK-NEXT: call void @outlined_ir_func_0(ptr [[A]], ptr [[B]], ptr [[OUTPUT]], ptr [[RESULT]], ptr [[DIFF_CE_LOC]])105; CHECK-NEXT: [[DIFF_CE_RELOAD:%.*]] = load i32, ptr [[DIFF_CE_LOC]], align 4106; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[DIFF_CE_LOC]])107; CHECK-NEXT: br label [[BLOCK_6:%.*]]108; CHECK: dummy:109; CHECK-NEXT: ret void110; CHECK: block_6:111; CHECK-NEXT: [[DIFF:%.*]] = phi i32 [ [[DIFF_CE_RELOAD]], [[BLOCK_2]] ]112; CHECK-NEXT: ret void113;114;115; CHECK-LABEL: @outline_outputs2(116; CHECK-NEXT: entry:117; CHECK-NEXT: [[DIFF_CE_LOC:%.*]] = alloca i32, align 4118; CHECK-NEXT: [[OUTPUT:%.*]] = alloca i32, align 4119; CHECK-NEXT: [[RESULT:%.*]] = alloca i32, align 4120; CHECK-NEXT: [[OUTPUT2:%.*]] = alloca i32, align 4121; CHECK-NEXT: [[RESULT2:%.*]] = alloca i32, align 4122; CHECK-NEXT: [[A:%.*]] = alloca i32, align 4123; CHECK-NEXT: [[B:%.*]] = alloca i32, align 4124; CHECK-NEXT: br label [[BLOCK_2:%.*]]125; CHECK: block_1:126; CHECK-NEXT: [[A2:%.*]] = alloca i32, align 4127; CHECK-NEXT: [[B2:%.*]] = alloca i32, align 4128; CHECK-NEXT: br label [[BLOCK_2]]129; CHECK: block_2:130; CHECK-NEXT: call void @llvm.lifetime.start.p0(ptr [[DIFF_CE_LOC]])131; CHECK-NEXT: call void @outlined_ir_func_0(ptr [[A]], ptr [[B]], ptr [[OUTPUT]], ptr [[RESULT]], ptr [[DIFF_CE_LOC]])132; CHECK-NEXT: [[DIFF_CE_RELOAD:%.*]] = load i32, ptr [[DIFF_CE_LOC]], align 4133; CHECK-NEXT: call void @llvm.lifetime.end.p0(ptr [[DIFF_CE_LOC]])134; CHECK-NEXT: br label [[BLOCK_6:%.*]]135; CHECK: dummy:136; CHECK-NEXT: ret void137; CHECK: block_6:138; CHECK-NEXT: [[DIFF:%.*]] = phi i32 [ [[DIFF_CE_RELOAD]], [[BLOCK_2]] ]139; CHECK-NEXT: ret void140;141;142; CHECK: define internal void @outlined_ir_func_0(143; CHECK-NEXT: newFuncRoot:144; CHECK-NEXT: br label [[BLOCK_2_TO_OUTLINE:%.*]]145; CHECK: block_2_to_outline:146; CHECK-NEXT: [[A2VAL:%.*]] = load i32, ptr [[TMP0:%.*]], align 4147; CHECK-NEXT: [[B2VAL:%.*]] = load i32, ptr [[TMP1:%.*]], align 4148; CHECK-NEXT: [[ADD2:%.*]] = add i32 2, [[A2VAL]]149; CHECK-NEXT: [[MUL2:%.*]] = mul i32 2, [[B2VAL]]150; CHECK-NEXT: br label [[BLOCK_5:%.*]]151; CHECK: block_3:152; CHECK-NEXT: [[AVAL:%.*]] = load i32, ptr [[TMP0]], align 4153; CHECK-NEXT: [[BVAL:%.*]] = load i32, ptr [[TMP1]], align 4154; CHECK-NEXT: [[ADD:%.*]] = add i32 2, [[AVAL]]155; CHECK-NEXT: [[MUL:%.*]] = mul i32 2, [[BVAL]]156; CHECK-NEXT: br label [[BLOCK_4:%.*]]157; CHECK: block_4:158; CHECK-NEXT: store i32 [[ADD]], ptr [[TMP2:%.*]], align 4159; CHECK-NEXT: store i32 [[MUL]], ptr [[TMP3:%.*]], align 4160; CHECK-NEXT: br label [[BLOCK_6_SPLIT:%.*]]161; CHECK: block_5:162; CHECK-NEXT: store i32 [[ADD2]], ptr [[TMP2]], align 4163; CHECK-NEXT: store i32 [[MUL2]], ptr [[TMP3]], align 4164; CHECK-NEXT: br label [[BLOCK_6_SPLIT]]165; CHECK: block_6.split:166; CHECK-NEXT: [[DIFF_CE:%.*]] = phi i32 [ [[AVAL]], [[BLOCK_4]] ], [ [[A2VAL]], [[BLOCK_5]] ]167; CHECK-NEXT: br label [[BLOCK_6_EXITSTUB:%.*]]168; CHECK: block_6.exitStub:169; CHECK-NEXT: store i32 [[DIFF_CE]], ptr [[TMP4:%.*]], align 4170; CHECK-NEXT: ret void171;172