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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt < %s -passes=infer-alignment -S | FileCheck %s3 4define <2 x i32> @load(<2 x i1> %mask, ptr %ptr) {5; CHECK-LABEL: define <2 x i32> @load(6; CHECK-SAME: <2 x i1> [[MASK:%.*]], ptr [[PTR:%.*]]) {7; CHECK-NEXT: [[ENTRY:.*:]]8; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[PTR]], i64 64) ]9; CHECK-NEXT: [[MASKED_LOAD:%.*]] = call <2 x i32> @llvm.masked.load.v2i32.p0(ptr align 64 [[PTR]], <2 x i1> [[MASK]], <2 x i32> poison)10; CHECK-NEXT: ret <2 x i32> [[MASKED_LOAD]]11;12entry:13 call void @llvm.assume(i1 true) [ "align"(ptr %ptr, i64 64) ]14 %masked_load = call <2 x i32> @llvm.masked.load.v2i32.p0(ptr %ptr, i32 1, <2 x i1> %mask, <2 x i32> poison)15 ret <2 x i32> %masked_load16}17 18define void @store(<2 x i1> %mask, <2 x i32> %val, ptr %ptr) {19; CHECK-LABEL: define void @store(20; CHECK-SAME: <2 x i1> [[MASK:%.*]], <2 x i32> [[VAL:%.*]], ptr [[PTR:%.*]]) {21; CHECK-NEXT: [[ENTRY:.*:]]22; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[PTR]], i64 64) ]23; CHECK-NEXT: tail call void @llvm.masked.store.v2i32.p0(<2 x i32> [[VAL]], ptr align 64 [[PTR]], <2 x i1> [[MASK]])24; CHECK-NEXT: ret void25;26entry:27 call void @llvm.assume(i1 true) [ "align"(ptr %ptr, i64 64) ]28 tail call void @llvm.masked.store.v2i32.p0(<2 x i32> %val, ptr %ptr, i32 1, <2 x i1> %mask)29 ret void30}31 32define <2 x i32> @null(<2 x i1> %mask, <2 x i32> %val) {33; CHECK-LABEL: define <2 x i32> @null(34; CHECK-SAME: <2 x i1> [[MASK:%.*]], <2 x i32> [[VAL:%.*]]) {35; CHECK-NEXT: [[ENTRY:.*:]]36; CHECK-NEXT: [[MASKED_LOAD:%.*]] = tail call <2 x i32> @llvm.masked.load.v2i32.p0(ptr align 4294967296 null, <2 x i1> [[MASK]], <2 x i32> [[VAL]])37; CHECK-NEXT: ret <2 x i32> [[MASKED_LOAD]]38;39entry:40 %masked_load = tail call <2 x i32> @llvm.masked.load.v2i32.p0(ptr null, i32 1, <2 x i1> %mask, <2 x i32> %val)41 ret <2 x i32> %masked_load42}43 44declare void @llvm.assume(i1)45declare <2 x i32> @llvm.masked.load.v2i32.p0(ptr, i32, <2 x i1>, <2 x i32>)46declare void @llvm.masked.store.v2i32.p0(<2 x i32>, ptr, i32, <2 x i1>)47