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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt --mtriple=aarch64-unknown-linux -S -passes=instcombine < %s | FileCheck %s3; ARM64 neon intrinsic variants - <rdar://problem/12349617>4 5define <4 x i32> @mulByZeroARM64(<4 x i16> %x) nounwind readnone ssp {6; CHECK-LABEL: define <4 x i32> @mulByZeroARM64(7; CHECK-SAME: <4 x i16> [[X:%.*]]) #[[ATTR0:[0-9]+]] {8; CHECK-NEXT: [[ENTRY:.*:]]9; CHECK-NEXT: ret <4 x i32> zeroinitializer10;11entry:12 %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> zeroinitializer) nounwind13 ret <4 x i32> %a14}15 16define <4 x i32> @mulByOneARM64(<4 x i16> %x) nounwind readnone ssp {17; CHECK-LABEL: define <4 x i32> @mulByOneARM64(18; CHECK-SAME: <4 x i16> [[X:%.*]]) #[[ATTR0]] {19; CHECK-NEXT: [[ENTRY:.*:]]20; CHECK-NEXT: [[A:%.*]] = sext <4 x i16> [[X]] to <4 x i32>21; CHECK-NEXT: ret <4 x i32> [[A]]22;23entry:24 %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind25 ret <4 x i32> %a26}27 28define <4 x i32> @constantMulARM64() nounwind readnone ssp {29; CHECK-LABEL: define <4 x i32> @constantMulARM64(30; CHECK-SAME: ) #[[ATTR0]] {31; CHECK-NEXT: [[ENTRY:.*:]]32; CHECK-NEXT: ret <4 x i32> splat (i32 6)33;34entry:35 %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind36 ret <4 x i32> %a37}38 39define <4 x i32> @constantMulSARM64() nounwind readnone ssp {40; CHECK-LABEL: define <4 x i32> @constantMulSARM64(41; CHECK-SAME: ) #[[ATTR0]] {42; CHECK-NEXT: [[ENTRY:.*:]]43; CHECK-NEXT: ret <4 x i32> splat (i32 -1)44;45entry:46 %b = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind47 ret <4 x i32> %b48}49 50define <4 x i32> @constantMulUARM64() nounwind readnone ssp {51; CHECK-LABEL: define <4 x i32> @constantMulUARM64(52; CHECK-SAME: ) #[[ATTR0]] {53; CHECK-NEXT: [[ENTRY:.*:]]54; CHECK-NEXT: ret <4 x i32> splat (i32 65535)55;56entry:57 %b = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind58 ret <4 x i32> %b59}60 61define <4 x i32> @complex1ARM64(<4 x i16> %x) nounwind readnone ssp {62; CHECK-LABEL: define <4 x i32> @complex1ARM64(63; CHECK-SAME: <4 x i16> [[X:%.*]]) #[[ATTR0]] {64; CHECK-NEXT: [[ENTRY:.*:]]65; CHECK-NEXT: [[A:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> splat (i16 2), <4 x i16> [[X]]) #[[ATTR2:[0-9]+]]66; CHECK-NEXT: ret <4 x i32> [[A]]67;68entry:69 %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) nounwind70 %b = add <4 x i32> zeroinitializer, %a71 ret <4 x i32> %b72}73 74define <4 x i32> @complex2ARM64(<4 x i32> %x) nounwind readnone ssp {75; CHECK-LABEL: define <4 x i32> @complex2ARM64(76; CHECK-SAME: <4 x i32> [[X:%.*]]) #[[ATTR0]] {77; CHECK-NEXT: [[ENTRY:.*:]]78; CHECK-NEXT: [[B:%.*]] = add <4 x i32> [[X]], splat (i32 6)79; CHECK-NEXT: ret <4 x i32> [[B]]80;81entry:82 %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind83 %b = add <4 x i32> %x, %a84 ret <4 x i32> %b85}86 87declare <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone88declare <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone89 90; CHECK: attributes #0 = { nounwind ssp memory(none) }91; CHECK: attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }92