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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S -passes=instcombine < %s | FileCheck %s3target triple = "aarch64-unknown-linux-gnu"4 5define <vscale x 8 x bfloat> @test_fcvt_bf16_f32(<vscale x 8 x bfloat> %a, <vscale x 4 x float> %b) {6; CHECK-LABEL: define <vscale x 8 x bfloat> @test_fcvt_bf16_f32(7; CHECK-SAME: <vscale x 8 x bfloat> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) {8; CHECK-NEXT: ret <vscale x 8 x bfloat> [[A]]9;10 %out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvt.bf16f32.v2(<vscale x 8 x bfloat> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %b)11 ret <vscale x 8 x bfloat> %out12}13 14define <vscale x 8 x half> @test_fcvt_f16_f32(<vscale x 8 x half> %a, <vscale x 4 x float> %b) {15; CHECK-LABEL: define <vscale x 8 x half> @test_fcvt_f16_f32(16; CHECK-SAME: <vscale x 8 x half> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) {17; CHECK-NEXT: ret <vscale x 8 x half> [[A]]18;19 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fcvt.f16f32(<vscale x 8 x half> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %b)20 ret <vscale x 8 x half> %out21}22 23define <vscale x 8 x half> @test_fcvt_f16_f64(<vscale x 8 x half> %a, <vscale x 2 x double> %b) {24; CHECK-LABEL: define <vscale x 8 x half> @test_fcvt_f16_f64(25; CHECK-SAME: <vscale x 8 x half> [[A:%.*]], <vscale x 2 x double> [[B:%.*]]) {26; CHECK-NEXT: ret <vscale x 8 x half> [[A]]27;28 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fcvt.f16f64(<vscale x 8 x half> %a, <vscale x 2 x i1> zeroinitializer, <vscale x 2 x double> %b)29 ret <vscale x 8 x half> %out30}31 32define <vscale x 4 x float> @test_fcvt_f32_f16(<vscale x 4 x float> %a, <vscale x 8 x half> %b) {33; CHECK-LABEL: define <vscale x 4 x float> @test_fcvt_f32_f16(34; CHECK-SAME: <vscale x 4 x float> [[A:%.*]], <vscale x 8 x half> [[B:%.*]]) {35; CHECK-NEXT: ret <vscale x 4 x float> [[A]]36;37 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f16(<vscale x 4 x float> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 8 x half> %b)38 ret <vscale x 4 x float> %out39}40 41define <vscale x 4 x float> @test_fcvt_f32_f64(<vscale x 4 x float> %a, <vscale x 2 x double> %b) {42; CHECK-LABEL: define <vscale x 4 x float> @test_fcvt_f32_f64(43; CHECK-SAME: <vscale x 4 x float> [[A:%.*]], <vscale x 2 x double> [[B:%.*]]) {44; CHECK-NEXT: ret <vscale x 4 x float> [[A]]45;46 %out = call<vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f64(<vscale x 4 x float> %a, <vscale x 2 x i1> zeroinitializer, <vscale x 2 x double> %b)47 ret <vscale x 4 x float> %out48}49 50define <vscale x 2 x double> @test_fcvt_f64_f16(<vscale x 2 x double> %a, <vscale x 8 x half> %b) {51; CHECK-LABEL: define <vscale x 2 x double> @test_fcvt_f64_f16(52; CHECK-SAME: <vscale x 2 x double> [[A:%.*]], <vscale x 8 x half> [[B:%.*]]) {53; CHECK-NEXT: ret <vscale x 2 x double> [[A]]54;55 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fcvt.f64f16(<vscale x 2 x double> %a, <vscale x 2 x i1> zeroinitializer, <vscale x 8 x half> %b)56 ret <vscale x 2 x double> %out57}58 59define <vscale x 2 x double> @test_fcvt_f64_f32(<vscale x 2 x double> %a, <vscale x 4 x float> %b) {60; CHECK-LABEL: define <vscale x 2 x double> @test_fcvt_f64_f32(61; CHECK-SAME: <vscale x 2 x double> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) {62; CHECK-NEXT: ret <vscale x 2 x double> [[A]]63;64 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fcvt.f64f32(<vscale x 2 x double> %a, <vscale x 2 x i1> zeroinitializer, <vscale x 4 x float> %b)65 ret <vscale x 2 x double> %out66}67 68define <vscale x 4 x float> @test_fcvtlt_f32_f16(<vscale x 4 x float> %a, <vscale x 8 x half> %b) {69; CHECK-LABEL: define <vscale x 4 x float> @test_fcvtlt_f32_f16(70; CHECK-SAME: <vscale x 4 x float> [[A:%.*]], <vscale x 8 x half> [[B:%.*]]) {71; CHECK-NEXT: ret <vscale x 4 x float> [[A]]72;73 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtlt.f32f16(<vscale x 4 x float> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 8 x half> %b)74 ret <vscale x 4 x float> %out75}76 77define <vscale x 2 x double> @test_fcvtlt_f64_f32(<vscale x 2 x double> %a, <vscale x 4 x float> %b) {78; CHECK-LABEL: define <vscale x 2 x double> @test_fcvtlt_f64_f32(79; CHECK-SAME: <vscale x 2 x double> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) {80; CHECK-NEXT: ret <vscale x 2 x double> [[A]]81;82 %out = call <vscale x 2 x double> @llvm.aarch64.sve.fcvtlt.f64f32(<vscale x 2 x double> %a, <vscale x 2 x i1> zeroinitializer, <vscale x 4 x float> %b)83 ret <vscale x 2 x double> %out84}85 86define <vscale x 8 x bfloat> @test_fcvtnt_bf16_f32(<vscale x 8 x bfloat> %a, <vscale x 4 x float> %b) {87; CHECK-LABEL: define <vscale x 8 x bfloat> @test_fcvtnt_bf16_f32(88; CHECK-SAME: <vscale x 8 x bfloat> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) {89; CHECK-NEXT: ret <vscale x 8 x bfloat> [[A]]90;91 %out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvtnt.bf16f32.v2(<vscale x 8 x bfloat> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %b)92 ret <vscale x 8 x bfloat> %out93}94 95define <vscale x 8 x half> @test_fcvtnt_f16_f32(<vscale x 8 x half> %a, <vscale x 4 x float> %b) {96; CHECK-LABEL: define <vscale x 8 x half> @test_fcvtnt_f16_f32(97; CHECK-SAME: <vscale x 8 x half> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) {98; CHECK-NEXT: ret <vscale x 8 x half> [[A]]99;100 %out = call <vscale x 8 x half> @llvm.aarch64.sve.fcvtnt.f16f32(<vscale x 8 x half> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %b)101 ret <vscale x 8 x half> %out102}103 104define <vscale x 4 x float> @test_fcvtnt_f32_f64(<vscale x 4 x float> %a, <vscale x 2 x double> %b) {105; CHECK-LABEL: define <vscale x 4 x float> @test_fcvtnt_f32_f64(106; CHECK-SAME: <vscale x 4 x float> [[A:%.*]], <vscale x 2 x double> [[B:%.*]]) {107; CHECK-NEXT: ret <vscale x 4 x float> [[A]]108;109 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtnt.f32f64(<vscale x 4 x float> %a, <vscale x 2 x i1> zeroinitializer, <vscale x 2 x double> %b)110 ret <vscale x 4 x float> %out111}112 113define <vscale x 4 x float> @test_fcvtx_f32_f64(<vscale x 4 x float> %a, <vscale x 2 x double> %b) {114; CHECK-LABEL: define <vscale x 4 x float> @test_fcvtx_f32_f64(115; CHECK-SAME: <vscale x 4 x float> [[A:%.*]], <vscale x 2 x double> [[B:%.*]]) {116; CHECK-NEXT: ret <vscale x 4 x float> [[A]]117;118 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtx.f32f64(<vscale x 4 x float> %a, <vscale x 2 x i1> zeroinitializer, <vscale x 2 x double> %b)119 ret <vscale x 4 x float> %out120}121 122define <vscale x 4 x float> @test_fcvtxnt_f32_f64(<vscale x 4 x float> %a, <vscale x 2 x double> %b) {123; CHECK-LABEL: define <vscale x 4 x float> @test_fcvtxnt_f32_f64(124; CHECK-SAME: <vscale x 4 x float> [[A:%.*]], <vscale x 2 x double> [[B:%.*]]) {125; CHECK-NEXT: ret <vscale x 4 x float> [[A]]126;127 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtxnt.f32f64(<vscale x 4 x float> %a, <vscale x 2 x i1> zeroinitializer, <vscale x 2 x double> %b)128 ret <vscale x 4 x float> %out129}130 131define <vscale x 8 x i16> @test_fcvtzs(<vscale x 8 x i16> %a, <vscale x 8 x half> %b) {132; CHECK-LABEL: define <vscale x 8 x i16> @test_fcvtzs(133; CHECK-SAME: <vscale x 8 x i16> [[A:%.*]], <vscale x 8 x half> [[B:%.*]]) {134; CHECK-NEXT: ret <vscale x 8 x i16> [[A]]135;136 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzs.nxv8i16.nxv8f16(<vscale x 8 x i16> %a, <vscale x 8 x i1> zeroinitializer, <vscale x 8 x half> %b)137 ret <vscale x 8 x i16> %out138}139 140define <vscale x 4 x i32> @test_fcvtzs_i32_f16(<vscale x 4 x i32> %a, <vscale x 8 x half> %b) {141; CHECK-LABEL: define <vscale x 4 x i32> @test_fcvtzs_i32_f16(142; CHECK-SAME: <vscale x 4 x i32> [[A:%.*]], <vscale x 8 x half> [[B:%.*]]) {143; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]144;145 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f16(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer,<vscale x 8 x half> %b)146 ret <vscale x 4 x i32> %out147}148 149define <vscale x 4 x i32> @test_fcvtzs_i32_f64(<vscale x 4 x i32> %a, <vscale x 2 x double> %b) {150; CHECK-LABEL: define <vscale x 4 x i32> @test_fcvtzs_i32_f64(151; CHECK-SAME: <vscale x 4 x i32> [[A:%.*]], <vscale x 2 x double> [[B:%.*]]) {152; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]153;154 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzs.i32f64(<vscale x 4 x i32> %a, <vscale x 2 x i1> zeroinitializer, <vscale x 2 x double> %b)155 ret <vscale x 4 x i32> %out156}157 158define <vscale x 2 x i64> @test_fcvtzs_i64_f16(<vscale x 2 x i64> %a, <vscale x 8 x half> %b) {159; CHECK-LABEL: define <vscale x 2 x i64> @test_fcvtzs_i64_f16(160; CHECK-SAME: <vscale x 2 x i64> [[A:%.*]], <vscale x 8 x half> [[B:%.*]]) {161; CHECK-NEXT: ret <vscale x 2 x i64> [[A]]162;163 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f16(<vscale x 2 x i64> %a, <vscale x 2 x i1> zeroinitializer,<vscale x 8 x half> %b)164 ret <vscale x 2 x i64> %out165}166 167define <vscale x 2 x i64> @test_fcvtzs_i64_f32(<vscale x 2 x i64> %a, <vscale x 4 x float> %b) {168; CHECK-LABEL: define <vscale x 2 x i64> @test_fcvtzs_i64_f32(169; CHECK-SAME: <vscale x 2 x i64> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) {170; CHECK-NEXT: ret <vscale x 2 x i64> [[A]]171;172 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzs.i64f32(<vscale x 2 x i64> %a, <vscale x 2 x i1> zeroinitializer, <vscale x 4 x float> %b)173 ret <vscale x 2 x i64> %out174}175 176define <vscale x 8 x i16> @test_fcvtzu(<vscale x 8 x i16> %a, <vscale x 8 x half> %b) {177; CHECK-LABEL: define <vscale x 8 x i16> @test_fcvtzu(178; CHECK-SAME: <vscale x 8 x i16> [[A:%.*]], <vscale x 8 x half> [[B:%.*]]) {179; CHECK-NEXT: ret <vscale x 8 x i16> [[A]]180;181 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.fcvtzu.nxv8i16.nxv8f16(<vscale x 8 x i16> %a, <vscale x 8 x i1> zeroinitializer, <vscale x 8 x half> %b)182 ret <vscale x 8 x i16> %out183}184 185define <vscale x 4 x i32> @test_fcvtzu_i32_f16(<vscale x 4 x i32> %a, <vscale x 8 x half> %b) {186; CHECK-LABEL: define <vscale x 4 x i32> @test_fcvtzu_i32_f16(187; CHECK-SAME: <vscale x 4 x i32> [[A:%.*]], <vscale x 8 x half> [[B:%.*]]) {188; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]189;190 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f16(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer,<vscale x 8 x half> %b)191 ret <vscale x 4 x i32> %out192}193 194define <vscale x 4 x i32> @test_fcvtzu_i32_f64(<vscale x 4 x i32> %a, <vscale x 2 x double> %b) {195; CHECK-LABEL: define <vscale x 4 x i32> @test_fcvtzu_i32_f64(196; CHECK-SAME: <vscale x 4 x i32> [[A:%.*]], <vscale x 2 x double> [[B:%.*]]) {197; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]198;199 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.fcvtzu.i32f64(<vscale x 4 x i32> %a, <vscale x 2 x i1> zeroinitializer, <vscale x 2 x double> %b)200 ret <vscale x 4 x i32> %out201}202 203define <vscale x 2 x i64> @test_fcvtzu_i64_f16(<vscale x 2 x i64> %a, <vscale x 8 x half> %b) {204; CHECK-LABEL: define <vscale x 2 x i64> @test_fcvtzu_i64_f16(205; CHECK-SAME: <vscale x 2 x i64> [[A:%.*]], <vscale x 8 x half> [[B:%.*]]) {206; CHECK-NEXT: ret <vscale x 2 x i64> [[A]]207;208 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f16(<vscale x 2 x i64> %a, <vscale x 2 x i1> zeroinitializer,<vscale x 8 x half> %b)209 ret <vscale x 2 x i64> %out210}211 212define <vscale x 2 x i64> @test_fcvtzu_i64_f32(<vscale x 2 x i64> %a, <vscale x 4 x float> %b) {213; CHECK-LABEL: define <vscale x 2 x i64> @test_fcvtzu_i64_f32(214; CHECK-SAME: <vscale x 2 x i64> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) {215; CHECK-NEXT: ret <vscale x 2 x i64> [[A]]216;217 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.fcvtzu.i64f32(<vscale x 2 x i64> %a, <vscale x 2 x i1> zeroinitializer, <vscale x 4 x float> %b)218 ret <vscale x 2 x i64> %out219}220 221define <vscale x 8 x half> @test_scvtf(<vscale x 8 x half> %a, <vscale x 8 x i16> %b) {222; CHECK-LABEL: define <vscale x 8 x half> @test_scvtf(223; CHECK-SAME: <vscale x 8 x half> [[A:%.*]], <vscale x 8 x i16> [[B:%.*]]) {224; CHECK-NEXT: ret <vscale x 8 x half> [[A]]225;226 %out = call <vscale x 8 x half> @llvm.aarch64.sve.scvtf.nxv8f16.nxv8i16(<vscale x 8 x half> %a, <vscale x 8 x i1> zeroinitializer, <vscale x 8 x i16> %b)227 ret <vscale x 8 x half> %out228}229 230define <vscale x 8 x half> @test_scvtf_f16_i32(<vscale x 8 x half> %a, <vscale x 4 x i32> %b) {231; CHECK-LABEL: define <vscale x 8 x half> @test_scvtf_f16_i32(232; CHECK-SAME: <vscale x 8 x half> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {233; CHECK-NEXT: ret <vscale x 8 x half> [[A]]234;235 %out = call <vscale x 8 x half> @llvm.aarch64.sve.scvtf.f16i32(<vscale x 8 x half> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %b)236 ret <vscale x 8 x half> %out237}238 239define <vscale x 8 x half> @test_scvtf_f16_i64(<vscale x 8 x half> %a,<vscale x 2 x i64> %b) {240; CHECK-LABEL: define <vscale x 8 x half> @test_scvtf_f16_i64(241; CHECK-SAME: <vscale x 8 x half> [[A:%.*]], <vscale x 2 x i64> [[B:%.*]]) {242; CHECK-NEXT: ret <vscale x 8 x half> [[A]]243;244 %out = call <vscale x 8 x half> @llvm.aarch64.sve.scvtf.f16i64(<vscale x 8 x half> %a, <vscale x 2 x i1> zeroinitializer, <vscale x 2 x i64> %b)245 ret <vscale x 8 x half> %out246}247 248define <vscale x 4 x float> @test_scvtf_f32_i64(<vscale x 4 x float> %a, <vscale x 2 x i64> %b) {249; CHECK-LABEL: define <vscale x 4 x float> @test_scvtf_f32_i64(250; CHECK-SAME: <vscale x 4 x float> [[A:%.*]], <vscale x 2 x i64> [[B:%.*]]) {251; CHECK-NEXT: ret <vscale x 4 x float> [[A]]252;253 %out = call <vscale x 4 x float> @llvm.aarch64.sve.scvtf.f32i64(<vscale x 4 x float> %a, <vscale x 2 x i1> zeroinitializer, <vscale x 2 x i64> %b)254 ret <vscale x 4 x float> %out255}256 257define <vscale x 2 x double> @test_scvtf_f64_i32(<vscale x 2 x double> %a, <vscale x 4 x i32> %b) {258; CHECK-LABEL: define <vscale x 2 x double> @test_scvtf_f64_i32(259; CHECK-SAME: <vscale x 2 x double> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {260; CHECK-NEXT: ret <vscale x 2 x double> [[A]]261;262 %out = call <vscale x 2 x double> @llvm.aarch64.sve.scvtf.f64i32(<vscale x 2 x double> %a, <vscale x 2 x i1> zeroinitializer, <vscale x 4 x i32> %b)263 ret <vscale x 2 x double> %out264}265 266define <vscale x 8 x half> @test_ucvtf(<vscale x 8 x half> %a, <vscale x 8 x i16> %b) {267; CHECK-LABEL: define <vscale x 8 x half> @test_ucvtf(268; CHECK-SAME: <vscale x 8 x half> [[A:%.*]], <vscale x 8 x i16> [[B:%.*]]) {269; CHECK-NEXT: ret <vscale x 8 x half> [[A]]270;271 %out = call <vscale x 8 x half> @llvm.aarch64.sve.ucvtf.nxv8f16.nxv8i16(<vscale x 8 x half> %a, <vscale x 8 x i1> zeroinitializer, <vscale x 8 x i16> %b)272 ret <vscale x 8 x half> %out273}274 275define <vscale x 8 x half> @test_ucvtf_f16_i32(<vscale x 8 x half> %a, <vscale x 4 x i32> %b) {276; CHECK-LABEL: define <vscale x 8 x half> @test_ucvtf_f16_i32(277; CHECK-SAME: <vscale x 8 x half> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {278; CHECK-NEXT: ret <vscale x 8 x half> [[A]]279;280 %out = call <vscale x 8 x half> @llvm.aarch64.sve.ucvtf.f16i32(<vscale x 8 x half> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %b)281 ret <vscale x 8 x half> %out282}283 284define <vscale x 8 x half> @test_ucvtf_f16_i64(<vscale x 8 x half> %a,<vscale x 2 x i64> %b) {285; CHECK-LABEL: define <vscale x 8 x half> @test_ucvtf_f16_i64(286; CHECK-SAME: <vscale x 8 x half> [[A:%.*]], <vscale x 2 x i64> [[B:%.*]]) {287; CHECK-NEXT: ret <vscale x 8 x half> [[A]]288;289 %out = call <vscale x 8 x half> @llvm.aarch64.sve.ucvtf.f16i64(<vscale x 8 x half> %a, <vscale x 2 x i1> zeroinitializer, <vscale x 2 x i64> %b)290 ret <vscale x 8 x half> %out291}292 293define <vscale x 4 x float> @test_ucvtf_f32_i64(<vscale x 4 x float> %a, <vscale x 2 x i64> %b) {294; CHECK-LABEL: define <vscale x 4 x float> @test_ucvtf_f32_i64(295; CHECK-SAME: <vscale x 4 x float> [[A:%.*]], <vscale x 2 x i64> [[B:%.*]]) {296; CHECK-NEXT: ret <vscale x 4 x float> [[A]]297;298 %out = call <vscale x 4 x float> @llvm.aarch64.sve.ucvtf.f32i64(<vscale x 4 x float> %a, <vscale x 2 x i1> zeroinitializer, <vscale x 2 x i64> %b)299 ret <vscale x 4 x float> %out300}301 302define <vscale x 2 x double> @test_ucvtf_f64_i32(<vscale x 2 x double> %a, <vscale x 4 x i32> %b) {303; CHECK-LABEL: define <vscale x 2 x double> @test_ucvtf_f64_i32(304; CHECK-SAME: <vscale x 2 x double> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {305; CHECK-NEXT: ret <vscale x 2 x double> [[A]]306;307 %out = call <vscale x 2 x double> @llvm.aarch64.sve.ucvtf.f64i32(<vscale x 2 x double> %a, <vscale x 2 x i1> zeroinitializer, <vscale x 4 x i32> %b)308 ret <vscale x 2 x double> %out309}310