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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52;RUN: opt -S -passes=instcombine < %s | FileCheck %s3target triple = "aarch64-unknown-linux-gnu"4 5 6define <16 x i8> @addqv_i8(<vscale x 16 x i8> %a) {7; CHECK-LABEL: define <16 x i8> @addqv_i8(8; CHECK-SAME: <vscale x 16 x i8> [[A:%.*]]) {9; CHECK-NEXT: ret <16 x i8> zeroinitializer10;11 %res = call <16 x i8> @llvm.aarch64.sve.addqv.v16i8.nxv16i8(<vscale x 16 x i1> zeroinitializer, <vscale x 16 x i8> %a);12 ret <16 x i8> %res13}14 15define <vscale x 4 x i1> @and_4(<vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd) {16; CHECK-LABEL: define <vscale x 4 x i1> @and_4(17; CHECK-SAME: <vscale x 4 x i1> [[PN:%.*]], <vscale x 4 x i1> [[PD:%.*]]) {18; CHECK-NEXT: ret <vscale x 4 x i1> zeroinitializer19;20 %res = call <vscale x 4 x i1> @llvm.aarch64.sve.and.z.nxv4i1(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd)21 ret <vscale x 4 x i1> %res;22}23 24define <vscale x 16 x i1> @bic_16(<vscale x 16 x i1> %Pn, <vscale x 16 x i1> %Pd) {25; CHECK-LABEL: define <vscale x 16 x i1> @bic_16(26; CHECK-SAME: <vscale x 16 x i1> [[PN:%.*]], <vscale x 16 x i1> [[PD:%.*]]) {27; CHECK-NEXT: ret <vscale x 16 x i1> zeroinitializer28;29 %res = call <vscale x 16 x i1> @llvm.aarch64.sve.bic.z.nxv16i1(<vscale x 16 x i1> zeroinitializer, <vscale x 16 x i1> %Pn, <vscale x 16 x i1> %Pd)30 ret <vscale x 16 x i1> %res;31}32 33define <vscale x 16 x i1> @brka_z_b8(<vscale x 16 x i1> %a) {34; CHECK-LABEL: define <vscale x 16 x i1> @brka_z_b8(35; CHECK-SAME: <vscale x 16 x i1> [[A:%.*]]) {36; CHECK-NEXT: ret <vscale x 16 x i1> zeroinitializer37;38 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1> zeroinitializer, <vscale x 16 x i1> %a)39 ret <vscale x 16 x i1> %out40}41 42define <vscale x 16 x i1> @brkb_z_b8(<vscale x 16 x i1> %a) {43; CHECK-LABEL: define <vscale x 16 x i1> @brkb_z_b8(44; CHECK-SAME: <vscale x 16 x i1> [[A:%.*]]) {45; CHECK-NEXT: ret <vscale x 16 x i1> zeroinitializer46;47 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1> zeroinitializer, <vscale x 16 x i1> %a)48 ret <vscale x 16 x i1> %out49}50 51define <vscale x 16 x i1> @brkn_b8(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {52; CHECK-LABEL: define <vscale x 16 x i1> @brkn_b8(53; CHECK-SAME: <vscale x 16 x i1> [[A:%.*]], <vscale x 16 x i1> [[B:%.*]]) {54; CHECK-NEXT: ret <vscale x 16 x i1> zeroinitializer55;56 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1> zeroinitializer, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)57 ret <vscale x 16 x i1> %out58}59 60define <vscale x 16 x i1> @brkpa_b8(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {61; CHECK-LABEL: define <vscale x 16 x i1> @brkpa_b8(62; CHECK-SAME: <vscale x 16 x i1> [[A:%.*]], <vscale x 16 x i1> [[B:%.*]]) {63; CHECK-NEXT: ret <vscale x 16 x i1> zeroinitializer64;65 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1> zeroinitializer, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)66 ret <vscale x 16 x i1> %out67}68 69define <vscale x 16 x i1> @brkpb_b8(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {70; CHECK-LABEL: define <vscale x 16 x i1> @brkpb_b8(71; CHECK-SAME: <vscale x 16 x i1> [[A:%.*]], <vscale x 16 x i1> [[B:%.*]]) {72; CHECK-NEXT: ret <vscale x 16 x i1> zeroinitializer73;74 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1> zeroinitializer, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)75 ret <vscale x 16 x i1> %out76}77 78define i64 @cntp_b64(<vscale x 2 x i1> %a) {79; CHECK-LABEL: define i64 @cntp_b64(80; CHECK-SAME: <vscale x 2 x i1> [[A:%.*]]) {81; CHECK-NEXT: ret i64 082;83; USE_SCALAR_INC-LABEL: cntp_b64:84; USE_SCALAR_INC: // %bb.0:85; USE_SCALAR_INC-NEXT: cntp x0, p0, p1.d86; USE_SCALAR_INC-NEXT: ret87 %out = call i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1> zeroinitializer, <vscale x 2 x i1> %a)88 ret i64 %out89}90 91define <vscale x 4 x i32> @compact_i32(<vscale x 4 x i32> %a) {92; CHECK-LABEL: define <vscale x 4 x i32> @compact_i32(93; CHECK-SAME: <vscale x 4 x i32> [[A:%.*]]) {94; CHECK-NEXT: ret <vscale x 4 x i32> zeroinitializer95;96 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.compact.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a)97 ret <vscale x 4 x i32> %out98}99 100define <vscale x 16 x i1> @eor_16(<vscale x 16 x i1> %Pn, <vscale x 16 x i1> %Pd) {101; CHECK-LABEL: define <vscale x 16 x i1> @eor_16(102; CHECK-SAME: <vscale x 16 x i1> [[PN:%.*]], <vscale x 16 x i1> [[PD:%.*]]) {103; CHECK-NEXT: ret <vscale x 16 x i1> zeroinitializer104;105 %res = call <vscale x 16 x i1> @llvm.aarch64.sve.eor.z.nxv16i1(<vscale x 16 x i1> zeroinitializer, <vscale x 16 x i1> %Pn, <vscale x 16 x i1> %Pd)106 ret <vscale x 16 x i1> %res;107}108 109define i32 @eorv_i32(<vscale x 4 x i32> %a) {110; CHECK-LABEL: define i32 @eorv_i32(111; CHECK-SAME: <vscale x 4 x i32> [[A:%.*]]) {112; CHECK-NEXT: ret i32 0113;114 %out = call i32 @llvm.aarch64.sve.eorv.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a)115 ret i32 %out116}117 118define <4 x i32> @eorqv_i32(<vscale x 4 x i32> %a) {119; CHECK-LABEL: define <4 x i32> @eorqv_i32(120; CHECK-SAME: <vscale x 4 x i32> [[A:%.*]]) {121; CHECK-NEXT: ret <4 x i32> zeroinitializer122;123 %res = call <4 x i32> @llvm.aarch64.sve.eorqv.v4i32.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a);124 ret <4 x i32> %res125}126 127define <vscale x 8 x i1> @nand_8(<vscale x 8 x i1> %Pn, <vscale x 8 x i1> %Pd) {128; CHECK-LABEL: define <vscale x 8 x i1> @nand_8(129; CHECK-SAME: <vscale x 8 x i1> [[PN:%.*]], <vscale x 8 x i1> [[PD:%.*]]) {130; CHECK-NEXT: ret <vscale x 8 x i1> zeroinitializer131;132 %res = call <vscale x 8 x i1> @llvm.aarch64.sve.nand.z.nxv8i1(<vscale x 8 x i1> zeroinitializer, <vscale x 8 x i1> %Pn, <vscale x 8 x i1> %Pd)133 ret <vscale x 8 x i1> %res;134}135 136define <vscale x 4 x i1> @nor_4(<vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd) {137; CHECK-LABEL: define <vscale x 4 x i1> @nor_4(138; CHECK-SAME: <vscale x 4 x i1> [[PN:%.*]], <vscale x 4 x i1> [[PD:%.*]]) {139; CHECK-NEXT: ret <vscale x 4 x i1> zeroinitializer140;141 %res = call <vscale x 4 x i1> @llvm.aarch64.sve.nor.z.nxv4i1(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd)142 ret <vscale x 4 x i1> %res;143}144 145define <vscale x 4 x i1> @orn_4(<vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd) {146; CHECK-LABEL: define <vscale x 4 x i1> @orn_4(147; CHECK-SAME: <vscale x 4 x i1> [[PN:%.*]], <vscale x 4 x i1> [[PD:%.*]]) {148; CHECK-NEXT: ret <vscale x 4 x i1> zeroinitializer149;150 %res = call <vscale x 4 x i1> @llvm.aarch64.sve.orn.z.nxv4i1(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i1> %Pn, <vscale x 4 x i1> %Pd)151 ret <vscale x 4 x i1> %res;152}153 154define <vscale x 2 x i1> @orr_2(<vscale x 2 x i1> %Pn, <vscale x 2 x i1> %Pd) {155; CHECK-LABEL: define <vscale x 2 x i1> @orr_2(156; CHECK-SAME: <vscale x 2 x i1> [[PN:%.*]], <vscale x 2 x i1> [[PD:%.*]]) {157; CHECK-NEXT: ret <vscale x 2 x i1> zeroinitializer158;159 %res = call <vscale x 2 x i1> @llvm.aarch64.sve.orr.z.nxv2i1(<vscale x 2 x i1> zeroinitializer, <vscale x 2 x i1> %Pn, <vscale x 2 x i1> %Pd)160 ret <vscale x 2 x i1> %res;161}162 163define i8 @orv_i8(<vscale x 16 x i8> %a) {164; CHECK-LABEL: define i8 @orv_i8(165; CHECK-SAME: <vscale x 16 x i8> [[A:%.*]]) {166; CHECK-NEXT: ret i8 0167;168 %out = call i8 @llvm.aarch64.sve.orv.nxv16i8(<vscale x 16 x i1> zeroinitializer, <vscale x 16 x i8> %a)169 ret i8 %out170}171 172define <8 x i16> @orqv_i16(<vscale x 8 x i16> %a) {173; CHECK-LABEL: define <8 x i16> @orqv_i16(174; CHECK-SAME: <vscale x 8 x i16> [[A:%.*]]) {175; CHECK-NEXT: ret <8 x i16> zeroinitializer176;177 %res = call <8 x i16> @llvm.aarch64.sve.orqv.v8i16.nxv8i16(<vscale x 8 x i1> zeroinitializer, <vscale x 8 x i16> %a);178 ret <8 x i16> %res179}180 181define <vscale x 4 x i1> @pnext_b32(<vscale x 4 x i1> %a) {182; CHECK-LABEL: define <vscale x 4 x i1> @pnext_b32(183; CHECK-SAME: <vscale x 4 x i1> [[A:%.*]]) {184; CHECK-NEXT: ret <vscale x 4 x i1> zeroinitializer185;186 %out = call <vscale x 4 x i1> @llvm.aarch64.sve.pnext.nxv4i1(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i1> %a)187 ret <vscale x 4 x i1> %out188}189 190define <vscale x 16 x i1> @rdffr_z() {191; CHECK-LABEL: define <vscale x 16 x i1> @rdffr_z() {192; CHECK-NEXT: ret <vscale x 16 x i1> zeroinitializer193;194 %out = call <vscale x 16 x i1> @llvm.aarch64.sve.rdffr.z(<vscale x 16 x i1> zeroinitializer)195 ret <vscale x 16 x i1> %out196}197 198define i64 @saddv_i64(<vscale x 2 x i64> %a) {199; CHECK-LABEL: define i64 @saddv_i64(200; CHECK-SAME: <vscale x 2 x i64> [[A:%.*]]) {201; CHECK-NEXT: ret i64 0202;203 %out = call i64 @llvm.aarch64.sve.saddv.nxv2i64(<vscale x 2 x i1> zeroinitializer, <vscale x 2 x i64> %a)204 ret i64 %out205}206 207define i64 @uaddv_i8(<vscale x 16 x i8> %a) {208; CHECK-LABEL: define i64 @uaddv_i8(209; CHECK-SAME: <vscale x 16 x i8> [[A:%.*]]) {210; CHECK-NEXT: ret i64 0211;212 %out = call i64 @llvm.aarch64.sve.uaddv.nxv16i8(<vscale x 16 x i1> zeroinitializer, <vscale x 16 x i8> %a)213 ret i64 %out214}215 216define i8 @umaxv_i8(<vscale x 16 x i8> %a) {217; CHECK-LABEL: define i8 @umaxv_i8(218; CHECK-SAME: <vscale x 16 x i8> [[A:%.*]]) {219; CHECK-NEXT: ret i8 0220;221 %out = call i8 @llvm.aarch64.sve.umaxv.nxv16i8(<vscale x 16 x i1> zeroinitializer, <vscale x 16 x i8> %a)222 ret i8 %out223}224 225define <8 x i16> @umaxqv_i16(<vscale x 8 x i16> %a) {226; CHECK-LABEL: define <8 x i16> @umaxqv_i16(227; CHECK-SAME: <vscale x 8 x i16> [[A:%.*]]) {228; CHECK-NEXT: ret <8 x i16> zeroinitializer229;230 %res = call <8 x i16> @llvm.aarch64.sve.umaxqv.v8i16.nxv8i16(<vscale x 8 x i1> zeroinitializer, <vscale x 8 x i16> %a);231 ret <8 x i16> %res232}233