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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 22; RUN: opt -S -passes=instcombine < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6; Replace SVE merging intrinsics with their first operand when they take an all false predicate.7 8declare <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)9define <vscale x 4 x i32> @simplify_abs_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {10; CHECK-LABEL: define <vscale x 4 x i32> @simplify_abs_intrinsic11; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {12; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[B]])13; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]14;15 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.abs.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %b)16 ret <vscale x 4 x i32> %r17}18 19declare <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)20define <vscale x 4 x i32> @simplify_add_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {21; CHECK-LABEL: define <vscale x 4 x i32> @simplify_add_intrinsic22; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1:[0-9]+]] {23; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]24;25 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)26 ret <vscale x 4 x i32> %r27}28 29declare <vscale x 4 x i32> @llvm.aarch64.sve.addp.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)30define <vscale x 4 x i32> @simplify_addp_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {31; CHECK-LABEL: define <vscale x 4 x i32> @simplify_addp_intrinsic32; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {33; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.addp.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])34; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]35;36 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.addp.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)37 ret <vscale x 4 x i32> %r38}39 40declare <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)41define <vscale x 4 x i32> @simplify_and_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {42; CHECK-LABEL: define <vscale x 4 x i32> @simplify_and_intrinsic43; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {44; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]45;46 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)47 ret <vscale x 4 x i32> %r48}49 50declare <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)51define <vscale x 4 x i32> @simplify_asr_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {52; CHECK-LABEL: define <vscale x 4 x i32> @simplify_asr_intrinsic53; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {54; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]55;56 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)57 ret <vscale x 4 x i32> %r58}59 60declare <vscale x 4 x i32> @llvm.aarch64.sve.bic.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)61define <vscale x 4 x i32> @simplify_bic_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {62; CHECK-LABEL: define <vscale x 4 x i32> @simplify_bic_intrinsic63; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {64; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]65;66 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.bic.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)67 ret <vscale x 4 x i32> %r68}69 70declare <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)71define <vscale x 4 x i32> @simplify_cls_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {72; CHECK-LABEL: define <vscale x 4 x i32> @simplify_cls_intrinsic73; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {74; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[B]])75; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]76;77 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cls.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %b)78 ret <vscale x 4 x i32> %r79}80 81declare <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)82define <vscale x 4 x i32> @simplify_clz_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {83; CHECK-LABEL: define <vscale x 4 x i32> @simplify_clz_intrinsic84; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {85; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[B]])86; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]87;88 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %b)89 ret <vscale x 4 x i32> %r90}91 92declare <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)93define <vscale x 4 x i32> @simplify_cnot_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {94; CHECK-LABEL: define <vscale x 4 x i32> @simplify_cnot_intrinsic95; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {96; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[B]])97; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]98;99 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %b)100 ret <vscale x 4 x i32> %r101}102 103declare <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)104define <vscale x 4 x i32> @simplify_cnt_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {105; CHECK-LABEL: define <vscale x 4 x i32> @simplify_cnt_intrinsic106; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {107; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[B]])108; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]109;110 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnt.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %b)111 ret <vscale x 4 x i32> %r112}113 114declare <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)115define <vscale x 4 x i32> @simplify_eor_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {116; CHECK-LABEL: define <vscale x 4 x i32> @simplify_eor_intrinsic117; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {118; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]119;120 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)121 ret <vscale x 4 x i32> %r122}123 124declare <vscale x 4 x float> @llvm.aarch64.sve.fabd.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)125define <vscale x 4 x float> @simplify_fabd_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {126; CHECK-LABEL: define <vscale x 4 x float> @simplify_fabd_intrinsic127; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) #[[ATTR1]] {128; CHECK-NEXT: ret <vscale x 4 x float> [[A]]129;130 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fabd.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b)131 ret <vscale x 4 x float> %r132}133 134declare <vscale x 4 x float> @llvm.aarch64.sve.fabs.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>)135define <vscale x 4 x float> @simplify_fabs_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {136; CHECK-LABEL: define <vscale x 4 x float> @simplify_fabs_intrinsic137; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) {138; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fabs.nxv4f32(<vscale x 4 x float> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[B]])139; CHECK-NEXT: ret <vscale x 4 x float> [[R]]140;141 %r = tail call <vscale x 4 x float> @llvm.aarch64.sve.fabs.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %b)142 ret <vscale x 4 x float> %r143}144 145declare <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)146define <vscale x 4 x float> @simplify_fadd_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {147; CHECK-LABEL: define <vscale x 4 x float> @simplify_fadd_intrinsic148; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) #[[ATTR1]] {149; CHECK-NEXT: ret <vscale x 4 x float> [[A]]150;151 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b)152 ret <vscale x 4 x float> %r153}154 155declare <vscale x 4 x float> @llvm.aarch64.sve.faddp.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)156define <vscale x 4 x float> @simplify_faddp_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {157; CHECK-LABEL: define <vscale x 4 x float> @simplify_faddp_intrinsic158; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) #[[ATTR1]] {159; CHECK-NEXT: [[R:%.*]] = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.faddp.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[A]], <vscale x 4 x float> [[B]])160; CHECK-NEXT: ret <vscale x 4 x float> [[R]]161;162 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.faddp.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b)163 ret <vscale x 4 x float> %r164}165 166declare <vscale x 4 x float> @llvm.aarch64.sve.famax.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)167define <vscale x 4 x float> @simplify_famax_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {168; CHECK-LABEL: define <vscale x 4 x float> @simplify_famax_intrinsic169; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) #[[ATTR1]] {170; CHECK-NEXT: [[R:%.*]] = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.famax.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[A]], <vscale x 4 x float> [[B]])171; CHECK-NEXT: ret <vscale x 4 x float> [[R]]172;173 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.famax.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b)174 ret <vscale x 4 x float> %r175}176 177declare <vscale x 4 x float> @llvm.aarch64.sve.famin.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)178define <vscale x 4 x float> @simplify_famin_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {179; CHECK-LABEL: define <vscale x 4 x float> @simplify_famin_intrinsic180; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) #[[ATTR1]] {181; CHECK-NEXT: [[R:%.*]] = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.famin.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[A]], <vscale x 4 x float> [[B]])182; CHECK-NEXT: ret <vscale x 4 x float> [[R]]183;184 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.famin.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b)185 ret <vscale x 4 x float> %r186}187 188declare <vscale x 4 x float> @llvm.aarch64.sve.fdiv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)189define <vscale x 4 x float> @simplify_fdiv_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {190; CHECK-LABEL: define <vscale x 4 x float> @simplify_fdiv_intrinsic191; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) #[[ATTR1]] {192; CHECK-NEXT: ret <vscale x 4 x float> [[A]]193;194 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fdiv.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b)195 ret <vscale x 4 x float> %r196}197 198declare <vscale x 4 x float> @llvm.aarch64.sve.fdivr.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)199define <vscale x 4 x float> @simplify_fdivr_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {200; CHECK-LABEL: define <vscale x 4 x float> @simplify_fdivr_intrinsic201; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) #[[ATTR1]] {202; CHECK-NEXT: [[R:%.*]] = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fdivr.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[A]], <vscale x 4 x float> [[B]])203; CHECK-NEXT: ret <vscale x 4 x float> [[R]]204;205 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fdivr.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b)206 ret <vscale x 4 x float> %r207}208 209declare <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x float>)210define <vscale x 4 x i32> @simplify_flogb_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x float> %b) {211; CHECK-LABEL: define <vscale x 4 x i32> @simplify_flogb_intrinsic212; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) {213; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[B]])214; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]215;216 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %b)217 ret <vscale x 4 x i32> %r218}219 220declare <vscale x 4 x float> @llvm.aarch64.sve.fmad.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)221define <vscale x 4 x float> @simplify_fmad_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c) #0 {222; CHECK-LABEL: define <vscale x 4 x float> @simplify_fmad_intrinsic223; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]], <vscale x 4 x float> [[C:%.*]]) #[[ATTR1]] {224; CHECK-NEXT: [[R:%.*]] = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fmad.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[A]], <vscale x 4 x float> [[B]], <vscale x 4 x float> [[C]])225; CHECK-NEXT: ret <vscale x 4 x float> [[R]]226;227 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fmad.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c)228 ret <vscale x 4 x float> %r229}230 231declare <vscale x 4 x float> @llvm.aarch64.sve.fmax.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)232define <vscale x 4 x float> @simplify_fmax_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {233; CHECK-LABEL: define <vscale x 4 x float> @simplify_fmax_intrinsic234; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) #[[ATTR1]] {235; CHECK-NEXT: ret <vscale x 4 x float> [[A]]236;237 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fmax.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b)238 ret <vscale x 4 x float> %r239}240 241declare <vscale x 4 x float> @llvm.aarch64.sve.fmaxp.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)242define <vscale x 4 x float> @simplify_fmaxp_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {243; CHECK-LABEL: define <vscale x 4 x float> @simplify_fmaxp_intrinsic244; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) #[[ATTR1]] {245; CHECK-NEXT: [[R:%.*]] = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fmaxp.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[A]], <vscale x 4 x float> [[B]])246; CHECK-NEXT: ret <vscale x 4 x float> [[R]]247;248 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fmaxp.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b)249 ret <vscale x 4 x float> %r250}251 252declare <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)253define <vscale x 4 x float> @simplify_fmaxnm_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {254; CHECK-LABEL: define <vscale x 4 x float> @simplify_fmaxnm_intrinsic255; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) #[[ATTR1]] {256; CHECK-NEXT: ret <vscale x 4 x float> [[A]]257;258 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b)259 ret <vscale x 4 x float> %r260}261 262declare <vscale x 4 x float> @llvm.aarch64.sve.fmaxnmp.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)263define <vscale x 4 x float> @simplify_fmaxnmp_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {264; CHECK-LABEL: define <vscale x 4 x float> @simplify_fmaxnmp_intrinsic265; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) #[[ATTR1]] {266; CHECK-NEXT: [[R:%.*]] = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fmaxnmp.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[A]], <vscale x 4 x float> [[B]])267; CHECK-NEXT: ret <vscale x 4 x float> [[R]]268;269 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fmaxnmp.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b)270 ret <vscale x 4 x float> %r271}272 273declare <vscale x 4 x float> @llvm.aarch64.sve.fmin.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)274define <vscale x 4 x float> @simplify_fmin_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {275; CHECK-LABEL: define <vscale x 4 x float> @simplify_fmin_intrinsic276; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) #[[ATTR1]] {277; CHECK-NEXT: ret <vscale x 4 x float> [[A]]278;279 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fmin.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b)280 ret <vscale x 4 x float> %r281}282 283declare <vscale x 4 x float> @llvm.aarch64.sve.fminp.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)284define <vscale x 4 x float> @simplify_fminp_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {285; CHECK-LABEL: define <vscale x 4 x float> @simplify_fminp_intrinsic286; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) #[[ATTR1]] {287; CHECK-NEXT: [[R:%.*]] = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fminp.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[A]], <vscale x 4 x float> [[B]])288; CHECK-NEXT: ret <vscale x 4 x float> [[R]]289;290 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fminp.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b)291 ret <vscale x 4 x float> %r292}293 294declare <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)295define <vscale x 4 x float> @simplify_fminnm_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {296; CHECK-LABEL: define <vscale x 4 x float> @simplify_fminnm_intrinsic297; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) #[[ATTR1]] {298; CHECK-NEXT: ret <vscale x 4 x float> [[A]]299;300 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b)301 ret <vscale x 4 x float> %r302}303 304declare <vscale x 4 x float> @llvm.aarch64.sve.fminnmp.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)305define <vscale x 4 x float> @simplify_fminnmp_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {306; CHECK-LABEL: define <vscale x 4 x float> @simplify_fminnmp_intrinsic307; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) #[[ATTR1]] {308; CHECK-NEXT: [[R:%.*]] = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fminnmp.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[A]], <vscale x 4 x float> [[B]])309; CHECK-NEXT: ret <vscale x 4 x float> [[R]]310;311 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fminnmp.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b)312 ret <vscale x 4 x float> %r313}314 315declare <vscale x 4 x float> @llvm.aarch64.sve.fmla.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)316define <vscale x 4 x float> @simplify_fmla_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c) #0 {317; CHECK-LABEL: define <vscale x 4 x float> @simplify_fmla_intrinsic318; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]], <vscale x 4 x float> [[C:%.*]]) #[[ATTR1]] {319; CHECK-NEXT: ret <vscale x 4 x float> [[A]]320;321 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fmla.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c)322 ret <vscale x 4 x float> %r323}324 325declare <vscale x 4 x float> @llvm.aarch64.sve.fmls.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)326define <vscale x 4 x float> @simplify_fmls_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c) #0 {327; CHECK-LABEL: define <vscale x 4 x float> @simplify_fmls_intrinsic328; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]], <vscale x 4 x float> [[C:%.*]]) #[[ATTR1]] {329; CHECK-NEXT: ret <vscale x 4 x float> [[A]]330;331 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fmls.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c)332 ret <vscale x 4 x float> %r333}334 335declare <vscale x 4 x float> @llvm.aarch64.sve.fmsb.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)336define <vscale x 4 x float> @simplify_fmsb_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c) #0 {337; CHECK-LABEL: define <vscale x 4 x float> @simplify_fmsb_intrinsic338; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]], <vscale x 4 x float> [[C:%.*]]) #[[ATTR1]] {339; CHECK-NEXT: [[R:%.*]] = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fmsb.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[A]], <vscale x 4 x float> [[B]], <vscale x 4 x float> [[C]])340; CHECK-NEXT: ret <vscale x 4 x float> [[R]]341;342 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fmsb.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c)343 ret <vscale x 4 x float> %r344}345 346declare <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)347define <vscale x 4 x float> @simplify_fmul_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {348; CHECK-LABEL: define <vscale x 4 x float> @simplify_fmul_intrinsic349; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) #[[ATTR1]] {350; CHECK-NEXT: ret <vscale x 4 x float> [[A]]351;352 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b)353 ret <vscale x 4 x float> %r354}355 356declare <vscale x 4 x float> @llvm.aarch64.sve.fmulx.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)357define <vscale x 4 x float> @simplify_fmulx_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {358; CHECK-LABEL: define <vscale x 4 x float> @simplify_fmulx_intrinsic359; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) #[[ATTR1]] {360; CHECK-NEXT: ret <vscale x 4 x float> [[A]]361;362 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fmulx.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b)363 ret <vscale x 4 x float> %r364}365 366declare <vscale x 4 x float> @llvm.aarch64.sve.fneg.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>)367define <vscale x 4 x float> @simplify_fneg_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {368; CHECK-LABEL: define <vscale x 4 x float> @simplify_fneg_intrinsic369; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) {370; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fneg.nxv4f32(<vscale x 4 x float> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[B]])371; CHECK-NEXT: ret <vscale x 4 x float> [[R]]372;373 %r = tail call <vscale x 4 x float> @llvm.aarch64.sve.fneg.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %b)374 ret <vscale x 4 x float> %r375}376 377declare <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)378define <vscale x 4 x float> @simplify_fnmad_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c) #0 {379; CHECK-LABEL: define <vscale x 4 x float> @simplify_fnmad_intrinsic380; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]], <vscale x 4 x float> [[C:%.*]]) #[[ATTR1]] {381; CHECK-NEXT: [[R:%.*]] = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[A]], <vscale x 4 x float> [[B]], <vscale x 4 x float> [[C]])382; CHECK-NEXT: ret <vscale x 4 x float> [[R]]383;384 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fnmad.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c)385 ret <vscale x 4 x float> %r386}387 388declare <vscale x 4 x float> @llvm.aarch64.sve.fnmla.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)389define <vscale x 4 x float> @simplify_fnmla_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c) #0 {390; CHECK-LABEL: define <vscale x 4 x float> @simplify_fnmla_intrinsic391; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]], <vscale x 4 x float> [[C:%.*]]) #[[ATTR1]] {392; CHECK-NEXT: ret <vscale x 4 x float> [[A]]393;394 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fnmla.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c)395 ret <vscale x 4 x float> %r396}397 398declare <vscale x 4 x float> @llvm.aarch64.sve.fnmls.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)399define <vscale x 4 x float> @simplify_fnmls_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c) #0 {400; CHECK-LABEL: define <vscale x 4 x float> @simplify_fnmls_intrinsic401; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]], <vscale x 4 x float> [[C:%.*]]) #[[ATTR1]] {402; CHECK-NEXT: ret <vscale x 4 x float> [[A]]403;404 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fnmls.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c)405 ret <vscale x 4 x float> %r406}407 408declare <vscale x 4 x float> @llvm.aarch64.sve.fnmsb.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)409define <vscale x 4 x float> @simplify_fnmsb_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c) #0 {410; CHECK-LABEL: define <vscale x 4 x float> @simplify_fnmsb_intrinsic411; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]], <vscale x 4 x float> [[C:%.*]]) #[[ATTR1]] {412; CHECK-NEXT: [[R:%.*]] = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fnmsb.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[A]], <vscale x 4 x float> [[B]], <vscale x 4 x float> [[C]])413; CHECK-NEXT: ret <vscale x 4 x float> [[R]]414;415 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fnmsb.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c)416 ret <vscale x 4 x float> %r417}418 419declare <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>)420define <vscale x 4 x float> @simplify_frecpx_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {421; CHECK-LABEL: define <vscale x 4 x float> @simplify_frecpx_intrinsic422; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) {423; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[B]])424; CHECK-NEXT: ret <vscale x 4 x float> [[R]]425;426 %r = tail call <vscale x 4 x float> @llvm.aarch64.sve.frecpx.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %b)427 ret <vscale x 4 x float> %r428}429 430declare <vscale x 4 x float> @llvm.aarch64.sve.frinta.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>)431define <vscale x 4 x float> @simplify_frinta_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {432; CHECK-LABEL: define <vscale x 4 x float> @simplify_frinta_intrinsic433; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) {434; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frinta.nxv4f32(<vscale x 4 x float> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[B]])435; CHECK-NEXT: ret <vscale x 4 x float> [[R]]436;437 %r = tail call <vscale x 4 x float> @llvm.aarch64.sve.frinta.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %b)438 ret <vscale x 4 x float> %r439}440 441declare <vscale x 4 x float> @llvm.aarch64.sve.frinti.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>)442define <vscale x 4 x float> @simplify_frinti_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {443; CHECK-LABEL: define <vscale x 4 x float> @simplify_frinti_intrinsic444; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) {445; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frinti.nxv4f32(<vscale x 4 x float> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[B]])446; CHECK-NEXT: ret <vscale x 4 x float> [[R]]447;448 %r = tail call <vscale x 4 x float> @llvm.aarch64.sve.frinti.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %b)449 ret <vscale x 4 x float> %r450}451 452declare <vscale x 4 x float> @llvm.aarch64.sve.frintm.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>)453define <vscale x 4 x float> @simplify_frintm_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {454; CHECK-LABEL: define <vscale x 4 x float> @simplify_frintm_intrinsic455; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) {456; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frintm.nxv4f32(<vscale x 4 x float> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[B]])457; CHECK-NEXT: ret <vscale x 4 x float> [[R]]458;459 %r = tail call <vscale x 4 x float> @llvm.aarch64.sve.frintm.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %b)460 ret <vscale x 4 x float> %r461}462 463declare <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>)464define <vscale x 4 x float> @simplify_frintn_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {465; CHECK-LABEL: define <vscale x 4 x float> @simplify_frintn_intrinsic466; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) {467; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[B]])468; CHECK-NEXT: ret <vscale x 4 x float> [[R]]469;470 %r = tail call <vscale x 4 x float> @llvm.aarch64.sve.frintn.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %b)471 ret <vscale x 4 x float> %r472}473 474declare <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>)475define <vscale x 4 x float> @simplify_frintp_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {476; CHECK-LABEL: define <vscale x 4 x float> @simplify_frintp_intrinsic477; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) {478; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[B]])479; CHECK-NEXT: ret <vscale x 4 x float> [[R]]480;481 %r = tail call <vscale x 4 x float> @llvm.aarch64.sve.frintp.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %b)482 ret <vscale x 4 x float> %r483}484 485declare <vscale x 4 x float> @llvm.aarch64.sve.frintx.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>)486define <vscale x 4 x float> @simplify_frintx_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {487; CHECK-LABEL: define <vscale x 4 x float> @simplify_frintx_intrinsic488; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) {489; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frintx.nxv4f32(<vscale x 4 x float> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[B]])490; CHECK-NEXT: ret <vscale x 4 x float> [[R]]491;492 %r = tail call <vscale x 4 x float> @llvm.aarch64.sve.frintx.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %b)493 ret <vscale x 4 x float> %r494}495 496declare <vscale x 4 x float> @llvm.aarch64.sve.frintz.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>)497define <vscale x 4 x float> @simplify_frintz_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {498; CHECK-LABEL: define <vscale x 4 x float> @simplify_frintz_intrinsic499; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) {500; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frintz.nxv4f32(<vscale x 4 x float> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[B]])501; CHECK-NEXT: ret <vscale x 4 x float> [[R]]502;503 %r = tail call <vscale x 4 x float> @llvm.aarch64.sve.frintz.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %b)504 ret <vscale x 4 x float> %r505}506 507declare <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>)508define <vscale x 4 x float> @simplify_fsqrt_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {509; CHECK-LABEL: define <vscale x 4 x float> @simplify_fsqrt_intrinsic510; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) {511; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[B]])512; CHECK-NEXT: ret <vscale x 4 x float> [[R]]513;514 %r = tail call <vscale x 4 x float> @llvm.aarch64.sve.fsqrt.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %b)515 ret <vscale x 4 x float> %r516}517 518declare <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)519define <vscale x 4 x float> @simplify_fsub_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {520; CHECK-LABEL: define <vscale x 4 x float> @simplify_fsub_intrinsic521; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) #[[ATTR1]] {522; CHECK-NEXT: ret <vscale x 4 x float> [[A]]523;524 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b)525 ret <vscale x 4 x float> %r526}527 528declare <vscale x 4 x float> @llvm.aarch64.sve.fsubr.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)529define <vscale x 4 x float> @simplify_fsubr_intrinsic(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {530; CHECK-LABEL: define <vscale x 4 x float> @simplify_fsubr_intrinsic531; CHECK-SAME: (<vscale x 4 x float> [[A:%.*]], <vscale x 4 x float> [[B:%.*]]) #[[ATTR1]] {532; CHECK-NEXT: [[R:%.*]] = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fsubr.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> [[A]], <vscale x 4 x float> [[B]])533; CHECK-NEXT: ret <vscale x 4 x float> [[R]]534;535 %r = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fsubr.nxv4f32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x float> %a, <vscale x 4 x float> %b)536 ret <vscale x 4 x float> %r537}538 539declare <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)540define <vscale x 4 x i32> @simplify_lsl_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {541; CHECK-LABEL: define <vscale x 4 x i32> @simplify_lsl_intrinsic542; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {543; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]544;545 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)546 ret <vscale x 4 x i32> %r547}548 549declare <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)550define <vscale x 4 x i32> @simplify_lsr_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {551; CHECK-LABEL: define <vscale x 4 x i32> @simplify_lsr_intrinsic552; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {553; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]554;555 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)556 ret <vscale x 4 x i32> %r557}558 559declare <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)560define <vscale x 4 x i32> @simplify_mad_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) #0 {561; CHECK-LABEL: define <vscale x 4 x i32> @simplify_mad_intrinsic562; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]], <vscale x 4 x i32> [[C:%.*]]) #[[ATTR1]] {563; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]], <vscale x 4 x i32> [[C]])564; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]565;566 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.mad.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c)567 ret <vscale x 4 x i32> %r568}569 570declare <vscale x 4 x i32> @llvm.aarch64.sve.mla.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)571define <vscale x 4 x i32> @simplify_mla_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) #0 {572; CHECK-LABEL: define <vscale x 4 x i32> @simplify_mla_intrinsic573; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]], <vscale x 4 x i32> [[C:%.*]]) #[[ATTR1]] {574; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]575;576 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.mla.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c)577 ret <vscale x 4 x i32> %r578}579 580declare <vscale x 4 x i32> @llvm.aarch64.sve.mls.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)581define <vscale x 4 x i32> @simplify_mls_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) #0 {582; CHECK-LABEL: define <vscale x 4 x i32> @simplify_mls_intrinsic583; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]], <vscale x 4 x i32> [[C:%.*]]) #[[ATTR1]] {584; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]585;586 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.mls.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c)587 ret <vscale x 4 x i32> %r588}589 590declare <vscale x 4 x i32> @llvm.aarch64.sve.msb.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)591define <vscale x 4 x i32> @simplify_msb_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) #0 {592; CHECK-LABEL: define <vscale x 4 x i32> @simplify_msb_intrinsic593; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]], <vscale x 4 x i32> [[C:%.*]]) #[[ATTR1]] {594; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.msb.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]], <vscale x 4 x i32> [[C]])595; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]596;597 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.msb.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c)598 ret <vscale x 4 x i32> %r599}600 601declare <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)602define <vscale x 4 x i32> @simplify_mul_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {603; CHECK-LABEL: define <vscale x 4 x i32> @simplify_mul_intrinsic604; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {605; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]606;607 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)608 ret <vscale x 4 x i32> %r609}610 611declare <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)612define <vscale x 4 x i32> @simplify_neg_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {613; CHECK-LABEL: define <vscale x 4 x i32> @simplify_neg_intrinsic614; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {615; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[B]])616; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]617;618 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.neg.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %b)619 ret <vscale x 4 x i32> %r620}621 622declare <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)623define <vscale x 4 x i32> @simplify_not_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {624; CHECK-LABEL: define <vscale x 4 x i32> @simplify_not_intrinsic625; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {626; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[B]])627; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]628;629 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.not.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %b)630 ret <vscale x 4 x i32> %r631}632 633declare <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)634define <vscale x 4 x i32> @simplify_orr_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {635; CHECK-LABEL: define <vscale x 4 x i32> @simplify_orr_intrinsic636; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {637; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]638;639 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)640 ret <vscale x 4 x i32> %r641}642 643declare <vscale x 4 x i32> @llvm.aarch64.sve.rbit.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)644define <vscale x 4 x i32> @simplify_rbit_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {645; CHECK-LABEL: define <vscale x 4 x i32> @simplify_rbit_intrinsic646; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {647; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.rbit.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[B]])648; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]649;650 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.rbit.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %b)651 ret <vscale x 4 x i32> %r652}653 654declare <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)655define <vscale x 4 x i32> @simplify_revb_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {656; CHECK-LABEL: define <vscale x 4 x i32> @simplify_revb_intrinsic657; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {658; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[B]])659; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]660;661 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %b)662 ret <vscale x 4 x i32> %r663}664 665declare <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)666define <vscale x 4 x i32> @simplify_revh_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {667; CHECK-LABEL: define <vscale x 4 x i32> @simplify_revh_intrinsic668; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {669; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[B]])670; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]671;672 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %b)673 ret <vscale x 4 x i32> %r674}675 676declare <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)677define <vscale x 2 x i64> @simplify_revw_intrinsic(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {678; CHECK-LABEL: define <vscale x 2 x i64> @simplify_revw_intrinsic679; CHECK-SAME: (<vscale x 2 x i64> [[A:%.*]], <vscale x 2 x i64> [[B:%.*]]) {680; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> [[A]], <vscale x 2 x i1> zeroinitializer, <vscale x 2 x i64> [[B]])681; CHECK-NEXT: ret <vscale x 2 x i64> [[R]]682;683 %r = tail call <vscale x 2 x i64> @llvm.aarch64.sve.revw.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> zeroinitializer, <vscale x 2 x i64> %b)684 ret <vscale x 2 x i64> %r685}686 687declare <vscale x 4 x i32> @llvm.aarch64.sve.revd.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)688define <vscale x 4 x i32> @simplify_revd_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {689; CHECK-LABEL: define <vscale x 4 x i32> @simplify_revd_intrinsic690; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {691; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.revd.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[B]])692; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]693;694 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.revd.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %b)695 ret <vscale x 4 x i32> %r696}697 698declare <vscale x 4 x i32> @llvm.aarch64.sve.sabd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)699define <vscale x 4 x i32> @simplify_sabd_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {700; CHECK-LABEL: define <vscale x 4 x i32> @simplify_sabd_intrinsic701; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {702; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]703;704 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sabd.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)705 ret <vscale x 4 x i32> %r706}707 708declare <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)709define <vscale x 4 x i32> @simplify_sdiv_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {710; CHECK-LABEL: define <vscale x 4 x i32> @simplify_sdiv_intrinsic711; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {712; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]713;714 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)715 ret <vscale x 4 x i32> %r716}717 718declare <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)719define <vscale x 4 x i32> @simplify_sdivr_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {720; CHECK-LABEL: define <vscale x 4 x i32> @simplify_sdivr_intrinsic721; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {722; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])723; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]724;725 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)726 ret <vscale x 4 x i32> %r727}728 729declare <vscale x 4 x i32> @llvm.aarch64.sve.shadd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)730define <vscale x 4 x i32> @simplify_shadd_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {731; CHECK-LABEL: define <vscale x 4 x i32> @simplify_shadd_intrinsic732; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {733; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.shadd.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])734; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]735;736 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.shadd.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)737 ret <vscale x 4 x i32> %r738}739 740declare <vscale x 4 x i32> @llvm.aarch64.sve.shsub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)741define <vscale x 4 x i32> @simplify_shsub_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {742; CHECK-LABEL: define <vscale x 4 x i32> @simplify_shsub_intrinsic743; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {744; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.shsub.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])745; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]746;747 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.shsub.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)748 ret <vscale x 4 x i32> %r749}750 751declare <vscale x 4 x i32> @llvm.aarch64.sve.shsubr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)752define <vscale x 4 x i32> @simplify_shsubr_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {753; CHECK-LABEL: define <vscale x 4 x i32> @simplify_shsubr_intrinsic754; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {755; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.shsubr.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])756; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]757;758 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.shsubr.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)759 ret <vscale x 4 x i32> %r760}761 762declare <vscale x 4 x i32> @llvm.aarch64.sve.smax.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)763define <vscale x 4 x i32> @simplify_smax_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {764; CHECK-LABEL: define <vscale x 4 x i32> @simplify_smax_intrinsic765; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {766; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]767;768 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smax.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)769 ret <vscale x 4 x i32> %r770}771 772declare <vscale x 4 x i32> @llvm.aarch64.sve.smaxp.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)773define <vscale x 4 x i32> @simplify_smaxp_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {774; CHECK-LABEL: define <vscale x 4 x i32> @simplify_smaxp_intrinsic775; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {776; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smaxp.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])777; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]778;779 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smaxp.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)780 ret <vscale x 4 x i32> %r781}782 783declare <vscale x 4 x i32> @llvm.aarch64.sve.smin.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)784define <vscale x 4 x i32> @simplify_smin_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {785; CHECK-LABEL: define <vscale x 4 x i32> @simplify_smin_intrinsic786; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {787; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]788;789 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smin.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)790 ret <vscale x 4 x i32> %r791}792 793declare <vscale x 4 x i32> @llvm.aarch64.sve.sminp.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)794define <vscale x 4 x i32> @simplify_sminp_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {795; CHECK-LABEL: define <vscale x 4 x i32> @simplify_sminp_intrinsic796; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {797; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sminp.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])798; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]799;800 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sminp.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)801 ret <vscale x 4 x i32> %r802}803 804declare <vscale x 4 x i32> @llvm.aarch64.sve.smulh.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)805define <vscale x 4 x i32> @simplify_smulh_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {806; CHECK-LABEL: define <vscale x 4 x i32> @simplify_smulh_intrinsic807; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {808; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]809;810 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smulh.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)811 ret <vscale x 4 x i32> %r812}813 814declare <vscale x 4 x i32> @llvm.aarch64.sve.sqabs.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)815define <vscale x 4 x i32> @simplify_sqabs_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {816; CHECK-LABEL: define <vscale x 4 x i32> @simplify_sqabs_intrinsic817; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {818; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqabs.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[B]])819; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]820;821 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqabs.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %b)822 ret <vscale x 4 x i32> %r823}824 825declare <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)826define <vscale x 4 x i32> @simplify_sqadd_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {827; CHECK-LABEL: define <vscale x 4 x i32> @simplify_sqadd_intrinsic828; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {829; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])830; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]831;832 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)833 ret <vscale x 4 x i32> %r834}835 836declare <vscale x 4 x i32> @llvm.aarch64.sve.sqneg.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)837define <vscale x 4 x i32> @simplify_sqneg_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {838; CHECK-LABEL: define <vscale x 4 x i32> @simplify_sqneg_intrinsic839; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {840; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqneg.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[B]])841; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]842;843 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqneg.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %b)844 ret <vscale x 4 x i32> %r845}846 847declare <vscale x 4 x i32> @llvm.aarch64.sve.sqrshl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)848define <vscale x 4 x i32> @simplify_sqrshl_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {849; CHECK-LABEL: define <vscale x 4 x i32> @simplify_sqrshl_intrinsic850; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {851; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqrshl.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])852; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]853;854 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqrshl.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)855 ret <vscale x 4 x i32> %r856}857 858declare <vscale x 4 x i32> @llvm.aarch64.sve.sqshl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)859define <vscale x 4 x i32> @simplify_sqshl_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {860; CHECK-LABEL: define <vscale x 4 x i32> @simplify_sqshl_intrinsic861; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {862; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqshl.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])863; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]864;865 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqshl.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)866 ret <vscale x 4 x i32> %r867}868 869declare <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)870define <vscale x 4 x i32> @simplify_sqsub_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {871; CHECK-LABEL: define <vscale x 4 x i32> @simplify_sqsub_intrinsic872; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {873; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]874;875 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)876 ret <vscale x 4 x i32> %r877}878 879declare <vscale x 4 x i32> @llvm.aarch64.sve.sqsubr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)880define <vscale x 4 x i32> @simplify_sqsubr_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {881; CHECK-LABEL: define <vscale x 4 x i32> @simplify_sqsubr_intrinsic882; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {883; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqsubr.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])884; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]885;886 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sqsubr.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)887 ret <vscale x 4 x i32> %r888}889 890declare <vscale x 4 x i32> @llvm.aarch64.sve.srhadd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)891define <vscale x 4 x i32> @simplify_srhadd_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {892; CHECK-LABEL: define <vscale x 4 x i32> @simplify_srhadd_intrinsic893; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {894; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.srhadd.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])895; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]896;897 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.srhadd.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)898 ret <vscale x 4 x i32> %r899}900 901declare <vscale x 4 x i32> @llvm.aarch64.sve.srshl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)902define <vscale x 4 x i32> @simplify_srshl_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {903; CHECK-LABEL: define <vscale x 4 x i32> @simplify_srshl_intrinsic904; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {905; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.srshl.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])906; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]907;908 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.srshl.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)909 ret <vscale x 4 x i32> %r910}911 912declare <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)913define <vscale x 4 x i32> @simplify_sub_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {914; CHECK-LABEL: define <vscale x 4 x i32> @simplify_sub_intrinsic915; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {916; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]917;918 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)919 ret <vscale x 4 x i32> %r920}921 922declare <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)923define <vscale x 4 x i32> @simplify_subr_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {924; CHECK-LABEL: define <vscale x 4 x i32> @simplify_subr_intrinsic925; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {926; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])927; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]928;929 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)930 ret <vscale x 4 x i32> %r931}932 933declare <vscale x 4 x i32> @llvm.aarch64.sve.suqadd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)934define <vscale x 4 x i32> @simplify_suqadd_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {935; CHECK-LABEL: define <vscale x 4 x i32> @simplify_suqadd_intrinsic936; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {937; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.suqadd.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])938; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]939;940 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.suqadd.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)941 ret <vscale x 4 x i32> %r942}943 944declare <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)945define <vscale x 4 x i32> @simplify_sxtb_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {946; CHECK-LABEL: define <vscale x 4 x i32> @simplify_sxtb_intrinsic947; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {948; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[B]])949; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]950;951 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sxtb.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %b)952 ret <vscale x 4 x i32> %r953}954 955declare <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)956define <vscale x 4 x i32> @simplify_sxth_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {957; CHECK-LABEL: define <vscale x 4 x i32> @simplify_sxth_intrinsic958; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {959; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[B]])960; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]961;962 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sxth.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %b)963 ret <vscale x 4 x i32> %r964}965 966declare <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)967define <vscale x 2 x i64> @simplify_sxtw_intrinsic(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {968; CHECK-LABEL: define <vscale x 2 x i64> @simplify_sxtw_intrinsic969; CHECK-SAME: (<vscale x 2 x i64> [[A:%.*]], <vscale x 2 x i64> [[B:%.*]]) {970; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> [[A]], <vscale x 2 x i1> zeroinitializer, <vscale x 2 x i64> [[B]])971; CHECK-NEXT: ret <vscale x 2 x i64> [[R]]972;973 %r = tail call <vscale x 2 x i64> @llvm.aarch64.sve.sxtw.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> zeroinitializer, <vscale x 2 x i64> %b)974 ret <vscale x 2 x i64> %r975}976 977declare <vscale x 4 x i32> @llvm.aarch64.sve.uabd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)978define <vscale x 4 x i32> @simplify_uabd_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {979; CHECK-LABEL: define <vscale x 4 x i32> @simplify_uabd_intrinsic980; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {981; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]982;983 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uabd.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)984 ret <vscale x 4 x i32> %r985}986 987declare <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)988define <vscale x 4 x i32> @simplify_udiv_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {989; CHECK-LABEL: define <vscale x 4 x i32> @simplify_udiv_intrinsic990; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {991; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]992;993 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)994 ret <vscale x 4 x i32> %r995}996 997declare <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)998define <vscale x 4 x i32> @simplify_udivr_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {999; CHECK-LABEL: define <vscale x 4 x i32> @simplify_udivr_intrinsic1000; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {1001; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])1002; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]1003;1004 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)1005 ret <vscale x 4 x i32> %r1006}1007 1008declare <vscale x 4 x i32> @llvm.aarch64.sve.uhadd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1009define <vscale x 4 x i32> @simplify_uhadd_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {1010; CHECK-LABEL: define <vscale x 4 x i32> @simplify_uhadd_intrinsic1011; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {1012; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uhadd.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])1013; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]1014;1015 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uhadd.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)1016 ret <vscale x 4 x i32> %r1017}1018 1019declare <vscale x 4 x i32> @llvm.aarch64.sve.uhsub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1020define <vscale x 4 x i32> @simplify_uhsub_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {1021; CHECK-LABEL: define <vscale x 4 x i32> @simplify_uhsub_intrinsic1022; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {1023; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uhsub.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])1024; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]1025;1026 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uhsub.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)1027 ret <vscale x 4 x i32> %r1028}1029 1030declare <vscale x 4 x i32> @llvm.aarch64.sve.uhsubr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1031define <vscale x 4 x i32> @simplify_uhsubr_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {1032; CHECK-LABEL: define <vscale x 4 x i32> @simplify_uhsubr_intrinsic1033; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {1034; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uhsubr.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])1035; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]1036;1037 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uhsubr.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)1038 ret <vscale x 4 x i32> %r1039}1040 1041declare <vscale x 4 x i32> @llvm.aarch64.sve.umax.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1042define <vscale x 4 x i32> @simplify_umax_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {1043; CHECK-LABEL: define <vscale x 4 x i32> @simplify_umax_intrinsic1044; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {1045; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]1046;1047 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umax.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)1048 ret <vscale x 4 x i32> %r1049}1050 1051declare <vscale x 4 x i32> @llvm.aarch64.sve.umaxp.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1052define <vscale x 4 x i32> @simplify_umaxp_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {1053; CHECK-LABEL: define <vscale x 4 x i32> @simplify_umaxp_intrinsic1054; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {1055; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umaxp.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])1056; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]1057;1058 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umaxp.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)1059 ret <vscale x 4 x i32> %r1060}1061 1062declare <vscale x 4 x i32> @llvm.aarch64.sve.umin.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1063define <vscale x 4 x i32> @simplify_umin_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {1064; CHECK-LABEL: define <vscale x 4 x i32> @simplify_umin_intrinsic1065; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {1066; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]1067;1068 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umin.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)1069 ret <vscale x 4 x i32> %r1070}1071 1072declare <vscale x 4 x i32> @llvm.aarch64.sve.uminp.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1073define <vscale x 4 x i32> @simplify_uminp_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {1074; CHECK-LABEL: define <vscale x 4 x i32> @simplify_uminp_intrinsic1075; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {1076; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uminp.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])1077; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]1078;1079 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uminp.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)1080 ret <vscale x 4 x i32> %r1081}1082 1083declare <vscale x 4 x i32> @llvm.aarch64.sve.umulh.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1084define <vscale x 4 x i32> @simplify_umulh_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {1085; CHECK-LABEL: define <vscale x 4 x i32> @simplify_umulh_intrinsic1086; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {1087; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]1088;1089 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umulh.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)1090 ret <vscale x 4 x i32> %r1091}1092 1093declare <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1094define <vscale x 4 x i32> @simplify_uqadd_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {1095; CHECK-LABEL: define <vscale x 4 x i32> @simplify_uqadd_intrinsic1096; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {1097; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])1098; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]1099;1100 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)1101 ret <vscale x 4 x i32> %r1102}1103 1104declare <vscale x 4 x i32> @llvm.aarch64.sve.uqrshl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1105define <vscale x 4 x i32> @simplify_uqrshl_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {1106; CHECK-LABEL: define <vscale x 4 x i32> @simplify_uqrshl_intrinsic1107; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {1108; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uqrshl.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])1109; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]1110;1111 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uqrshl.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)1112 ret <vscale x 4 x i32> %r1113}1114 1115declare <vscale x 4 x i32> @llvm.aarch64.sve.uqshl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1116define <vscale x 4 x i32> @simplify_uqshl_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {1117; CHECK-LABEL: define <vscale x 4 x i32> @simplify_uqshl_intrinsic1118; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {1119; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uqshl.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])1120; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]1121;1122 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uqshl.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)1123 ret <vscale x 4 x i32> %r1124}1125 1126declare <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1127define <vscale x 4 x i32> @simplify_uqsub_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {1128; CHECK-LABEL: define <vscale x 4 x i32> @simplify_uqsub_intrinsic1129; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {1130; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]1131;1132 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)1133 ret <vscale x 4 x i32> %r1134}1135 1136declare <vscale x 4 x i32> @llvm.aarch64.sve.uqsubr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1137define <vscale x 4 x i32> @simplify_uqsubr_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {1138; CHECK-LABEL: define <vscale x 4 x i32> @simplify_uqsubr_intrinsic1139; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {1140; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uqsubr.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])1141; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]1142;1143 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uqsubr.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)1144 ret <vscale x 4 x i32> %r1145}1146 1147declare <vscale x 4 x i32> @llvm.aarch64.sve.urecpe.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)1148define <vscale x 4 x i32> @simplify_urecpe_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {1149; CHECK-LABEL: define <vscale x 4 x i32> @simplify_urecpe_intrinsic1150; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {1151; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.urecpe.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[B]])1152; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]1153;1154 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.urecpe.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %b)1155 ret <vscale x 4 x i32> %r1156}1157 1158declare <vscale x 4 x i32> @llvm.aarch64.sve.urhadd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1159define <vscale x 4 x i32> @simplify_urhadd_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {1160; CHECK-LABEL: define <vscale x 4 x i32> @simplify_urhadd_intrinsic1161; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {1162; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.urhadd.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])1163; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]1164;1165 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.urhadd.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)1166 ret <vscale x 4 x i32> %r1167}1168 1169declare <vscale x 4 x i32> @llvm.aarch64.sve.urshl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1170define <vscale x 4 x i32> @simplify_urshl_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {1171; CHECK-LABEL: define <vscale x 4 x i32> @simplify_urshl_intrinsic1172; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {1173; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.urshl.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])1174; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]1175;1176 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.urshl.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)1177 ret <vscale x 4 x i32> %r1178}1179 1180declare <vscale x 4 x i32> @llvm.aarch64.sve.ursqrte.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)1181define <vscale x 4 x i32> @simplify_ursqrte_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {1182; CHECK-LABEL: define <vscale x 4 x i32> @simplify_ursqrte_intrinsic1183; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {1184; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.ursqrte.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[B]])1185; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]1186;1187 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.ursqrte.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %b)1188 ret <vscale x 4 x i32> %r1189}1190 1191declare <vscale x 4 x i32> @llvm.aarch64.sve.usqadd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)1192define <vscale x 4 x i32> @simplify_usqadd_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {1193; CHECK-LABEL: define <vscale x 4 x i32> @simplify_usqadd_intrinsic1194; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR1]] {1195; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.usqadd.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]])1196; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]1197;1198 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.usqadd.nxv4i32(<vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)1199 ret <vscale x 4 x i32> %r1200}1201 1202declare <vscale x 4 x i32> @llvm.aarch64.sve.uxtb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)1203define <vscale x 4 x i32> @simplify_uxtb_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {1204; CHECK-LABEL: define <vscale x 4 x i32> @simplify_uxtb_intrinsic1205; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {1206; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uxtb.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[B]])1207; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]1208;1209 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uxtb.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %b)1210 ret <vscale x 4 x i32> %r1211}1212 1213declare <vscale x 4 x i32> @llvm.aarch64.sve.uxth.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)1214define <vscale x 4 x i32> @simplify_uxth_intrinsic(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {1215; CHECK-LABEL: define <vscale x 4 x i32> @simplify_uxth_intrinsic1216; CHECK-SAME: (<vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) {1217; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uxth.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> [[B]])1218; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]1219;1220 %r = tail call <vscale x 4 x i32> @llvm.aarch64.sve.uxth.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> %b)1221 ret <vscale x 4 x i32> %r1222}1223 1224declare <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)1225define <vscale x 2 x i64> @simplify_uxtw_intrinsic(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {1226; CHECK-LABEL: define <vscale x 2 x i64> @simplify_uxtw_intrinsic1227; CHECK-SAME: (<vscale x 2 x i64> [[A:%.*]], <vscale x 2 x i64> [[B:%.*]]) {1228; CHECK-NEXT: [[R:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> [[A]], <vscale x 2 x i1> zeroinitializer, <vscale x 2 x i64> [[B]])1229; CHECK-NEXT: ret <vscale x 2 x i64> [[R]]1230;1231 %r = tail call <vscale x 2 x i64> @llvm.aarch64.sve.uxtw.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> zeroinitializer, <vscale x 2 x i64> %b)1232 ret <vscale x 2 x i64> %r1233}1234 1235attributes #0 = { "target-features"="+sve" }1236