220 lines · plain
1; RUN: opt -S -passes=instcombine < %s | FileCheck %s2 3target triple = "aarch64-unknown-linux-gnu"4 5declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32)6declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32)7declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32)8 9; SVE intrinsics fmul, fmul_u, fadd, fadd_u, fsub and fsub_u should be replaced with regular fmul, fadd and fsub.10declare <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)11define <vscale x 8 x half> @replace_fmul_intrinsic_half(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {12; CHECK-LABEL: @replace_fmul_intrinsic_half13; CHECK-NEXT: %1 = fmul fast <vscale x 8 x half> %a, %b14; CHECK-NEXT: ret <vscale x 8 x half> %115 %1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)16 %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1> %1, <vscale x 8 x half> %a, <vscale x 8 x half> %b)17 ret <vscale x 8 x half> %218}19 20declare <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)21define <vscale x 4 x float> @replace_fmul_intrinsic_float(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {22; CHECK-LABEL: @replace_fmul_intrinsic_float23; CHECK-NEXT: %1 = fmul fast <vscale x 4 x float> %a, %b24; CHECK-NEXT: ret <vscale x 4 x float> %125 %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)26 %2 = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4f32(<vscale x 4 x i1> %1, <vscale x 4 x float> %a, <vscale x 4 x float> %b)27 ret <vscale x 4 x float> %228}29 30declare <vscale x 2 x double> @llvm.aarch64.sve.fmul.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)31define <vscale x 2 x double> @replace_fmul_intrinsic_double(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {32; CHECK-LABEL: @replace_fmul_intrinsic_double33; CHECK-NEXT: %1 = fmul fast <vscale x 2 x double> %a, %b34; CHECK-NEXT: ret <vscale x 2 x double> %135 %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)36 %2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.fmul.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)37 ret <vscale x 2 x double> %238}39 40declare <vscale x 8 x half> @llvm.aarch64.sve.fmul.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)41define <vscale x 8 x half> @replace_fmul_u_intrinsic_half(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {42; CHECK-LABEL: @replace_fmul_u_intrinsic_half43; CHECK-NEXT: %1 = fmul fast <vscale x 8 x half> %a, %b44; CHECK-NEXT: ret <vscale x 8 x half> %145 %1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)46 %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.u.nxv8f16(<vscale x 8 x i1> %1, <vscale x 8 x half> %a, <vscale x 8 x half> %b)47 ret <vscale x 8 x half> %248}49 50declare <vscale x 4 x float> @llvm.aarch64.sve.fmul.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)51define <vscale x 4 x float> @replace_fmul_u_intrinsic_float(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {52; CHECK-LABEL: @replace_fmul_u_intrinsic_float53; CHECK-NEXT: %1 = fmul fast <vscale x 4 x float> %a, %b54; CHECK-NEXT: ret <vscale x 4 x float> %155 %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)56 %2 = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fmul.u.nxv4f32(<vscale x 4 x i1> %1, <vscale x 4 x float> %a, <vscale x 4 x float> %b)57 ret <vscale x 4 x float> %258}59 60declare <vscale x 2 x double> @llvm.aarch64.sve.fmul.u.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)61define <vscale x 2 x double> @replace_fmul_u_intrinsic_double(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {62; CHECK-LABEL: @replace_fmul_u_intrinsic_double63; CHECK-NEXT: %1 = fmul fast <vscale x 2 x double> %a, %b64; CHECK-NEXT: ret <vscale x 2 x double> %165 %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)66 %2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.fmul.u.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)67 ret <vscale x 2 x double> %268}69 70declare <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)71define <vscale x 8 x half> @replace_fadd_intrinsic_half(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {72; CHECK-LABEL: @replace_fadd_intrinsic_half73; CHECK-NEXT: %1 = fadd fast <vscale x 8 x half> %a, %b74; CHECK-NEXT: ret <vscale x 8 x half> %175 %1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)76 %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1> %1, <vscale x 8 x half> %a, <vscale x 8 x half> %b)77 ret <vscale x 8 x half> %278}79 80declare <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)81define <vscale x 4 x float> @replace_fadd_intrinsic_float(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {82; CHECK-LABEL: @replace_fadd_intrinsic_float83; CHECK-NEXT: %1 = fadd fast <vscale x 4 x float> %a, %b84; CHECK-NEXT: ret <vscale x 4 x float> %185 %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)86 %2 = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4f32(<vscale x 4 x i1> %1, <vscale x 4 x float> %a, <vscale x 4 x float> %b)87 ret <vscale x 4 x float> %288}89 90declare <vscale x 2 x double> @llvm.aarch64.sve.fadd.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)91define <vscale x 2 x double> @replace_fadd_intrinsic_double(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {92; CHECK-LABEL: @replace_fadd_intrinsic_double93; CHECK-NEXT: %1 = fadd fast <vscale x 2 x double> %a, %b94; CHECK-NEXT: ret <vscale x 2 x double> %195 %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)96 %2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.fadd.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)97 ret <vscale x 2 x double> %298}99 100declare <vscale x 8 x half> @llvm.aarch64.sve.fadd.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)101define <vscale x 8 x half> @replace_fadd_u_intrinsic_half(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {102; CHECK-LABEL: @replace_fadd_u_intrinsic_half103; CHECK-NEXT: %1 = fadd fast <vscale x 8 x half> %a, %b104; CHECK-NEXT: ret <vscale x 8 x half> %1105 %1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)106 %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fadd.u.nxv8f16(<vscale x 8 x i1> %1, <vscale x 8 x half> %a, <vscale x 8 x half> %b)107 ret <vscale x 8 x half> %2108}109 110declare <vscale x 4 x float> @llvm.aarch64.sve.fadd.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)111define <vscale x 4 x float> @replace_fadd_u_intrinsic_float(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {112; CHECK-LABEL: @replace_fadd_u_intrinsic_float113; CHECK-NEXT: %1 = fadd fast <vscale x 4 x float> %a, %b114; CHECK-NEXT: ret <vscale x 4 x float> %1115 %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)116 %2 = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fadd.u.nxv4f32(<vscale x 4 x i1> %1, <vscale x 4 x float> %a, <vscale x 4 x float> %b)117 ret <vscale x 4 x float> %2118}119 120declare <vscale x 2 x double> @llvm.aarch64.sve.fadd.u.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)121define <vscale x 2 x double> @replace_fadd_u_intrinsic_double(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {122; CHECK-LABEL: @replace_fadd_u_intrinsic_double123; CHECK-NEXT: %1 = fadd fast <vscale x 2 x double> %a, %b124; CHECK-NEXT: ret <vscale x 2 x double> %1125 %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)126 %2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.fadd.u.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)127 ret <vscale x 2 x double> %2128}129 130declare <vscale x 8 x half> @llvm.aarch64.sve.fsub.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)131define <vscale x 8 x half> @replace_fsub_intrinsic_half(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {132; CHECK-LABEL: @replace_fsub_intrinsic_half133; CHECK-NEXT: %1 = fsub fast <vscale x 8 x half> %a, %b134; CHECK-NEXT: ret <vscale x 8 x half> %1135 %1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)136 %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fsub.nxv8f16(<vscale x 8 x i1> %1, <vscale x 8 x half> %a, <vscale x 8 x half> %b)137 ret <vscale x 8 x half> %2138}139 140declare <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)141define <vscale x 4 x float> @replace_fsub_intrinsic_float(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {142; CHECK-LABEL: @replace_fsub_intrinsic_float143; CHECK-NEXT: %1 = fsub fast <vscale x 4 x float> %a, %b144; CHECK-NEXT: ret <vscale x 4 x float> %1145 %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)146 %2 = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1> %1, <vscale x 4 x float> %a, <vscale x 4 x float> %b)147 ret <vscale x 4 x float> %2148}149 150declare <vscale x 2 x double> @llvm.aarch64.sve.fsub.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)151define <vscale x 2 x double> @replace_fsub_intrinsic_double(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {152; CHECK-LABEL: @replace_fsub_intrinsic_double153; CHECK-NEXT: %1 = fsub fast <vscale x 2 x double> %a, %b154; CHECK-NEXT: ret <vscale x 2 x double> %1155 %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)156 %2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.fsub.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)157 ret <vscale x 2 x double> %2158}159 160define <vscale x 2 x double> @no_replace_on_non_ptrue_all(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {161; CHECK-LABEL: @no_replace_on_non_ptrue_all162; CHECK-NEXT: %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 5)163; CHECK-NEXT: %2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.fsub.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)164; CHECK-NEXT: ret <vscale x 2 x double> %2165 %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 5)166 %2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.fsub.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)167 ret <vscale x 2 x double> %2168}169 170define <vscale x 2 x double> @replace_fsub_intrinsic_no_fast_flag(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {171; CHECK-LABEL: @replace_fsub_intrinsic_no_fast_flag172; CHECK-NEXT: %1 = fsub <vscale x 2 x double> %a, %b173; CHECK-NEXT: ret <vscale x 2 x double> %1174 %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)175 %2 = tail call <vscale x 2 x double> @llvm.aarch64.sve.fsub.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)176 ret <vscale x 2 x double> %2177}178 179declare <vscale x 8 x half> @llvm.aarch64.sve.fsub.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)180define <vscale x 8 x half> @replace_fsub_u_intrinsic_half(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {181; CHECK-LABEL: @replace_fsub_u_intrinsic_half182; CHECK-NEXT: %1 = fsub fast <vscale x 8 x half> %a, %b183; CHECK-NEXT: ret <vscale x 8 x half> %1184 %1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)185 %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fsub.u.nxv8f16(<vscale x 8 x i1> %1, <vscale x 8 x half> %a, <vscale x 8 x half> %b)186 ret <vscale x 8 x half> %2187}188 189declare <vscale x 4 x float> @llvm.aarch64.sve.fsub.u.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)190define <vscale x 4 x float> @replace_fsub_u_intrinsic_float(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {191; CHECK-LABEL: @replace_fsub_u_intrinsic_float192; CHECK-NEXT: %1 = fsub fast <vscale x 4 x float> %a, %b193; CHECK-NEXT: ret <vscale x 4 x float> %1194 %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)195 %2 = tail call fast <vscale x 4 x float> @llvm.aarch64.sve.fsub.u.nxv4f32(<vscale x 4 x i1> %1, <vscale x 4 x float> %a, <vscale x 4 x float> %b)196 ret <vscale x 4 x float> %2197}198 199declare <vscale x 2 x double> @llvm.aarch64.sve.fsub.u.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)200define <vscale x 2 x double> @replace_fsub_u_intrinsic_no_fast_flag(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {201; CHECK-LABEL: @replace_fsub_u_intrinsic_no_fast_flag202; CHECK-NEXT: %1 = fsub <vscale x 2 x double> %a, %b203; CHECK-NEXT: ret <vscale x 2 x double> %1204 %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)205 %2 = tail call <vscale x 2 x double> @llvm.aarch64.sve.fsub.u.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)206 ret <vscale x 2 x double> %2207}208 209define <vscale x 2 x double> @no_replace_on_non_ptrue_all_u(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {210; CHECK-LABEL: @no_replace_on_non_ptrue_all_u211; CHECK-NEXT: %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 5)212; CHECK-NEXT: %2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.fsub.u.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)213; CHECK-NEXT: ret <vscale x 2 x double> %2214 %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 5)215 %2 = tail call fast <vscale x 2 x double> @llvm.aarch64.sve.fsub.u.nxv2f64(<vscale x 2 x i1> %1, <vscale x 2 x double> %a, <vscale x 2 x double> %b)216 ret <vscale x 2 x double> %2217}218 219attributes #0 = { "target-features"="+sve" }220