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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -passes=instcombine < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6; fadd(a, fmul(b, c)) -> fmla(a, b, c)7define <vscale x 8 x half> @combine_fmuladd_1(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) #0 {8; CHECK-LABEL: @combine_fmuladd_1(9; CHECK-NEXT: [[TMP1:%.*]] = call fast <vscale x 8 x half> @llvm.aarch64.sve.fmla.nxv8f16(<vscale x 8 x i1> [[P:%.*]], <vscale x 8 x half> [[A:%.*]], <vscale x 8 x half> [[B:%.*]], <vscale x 8 x half> [[C:%.*]])10; CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]11;12 %1 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %b, <vscale x 8 x half> %c)13 %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %1)14 ret <vscale x 8 x half> %215}16 17; fadd(a, fmul_u(b, c)) -> fmla(a, b, c)18define <vscale x 8 x half> @combine_fmuladd_2(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) #0 {19; CHECK-LABEL: @combine_fmuladd_2(20; CHECK-NEXT: [[TMP1:%.*]] = call fast <vscale x 8 x half> @llvm.aarch64.sve.fmla.nxv8f16(<vscale x 8 x i1> [[P:%.*]], <vscale x 8 x half> [[A:%.*]], <vscale x 8 x half> [[B:%.*]], <vscale x 8 x half> [[C:%.*]])21; CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]22;23 %1 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.u.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %b, <vscale x 8 x half> %c)24 %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %1)25 ret <vscale x 8 x half> %226}27 28; fadd_u(a, fmul_u(b, c)) -> fmla_u(a, b, c)29define <vscale x 8 x half> @combine_fmuladd_3(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) #0 {30; CHECK-LABEL: @combine_fmuladd_3(31; CHECK-NEXT: [[TMP1:%.*]] = call fast <vscale x 8 x half> @llvm.aarch64.sve.fmla.u.nxv8f16(<vscale x 8 x i1> [[P:%.*]], <vscale x 8 x half> [[A:%.*]], <vscale x 8 x half> [[B:%.*]], <vscale x 8 x half> [[C:%.*]])32; CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]33;34 %1 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.u.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %b, <vscale x 8 x half> %c)35 %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fadd.u.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %1)36 ret <vscale x 8 x half> %237}38 39; TODO: Missing combine!40; fadd_u(a, fmul(b, c)) -> fmla_u(a, b, c)41define <vscale x 8 x half> @combine_fmuladd_4(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) #0 {42; CHECK-LABEL: @combine_fmuladd_4(43; CHECK-NEXT: [[TMP1:%.*]] = call fast <vscale x 8 x half> @llvm.aarch64.sve.fmla.nxv8f16(<vscale x 8 x i1> [[P:%.*]], <vscale x 8 x half> [[A:%.*]], <vscale x 8 x half> [[B:%.*]], <vscale x 8 x half> [[C:%.*]])44; CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]45;46 %1 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %b, <vscale x 8 x half> %c)47 %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fadd.u.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %1)48 ret <vscale x 8 x half> %249}50 51; fadd(fmul(b, c), a) -> fmad(b, c, a)52define <vscale x 8 x half> @combine_fmuladd_5(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) #0 {53; CHECK-LABEL: @combine_fmuladd_5(54; CHECK-NEXT: [[TMP1:%.*]] = call fast <vscale x 8 x half> @llvm.aarch64.sve.fmad.nxv8f16(<vscale x 8 x i1> [[P:%.*]], <vscale x 8 x half> [[B:%.*]], <vscale x 8 x half> [[C:%.*]], <vscale x 8 x half> [[A:%.*]])55; CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]56;57 %1 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %b, <vscale x 8 x half> %c)58 %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %1, <vscale x 8 x half> %a)59 ret <vscale x 8 x half> %260}61 62; TODO: Missing combine!63; fadd(fmul_u(b, c), a) -> fmla_u(a, b, c)64define <vscale x 8 x half> @combine_fmuladd_6(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) #0 {65; CHECK-LABEL: @combine_fmuladd_6(66; CHECK-NEXT: [[TMP1:%.*]] = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.u.nxv8f16(<vscale x 8 x i1> [[P:%.*]], <vscale x 8 x half> [[B:%.*]], <vscale x 8 x half> [[C:%.*]])67; CHECK-NEXT: [[TMP2:%.*]] = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1> [[P]], <vscale x 8 x half> [[TMP1]], <vscale x 8 x half> [[A:%.*]])68; CHECK-NEXT: ret <vscale x 8 x half> [[TMP2]]69;70 %1 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.u.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %b, <vscale x 8 x half> %c)71 %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %1, <vscale x 8 x half> %a)72 ret <vscale x 8 x half> %273}74 75; TODO: Missing combine!76; fadd_u(fmul_u(b, c), a) -> fmla_u(a, b, c)77define <vscale x 8 x half> @combine_fmuladd_7(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) #0 {78; CHECK-LABEL: @combine_fmuladd_7(79; CHECK-NEXT: [[TMP1:%.*]] = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.u.nxv8f16(<vscale x 8 x i1> [[P:%.*]], <vscale x 8 x half> [[B:%.*]], <vscale x 8 x half> [[C:%.*]])80; CHECK-NEXT: [[TMP2:%.*]] = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fadd.u.nxv8f16(<vscale x 8 x i1> [[P]], <vscale x 8 x half> [[TMP1]], <vscale x 8 x half> [[A:%.*]])81; CHECK-NEXT: ret <vscale x 8 x half> [[TMP2]]82;83 %1 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.u.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %b, <vscale x 8 x half> %c)84 %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fadd.u.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %1, <vscale x 8 x half> %a)85 ret <vscale x 8 x half> %286}87 88; TODO: Missing combine!89; fadd_u(fmul(b, c), a) -> fmla_u(a, b, c)90define <vscale x 8 x half> @combine_fmuladd_8(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) #0 {91; CHECK-LABEL: @combine_fmuladd_8(92; CHECK-NEXT: [[TMP1:%.*]] = call fast <vscale x 8 x half> @llvm.aarch64.sve.fmad.nxv8f16(<vscale x 8 x i1> [[P:%.*]], <vscale x 8 x half> [[B:%.*]], <vscale x 8 x half> [[C:%.*]], <vscale x 8 x half> [[A:%.*]])93; CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]94;95 %1 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %b, <vscale x 8 x half> %c)96 %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fadd.u.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %1, <vscale x 8 x half> %a)97 ret <vscale x 8 x half> %298}99 100; fsub(a, fmul(b, c)) -> fmls(a, b, c)101define <vscale x 8 x half> @combine_fmulsub_1(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) #0 {102; CHECK-LABEL: @combine_fmulsub_1(103; CHECK-NEXT: [[TMP1:%.*]] = call fast <vscale x 8 x half> @llvm.aarch64.sve.fmls.nxv8f16(<vscale x 8 x i1> [[P:%.*]], <vscale x 8 x half> [[A:%.*]], <vscale x 8 x half> [[B:%.*]], <vscale x 8 x half> [[C:%.*]])104; CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]105;106 %1 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %b, <vscale x 8 x half> %c)107 %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fsub.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %1)108 ret <vscale x 8 x half> %2109}110 111define <vscale x 8 x half> @combine_fmulsub_2(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) #0 {112; CHECK-LABEL: @combine_fmulsub_2(113; CHECK-NEXT: [[TMP1:%.*]] = call fast <vscale x 8 x half> @llvm.aarch64.sve.fmls.nxv8f16(<vscale x 8 x i1> [[P:%.*]], <vscale x 8 x half> [[A:%.*]], <vscale x 8 x half> [[B:%.*]], <vscale x 8 x half> [[C:%.*]])114; CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]115;116 %1 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.u.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %b, <vscale x 8 x half> %c)117 %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fsub.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %1)118 ret <vscale x 8 x half> %2119}120 121; fsub_u(a, fmul_u(b, c)) -> fmls_u(a, b, c)122define <vscale x 8 x half> @combine_fmulsub_3(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) #0 {123; CHECK-LABEL: @combine_fmulsub_3(124; CHECK-NEXT: [[TMP1:%.*]] = call fast <vscale x 8 x half> @llvm.aarch64.sve.fmls.u.nxv8f16(<vscale x 8 x i1> [[P:%.*]], <vscale x 8 x half> [[A:%.*]], <vscale x 8 x half> [[B:%.*]], <vscale x 8 x half> [[C:%.*]])125; CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]126;127 %1 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.u.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %b, <vscale x 8 x half> %c)128 %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fsub.u.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %1)129 ret <vscale x 8 x half> %2130}131 132; TODO: Missing combine!133; fsub_u(a, fmul(b, c)) -> fmls_u(a, b, c)134define <vscale x 8 x half> @combine_fmulsub_4(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) #0 {135; CHECK-LABEL: @combine_fmulsub_4(136; CHECK-NEXT: [[TMP1:%.*]] = call fast <vscale x 8 x half> @llvm.aarch64.sve.fmls.nxv8f16(<vscale x 8 x i1> [[P:%.*]], <vscale x 8 x half> [[A:%.*]], <vscale x 8 x half> [[B:%.*]], <vscale x 8 x half> [[C:%.*]])137; CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]138;139 %1 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %b, <vscale x 8 x half> %c)140 %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fsub.u.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %1)141 ret <vscale x 8 x half> %2142}143 144; fsub(mul(b, c), a) -> fnmsb(b, c, a)145define <vscale x 8 x half> @combine_fmulsub_5(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) #0 {146; CHECK-LABEL: @combine_fmulsub_5(147; CHECK-NEXT: [[TMP1:%.*]] = call fast <vscale x 8 x half> @llvm.aarch64.sve.fnmsb.nxv8f16(<vscale x 8 x i1> [[P:%.*]], <vscale x 8 x half> [[B:%.*]], <vscale x 8 x half> [[C:%.*]], <vscale x 8 x half> [[A:%.*]])148; CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]149;150 %1 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %b, <vscale x 8 x half> %c)151 %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fsub.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %1, <vscale x 8 x half> %a)152 ret <vscale x 8 x half> %2153}154 155; TODO: Missing combine!156; fsub(fmul_u(b, c), a) -> fnmls_u(a, b, c)157define <vscale x 8 x half> @combine_fmulsub_6(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) #0 {158; CHECK-LABEL: @combine_fmulsub_6(159; CHECK-NEXT: [[TMP1:%.*]] = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.u.nxv8f16(<vscale x 8 x i1> [[P:%.*]], <vscale x 8 x half> [[B:%.*]], <vscale x 8 x half> [[C:%.*]])160; CHECK-NEXT: [[TMP2:%.*]] = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fsub.nxv8f16(<vscale x 8 x i1> [[P]], <vscale x 8 x half> [[TMP1]], <vscale x 8 x half> [[A:%.*]])161; CHECK-NEXT: ret <vscale x 8 x half> [[TMP2]]162;163 %1 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.u.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %b, <vscale x 8 x half> %c)164 %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fsub.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %1, <vscale x 8 x half> %a)165 ret <vscale x 8 x half> %2166}167 168; TODO: Missing combine!169; fsub_u(fmul_u(b, c), a) -> fnmls_u(a, b, c)170define <vscale x 8 x half> @combine_fmulsub_7(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) #0 {171; CHECK-LABEL: @combine_fmulsub_7(172; CHECK-NEXT: [[TMP1:%.*]] = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.u.nxv8f16(<vscale x 8 x i1> [[P:%.*]], <vscale x 8 x half> [[B:%.*]], <vscale x 8 x half> [[C:%.*]])173; CHECK-NEXT: [[TMP2:%.*]] = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fsub.u.nxv8f16(<vscale x 8 x i1> [[P]], <vscale x 8 x half> [[TMP1]], <vscale x 8 x half> [[A:%.*]])174; CHECK-NEXT: ret <vscale x 8 x half> [[TMP2]]175;176 %1 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.u.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %b, <vscale x 8 x half> %c)177 %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fsub.u.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %1, <vscale x 8 x half> %a)178 ret <vscale x 8 x half> %2179}180 181; TODO: Missing combine!182; fsub_u(fmul(b, c), a) -> fnmls_u(a, b, c)183define <vscale x 8 x half> @combine_fmulsub_8(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) #0 {184; CHECK-LABEL: @combine_fmulsub_8(185; CHECK-NEXT: [[TMP1:%.*]] = call fast <vscale x 8 x half> @llvm.aarch64.sve.fnmsb.nxv8f16(<vscale x 8 x i1> [[P:%.*]], <vscale x 8 x half> [[B:%.*]], <vscale x 8 x half> [[C:%.*]], <vscale x 8 x half> [[A:%.*]])186; CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]187;188 %1 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %b, <vscale x 8 x half> %c)189 %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fsub.u.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %1, <vscale x 8 x half> %a)190 ret <vscale x 8 x half> %2191}192 193; add(a, mul(b, c)) -> mla(a, b, c)194define <vscale x 16 x i8> @combine_muladd_1(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {195; CHECK-LABEL: @combine_muladd_1(196; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.mla.nxv16i8(<vscale x 16 x i1> [[P:%.*]], <vscale x 16 x i8> [[A:%.*]], <vscale x 16 x i8> [[B:%.*]], <vscale x 16 x i8> [[C:%.*]])197; CHECK-NEXT: ret <vscale x 16 x i8> [[TMP1]]198;199 %1 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)200 %2 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %1)201 ret <vscale x 16 x i8> %2202}203 204; TODO: Missing combine!205; add(a, mul_u(b, c)) -> mla(a, b, c)206define <vscale x 16 x i8> @combine_muladd_2(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {207; CHECK-LABEL: @combine_muladd_2(208; CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.u.nxv16i8(<vscale x 16 x i1> [[P:%.*]], <vscale x 16 x i8> [[B:%.*]], <vscale x 16 x i8> [[C:%.*]])209; CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1> [[P]], <vscale x 16 x i8> [[A:%.*]], <vscale x 16 x i8> [[TMP1]])210; CHECK-NEXT: ret <vscale x 16 x i8> [[TMP2]]211;212 %1 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.u.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)213 %2 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %1)214 ret <vscale x 16 x i8> %2215}216 217; add_u(a, mul_u(b, c)) -> mla_u(a, b, c)218define <vscale x 16 x i8> @combine_muladd_3(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {219; CHECK-LABEL: @combine_muladd_3(220; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.mla.u.nxv16i8(<vscale x 16 x i1> [[P:%.*]], <vscale x 16 x i8> [[A:%.*]], <vscale x 16 x i8> [[B:%.*]], <vscale x 16 x i8> [[C:%.*]])221; CHECK-NEXT: ret <vscale x 16 x i8> [[TMP1]]222;223 %1 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.u.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)224 %2 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.add.u.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %1)225 ret <vscale x 16 x i8> %2226}227 228; TODO: Missing combine!229; add_u(a, mul(b, c)) -> mla_u(a, b, c)230define <vscale x 16 x i8> @combine_muladd_4(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {231; CHECK-LABEL: @combine_muladd_4(232; CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> [[P:%.*]], <vscale x 16 x i8> [[B:%.*]], <vscale x 16 x i8> [[C:%.*]])233; CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.add.u.nxv16i8(<vscale x 16 x i1> [[P]], <vscale x 16 x i8> [[A:%.*]], <vscale x 16 x i8> [[TMP1]])234; CHECK-NEXT: ret <vscale x 16 x i8> [[TMP2]]235;236 %1 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)237 %2 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.add.u.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %1)238 ret <vscale x 16 x i8> %2239}240 241; add(mul(b, c), a) -> mad(b, c, c)242define <vscale x 16 x i8> @combine_muladd_5(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {243; CHECK-LABEL: @combine_muladd_5(244; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.mad.nxv16i8(<vscale x 16 x i1> [[P:%.*]], <vscale x 16 x i8> [[B:%.*]], <vscale x 16 x i8> [[C:%.*]], <vscale x 16 x i8> [[A:%.*]])245; CHECK-NEXT: ret <vscale x 16 x i8> [[TMP1]]246;247 %1 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)248 %2 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %1, <vscale x 16 x i8> %a)249 ret <vscale x 16 x i8> %2250}251 252; TODO: Missing combine!253; add(mul_u(b, c), a) -> mla_u(a, b, c)254define <vscale x 16 x i8> @combine_muladd_6(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {255; CHECK-LABEL: @combine_muladd_6(256; CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.u.nxv16i8(<vscale x 16 x i1> [[P:%.*]], <vscale x 16 x i8> [[B:%.*]], <vscale x 16 x i8> [[C:%.*]])257; CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1> [[P]], <vscale x 16 x i8> [[TMP1]], <vscale x 16 x i8> [[A:%.*]])258; CHECK-NEXT: ret <vscale x 16 x i8> [[TMP2]]259;260 %1 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.u.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)261 %2 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %1, <vscale x 16 x i8> %a)262 ret <vscale x 16 x i8> %2263}264 265; TODO: Missing combine!266; add_u(mul_u(b, c), a) -> mla_u(a, b, c)267define <vscale x 16 x i8> @combine_muladd_7(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {268; CHECK-LABEL: @combine_muladd_7(269; CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.u.nxv16i8(<vscale x 16 x i1> [[P:%.*]], <vscale x 16 x i8> [[B:%.*]], <vscale x 16 x i8> [[C:%.*]])270; CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.add.u.nxv16i8(<vscale x 16 x i1> [[P]], <vscale x 16 x i8> [[TMP1]], <vscale x 16 x i8> [[A:%.*]])271; CHECK-NEXT: ret <vscale x 16 x i8> [[TMP2]]272;273 %1 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.u.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)274 %2 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.add.u.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %1, <vscale x 16 x i8> %a)275 ret <vscale x 16 x i8> %2276}277 278; TODO: Missing combine!279; add_u(mul(b, c), a) -> mla_u(a, b, c)280define <vscale x 16 x i8> @combine_muladd_8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {281; CHECK-LABEL: @combine_muladd_8(282; CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> [[P:%.*]], <vscale x 16 x i8> [[B:%.*]], <vscale x 16 x i8> [[C:%.*]])283; CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.add.u.nxv16i8(<vscale x 16 x i1> [[P]], <vscale x 16 x i8> [[TMP1]], <vscale x 16 x i8> [[A:%.*]])284; CHECK-NEXT: ret <vscale x 16 x i8> [[TMP2]]285;286 %1 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)287 %2 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.add.u.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %1, <vscale x 16 x i8> %a)288 ret <vscale x 16 x i8> %2289}290 291; sub(a, mul(b, c)) -> mls(a, b, c)292define <vscale x 16 x i8> @combine_mulsub_1(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {293; CHECK-LABEL: @combine_mulsub_1(294; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.mls.nxv16i8(<vscale x 16 x i1> [[P:%.*]], <vscale x 16 x i8> [[A:%.*]], <vscale x 16 x i8> [[B:%.*]], <vscale x 16 x i8> [[C:%.*]])295; CHECK-NEXT: ret <vscale x 16 x i8> [[TMP1]]296;297 %1 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)298 %2 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %1)299 ret <vscale x 16 x i8> %2300}301 302; TODO: Missing combine!303; sub(a, mul_u(b, c)) -> mls(a, b, c)304define <vscale x 16 x i8> @combine_mulsub_2(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {305; CHECK-LABEL: @combine_mulsub_2(306; CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.u.nxv16i8(<vscale x 16 x i1> [[P:%.*]], <vscale x 16 x i8> [[B:%.*]], <vscale x 16 x i8> [[C:%.*]])307; CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1> [[P]], <vscale x 16 x i8> [[A:%.*]], <vscale x 16 x i8> [[TMP1]])308; CHECK-NEXT: ret <vscale x 16 x i8> [[TMP2]]309;310 %1 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.u.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)311 %2 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %1)312 ret <vscale x 16 x i8> %2313}314 315; sub_u(a, mul_u(b, c)) -> mls_u(a, b, c)316define <vscale x 16 x i8> @combine_mulsub_3(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {317; CHECK-LABEL: @combine_mulsub_3(318; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.mls.u.nxv16i8(<vscale x 16 x i1> [[P:%.*]], <vscale x 16 x i8> [[A:%.*]], <vscale x 16 x i8> [[B:%.*]], <vscale x 16 x i8> [[C:%.*]])319; CHECK-NEXT: ret <vscale x 16 x i8> [[TMP1]]320;321 %1 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.u.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)322 %2 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sub.u.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %1)323 ret <vscale x 16 x i8> %2324}325 326; TODO: Missing combine!327; sub_u(a, mul(b, c)) -> mls_u(a, b, c)328define <vscale x 16 x i8> @combine_mulsub_4(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {329; CHECK-LABEL: @combine_mulsub_4(330; CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> [[P:%.*]], <vscale x 16 x i8> [[B:%.*]], <vscale x 16 x i8> [[C:%.*]])331; CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sub.u.nxv16i8(<vscale x 16 x i1> [[P]], <vscale x 16 x i8> [[A:%.*]], <vscale x 16 x i8> [[TMP1]])332; CHECK-NEXT: ret <vscale x 16 x i8> [[TMP2]]333;334 %1 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)335 %2 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sub.u.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %1)336 ret <vscale x 16 x i8> %2337}338 339; sub(mul(b, c), a) -> sub(mul(b, c), a)340define <vscale x 16 x i8> @combine_mulsub_5(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {341; CHECK-LABEL: @combine_mulsub_5(342; CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> [[P:%.*]], <vscale x 16 x i8> [[B:%.*]], <vscale x 16 x i8> [[C:%.*]])343; CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1> [[P]], <vscale x 16 x i8> [[TMP1]], <vscale x 16 x i8> [[A:%.*]])344; CHECK-NEXT: ret <vscale x 16 x i8> [[TMP2]]345;346 %1 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)347 %2 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %1, <vscale x 16 x i8> %a)348 ret <vscale x 16 x i8> %2349}350 351; TODO: Missing combine!352; sub(mul_u(b, c), a) -> sub_u(mul_u(b, c), a)353define <vscale x 16 x i8> @combine_mulsub_6(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {354; CHECK-LABEL: @combine_mulsub_6(355; CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.u.nxv16i8(<vscale x 16 x i1> [[P:%.*]], <vscale x 16 x i8> [[B:%.*]], <vscale x 16 x i8> [[C:%.*]])356; CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1> [[P]], <vscale x 16 x i8> [[TMP1]], <vscale x 16 x i8> [[A:%.*]])357; CHECK-NEXT: ret <vscale x 16 x i8> [[TMP2]]358;359 %1 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.u.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)360 %2 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %1, <vscale x 16 x i8> %a)361 ret <vscale x 16 x i8> %2362}363 364; sub_u(mul_u(b, c), a) -> sub_u(mul_u(b, c), a)365define <vscale x 16 x i8> @combine_mulsub_7(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {366; CHECK-LABEL: @combine_mulsub_7(367; CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.u.nxv16i8(<vscale x 16 x i1> [[P:%.*]], <vscale x 16 x i8> [[B:%.*]], <vscale x 16 x i8> [[C:%.*]])368; CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sub.u.nxv16i8(<vscale x 16 x i1> [[P]], <vscale x 16 x i8> [[TMP1]], <vscale x 16 x i8> [[A:%.*]])369; CHECK-NEXT: ret <vscale x 16 x i8> [[TMP2]]370;371 %1 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.u.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)372 %2 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sub.u.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %1, <vscale x 16 x i8> %a)373 ret <vscale x 16 x i8> %2374}375 376; TODO: Missing combine!377; sub_u(mul(b, c), a) -> sub_u(mul_u(b, c), a)378define <vscale x 16 x i8> @combine_mulsub_8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {379; CHECK-LABEL: @combine_mulsub_8(380; CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> [[P:%.*]], <vscale x 16 x i8> [[B:%.*]], <vscale x 16 x i8> [[C:%.*]])381; CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sub.u.nxv16i8(<vscale x 16 x i1> [[P]], <vscale x 16 x i8> [[TMP1]], <vscale x 16 x i8> [[A:%.*]])382; CHECK-NEXT: ret <vscale x 16 x i8> [[TMP2]]383;384 %1 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)385 %2 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.sub.u.nxv16i8(<vscale x 16 x i1> %p, <vscale x 16 x i8> %1, <vscale x 16 x i8> %a)386 ret <vscale x 16 x i8> %2387}388 389define <vscale x 8 x half> @neg_combine_fmuladd_neq_pred(<vscale x 8 x i1> %p1, <vscale x 8 x i1> %p2, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) #0 {390; CHECK-LABEL: @neg_combine_fmuladd_neq_pred(391; CHECK-NEXT: [[TMP1:%.*]] = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1> [[P1:%.*]], <vscale x 8 x half> [[B:%.*]], <vscale x 8 x half> [[C:%.*]])392; CHECK-NEXT: [[TMP2:%.*]] = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1> [[P2:%.*]], <vscale x 8 x half> [[A:%.*]], <vscale x 8 x half> [[TMP1]])393; CHECK-NEXT: ret <vscale x 8 x half> [[TMP2]]394;395; ret <vscale x 8 x half> %9396 %1 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1> %p1, <vscale x 8 x half> %b, <vscale x 8 x half> %c)397 %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1> %p2, <vscale x 8 x half> %a, <vscale x 8 x half> %1)398 ret <vscale x 8 x half> %2399}400 401define <vscale x 8 x half> @neg_combine_fmuladd_two_fmul_uses(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) #0 {402; CHECK-LABEL: @neg_combine_fmuladd_two_fmul_uses(403; CHECK-NEXT: [[TMP1:%.*]] = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1> [[P:%.*]], <vscale x 8 x half> [[B:%.*]], <vscale x 8 x half> [[C:%.*]])404; CHECK-NEXT: [[TMP2:%.*]] = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1> [[P]], <vscale x 8 x half> [[A:%.*]], <vscale x 8 x half> [[TMP1]])405; CHECK-NEXT: [[TMP3:%.*]] = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1> [[P]], <vscale x 8 x half> [[TMP2]], <vscale x 8 x half> [[TMP1]])406; CHECK-NEXT: ret <vscale x 8 x half> [[TMP3]]407;408; ret <vscale x 8 x half> %8409 %1 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %b, <vscale x 8 x half> %c)410 %2 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %1)411 %3 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %2, <vscale x 8 x half> %1)412 ret <vscale x 8 x half> %3413}414 415define <vscale x 8 x half> @neg_combine_fmuladd_neq_flags(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c) #0 {416; CHECK-LABEL: @neg_combine_fmuladd_neq_flags(417; CHECK-NEXT: [[TMP1:%.*]] = tail call reassoc nnan contract <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1> [[P:%.*]], <vscale x 8 x half> [[B:%.*]], <vscale x 8 x half> [[C:%.*]])418; CHECK-NEXT: [[TMP2:%.*]] = tail call reassoc contract <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1> [[P]], <vscale x 8 x half> [[A:%.*]], <vscale x 8 x half> [[TMP1]])419; CHECK-NEXT: ret <vscale x 8 x half> [[TMP2]]420;421; ret <vscale x 8 x half> %7422 %1 = tail call reassoc nnan contract <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %b, <vscale x 8 x half> %c)423 %2 = tail call reassoc contract <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %1)424 ret <vscale x 8 x half> %2425}426 427declare <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)428declare <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)429declare <vscale x 8 x half> @llvm.aarch64.sve.fsub.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)430 431declare <vscale x 8 x half> @llvm.aarch64.sve.fmul.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)432declare <vscale x 8 x half> @llvm.aarch64.sve.fadd.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)433declare <vscale x 8 x half> @llvm.aarch64.sve.fsub.u.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)434 435declare <vscale x 16 x i8> @llvm.aarch64.sve.mul.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)436declare <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)437declare <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)438 439declare <vscale x 16 x i8> @llvm.aarch64.sve.mul.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)440declare <vscale x 16 x i8> @llvm.aarch64.sve.add.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)441declare <vscale x 16 x i8> @llvm.aarch64.sve.sub.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)442 443attributes #0 = { "target-features"="+sve" }444