45 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=instcombine -S < %s | FileCheck %s3 4target triple = "aarch64"5 6define i16 @clastb_n_i16(<vscale x 8 x i1> %pg, i16 %a, <vscale x 8 x i16> %b) {7; CHECK-LABEL: @clastb_n_i16(8; CHECK-NEXT: [[TMP1:%.*]] = bitcast i16 [[A:%.*]] to half9; CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 8 x i16> [[B:%.*]] to <vscale x 8 x half>10; CHECK-NEXT: [[TMP3:%.*]] = call half @llvm.aarch64.sve.clastb.n.nxv8f16(<vscale x 8 x i1> [[PG:%.*]], half [[TMP1]], <vscale x 8 x half> [[TMP2]])11; CHECK-NEXT: [[TMP4:%.*]] = bitcast half [[TMP3]] to i1612; CHECK-NEXT: ret i16 [[TMP4]]13;14 %out = call i16 @llvm.aarch64.sve.clastb.n.nxv8i16(<vscale x 8 x i1> %pg, i16 %a, <vscale x 8 x i16> %b)15 ret i16 %out16}17 18define i32 @clastb_n_i32(<vscale x 4 x i1> %pg, i32 %a, <vscale x 4 x i32> %b) {19; CHECK-LABEL: @clastb_n_i32(20; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[A:%.*]] to float21; CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 4 x i32> [[B:%.*]] to <vscale x 4 x float>22; CHECK-NEXT: [[TMP3:%.*]] = call float @llvm.aarch64.sve.clastb.n.nxv4f32(<vscale x 4 x i1> [[PG:%.*]], float [[TMP1]], <vscale x 4 x float> [[TMP2]])23; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[TMP3]] to i3224; CHECK-NEXT: ret i32 [[TMP4]]25;26 %out = call i32 @llvm.aarch64.sve.clastb.n.nxv4i32(<vscale x 4 x i1> %pg, i32 %a, <vscale x 4 x i32> %b)27 ret i32 %out28}29 30define i64 @clastb_n_i64(<vscale x 2 x i1> %pg, i64 %a, <vscale x 2 x i64> %b) {31; CHECK-LABEL: @clastb_n_i64(32; CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[A:%.*]] to double33; CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i64> [[B:%.*]] to <vscale x 2 x double>34; CHECK-NEXT: [[TMP3:%.*]] = call double @llvm.aarch64.sve.clastb.n.nxv2f64(<vscale x 2 x i1> [[PG:%.*]], double [[TMP1]], <vscale x 2 x double> [[TMP2]])35; CHECK-NEXT: [[TMP4:%.*]] = bitcast double [[TMP3]] to i6436; CHECK-NEXT: ret i64 [[TMP4]]37;38 %out = call i64 @llvm.aarch64.sve.clastb.n.nxv2i64(<vscale x 2 x i1> %pg, i64 %a, <vscale x 2 x i64> %b)39 ret i64 %out40}41 42declare i16 @llvm.aarch64.sve.clastb.n.nxv8i16(<vscale x 8 x i1>, i16, <vscale x 8 x i16>)43declare i32 @llvm.aarch64.sve.clastb.n.nxv4i32(<vscale x 4 x i1>, i32, <vscale x 4 x i32>)44declare i64 @llvm.aarch64.sve.clastb.n.nxv2i64(<vscale x 2 x i1>, i64, <vscale x 2 x i64>)45