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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S -passes=instcombine < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6; The follow tests verify the mechanics of simplification. The operation is not7; important beyond being commutative with a known identity value.8 9define <vscale x 4 x i32> @commute_constant_to_rhs(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) #0 {10; CHECK-LABEL: define <vscale x 4 x i32> @commute_constant_to_rhs(11; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]]) #[[ATTR0:[0-9]+]] {12; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> splat (i32 303))13; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]14;15 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 303), <vscale x 4 x i32> %a)16 ret <vscale x 4 x i32> %r17}18 19; Operation is not commutative.20define <vscale x 4 x i32> @cannot_commute_constant_to_rhs_1(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) #0 {21; CHECK-LABEL: define <vscale x 4 x i32> @cannot_commute_constant_to_rhs_1(22; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]]) #[[ATTR0]] {23; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 303), <vscale x 4 x i32> [[A]])24; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]25;26 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 303), <vscale x 4 x i32> %a)27 ret <vscale x 4 x i32> %r28}29 30; Inactive lanes are important, which make the operation non-commutative.31define <vscale x 4 x i32> @cannot_commute_constant_to_rhs_2(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) #0 {32; CHECK-LABEL: define <vscale x 4 x i32> @cannot_commute_constant_to_rhs_2(33; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]]) #[[ATTR0]] {34; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 303), <vscale x 4 x i32> [[A]])35; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]36;37 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 303), <vscale x 4 x i32> %a)38 ret <vscale x 4 x i32> %r39}40 41define <vscale x 4 x i32> @idempotent_mul(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) #0 {42; CHECK-LABEL: define <vscale x 4 x i32> @idempotent_mul(43; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]]) #[[ATTR0]] {44; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]45;46 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat (i32 1))47 ret <vscale x 4 x i32> %r48}49 50define <vscale x 4 x i32> @idempotent_mul_ops_reverse(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) #0 {51; CHECK-LABEL: define <vscale x 4 x i32> @idempotent_mul_ops_reverse(52; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]]) #[[ATTR0]] {53; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> splat (i32 1)54; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]55;56 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 1), <vscale x 4 x i32> %a)57 ret <vscale x 4 x i32> %r58}59 60define <vscale x 4 x i32> @idempotent_mul_u(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) #0 {61; CHECK-LABEL: define <vscale x 4 x i32> @idempotent_mul_u(62; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]]) #[[ATTR0]] {63; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]64;65 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat (i32 1))66 ret <vscale x 4 x i32> %r67}68 69define <vscale x 4 x i32> @idempotent_mul_u_ops_reverse(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) #0 {70; CHECK-LABEL: define <vscale x 4 x i32> @idempotent_mul_u_ops_reverse(71; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]]) #[[ATTR0]] {72; CHECK-NEXT: ret <vscale x 4 x i32> [[A]]73;74 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 1), <vscale x 4 x i32> %a)75 ret <vscale x 4 x i32> %r76}77 78; Show that we only need to know the active lanes are constant.79; TODO: We can do better here because we can use %a directly as part of the80; select because we know only its inactive lanes will be used.81define <vscale x 4 x i32> @constant_mul_after_striping_inactive_lanes(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {82; CHECK-LABEL: define <vscale x 4 x i32> @constant_mul_after_striping_inactive_lanes(83; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR0]] {84; CHECK-NEXT: [[A_DUP:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.nxv4i32(<vscale x 4 x i32> [[A]], <vscale x 4 x i1> [[PG]], i32 3)85; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 6), <vscale x 4 x i32> [[A_DUP]]86; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]87;88 %a.dup = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, i32 3)89 %b.dup = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.nxv4i32(<vscale x 4 x i32> %b, <vscale x 4 x i1> %pg, i32 2)90 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a.dup, <vscale x 4 x i32> %b.dup)91 ret <vscale x 4 x i32> %r92}93 94; Show that we only need to know the active lanes are constant.95define <vscale x 4 x i32> @constant_mul_u_after_striping_inactive_lanes(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {96; CHECK-LABEL: define <vscale x 4 x i32> @constant_mul_u_after_striping_inactive_lanes(97; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]], <vscale x 4 x i32> [[B:%.*]]) #[[ATTR0]] {98; CHECK-NEXT: ret <vscale x 4 x i32> splat (i32 6)99;100 %a.dup = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, i32 3)101 %b.dup = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.nxv4i32(<vscale x 4 x i32> %b, <vscale x 4 x i1> %pg, i32 2)102 %3 = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a.dup, <vscale x 4 x i32> %b.dup)103 ret <vscale x 4 x i32> %3104}105 106; SVE intrinsics don't have the same poison propagation rules as the IR.107define <vscale x 4 x i32> @dont_propagate_poison(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) #0 {108; CHECK-LABEL: define <vscale x 4 x i32> @dont_propagate_poison(109; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]]) #[[ATTR0]] {110; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> poison, <vscale x 4 x i32> splat (i32 1))111; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]112;113 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> poison, <vscale x 4 x i32> splat (i32 1))114 ret <vscale x 4 x i32> %r115}116 117; The follow tests demonstrate the operations for which hooks are in place to118; enable simplification. Given the simplications themselves are common code, it119; is assumed they are already well tested elsewhere.120 121define <vscale x 4 x i32> @constant_add(<vscale x 4 x i1> %pg) #0 {122; CHECK-LABEL: define <vscale x 4 x i32> @constant_add(123; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {124; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 10), <vscale x 4 x i32> splat (i32 7)125; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]126;127 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))128 ret <vscale x 4 x i32> %r129}130 131define <vscale x 4 x i32> @constant_add_u(<vscale x 4 x i1> %pg) #0 {132; CHECK-LABEL: define <vscale x 4 x i32> @constant_add_u(133; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {134; CHECK-NEXT: ret <vscale x 4 x i32> splat (i32 10)135;136 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.add.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))137 ret <vscale x 4 x i32> %r138}139 140define <vscale x 4 x i32> @constant_and(<vscale x 4 x i1> %pg) #0 {141; CHECK-LABEL: define <vscale x 4 x i32> @constant_and(142; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {143; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 6), <vscale x 4 x i32> splat (i32 7)144; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]145;146 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 14))147 ret <vscale x 4 x i32> %r148}149 150define <vscale x 4 x i32> @constant_and_u(<vscale x 4 x i1> %pg) #0 {151; CHECK-LABEL: define <vscale x 4 x i32> @constant_and_u(152; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {153; CHECK-NEXT: ret <vscale x 4 x i32> splat (i32 6)154;155 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.and.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 14))156 ret <vscale x 4 x i32> %r157}158 159define <vscale x 4 x i32> @constant_eor(<vscale x 4 x i1> %pg) #0 {160; CHECK-LABEL: define <vscale x 4 x i32> @constant_eor(161; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {162; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 4), <vscale x 4 x i32> splat (i32 7)163; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]164;165 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))166 ret <vscale x 4 x i32> %r167}168 169define <vscale x 4 x i32> @constant_eor_u(<vscale x 4 x i1> %pg) #0 {170; CHECK-LABEL: define <vscale x 4 x i32> @constant_eor_u(171; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {172; CHECK-NEXT: ret <vscale x 4 x i32> splat (i32 4)173;174 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))175 ret <vscale x 4 x i32> %r176}177 178define <vscale x 4 x float> @constant_fadd(<vscale x 4 x i1> %pg) #0 {179; CHECK-LABEL: define <vscale x 4 x float> @constant_fadd(180; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {181; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x float> splat (float 1.300000e+01), <vscale x 4 x float> splat (float 7.000000e+00)182; CHECK-NEXT: ret <vscale x 4 x float> [[R]]183;184 %r = call <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 7.0), <vscale x 4 x float> splat (float 6.0))185 ret <vscale x 4 x float> %r186}187 188define <vscale x 4 x float> @constant_fadd_u(<vscale x 4 x i1> %pg) #0 {189; CHECK-LABEL: define <vscale x 4 x float> @constant_fadd_u(190; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {191; CHECK-NEXT: ret <vscale x 4 x float> splat (float 1.300000e+01)192;193 %r = call <vscale x 4 x float> @llvm.aarch64.sve.fadd.u.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 7.0), <vscale x 4 x float> splat (float 6.0))194 ret <vscale x 4 x float> %r195}196 197define <vscale x 4 x float> @constant_fdiv(<vscale x 4 x i1> %pg) #0 {198; CHECK-LABEL: define <vscale x 4 x float> @constant_fdiv(199; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {200; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x float> splat (float 2.000000e+00), <vscale x 4 x float> splat (float 1.200000e+01)201; CHECK-NEXT: ret <vscale x 4 x float> [[R]]202;203 %r = call <vscale x 4 x float> @llvm.aarch64.sve.fdiv.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 12.0), <vscale x 4 x float> splat (float 6.0))204 ret <vscale x 4 x float> %r205}206 207define <vscale x 4 x float> @constant_fdiv_u(<vscale x 4 x i1> %pg) #0 {208; CHECK-LABEL: define <vscale x 4 x float> @constant_fdiv_u(209; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {210; CHECK-NEXT: ret <vscale x 4 x float> splat (float 0x3FF2AAAAA0000000)211;212 %r = call <vscale x 4 x float> @llvm.aarch64.sve.fdiv.u.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 7.0), <vscale x 4 x float> splat (float 6.0))213 ret <vscale x 4 x float> %r214}215 216define <vscale x 4 x float> @constant_fdivr(<vscale x 4 x i1> %pg) #0 {217; CHECK-LABEL: define <vscale x 4 x float> @constant_fdivr(218; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {219; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fdivr.nxv4f32(<vscale x 4 x i1> [[PG]], <vscale x 4 x float> splat (float 6.000000e+00), <vscale x 4 x float> splat (float 1.200000e+01))220; CHECK-NEXT: ret <vscale x 4 x float> [[R]]221;222 %r = call <vscale x 4 x float> @llvm.aarch64.sve.fdivr.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 6.0), <vscale x 4 x float> splat (float 12.0))223 ret <vscale x 4 x float> %r224}225 226define <vscale x 4 x float> @constant_fmul(<vscale x 4 x i1> %pg) #0 {227; CHECK-LABEL: define <vscale x 4 x float> @constant_fmul(228; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {229; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x float> splat (float 4.200000e+01), <vscale x 4 x float> splat (float 7.000000e+00)230; CHECK-NEXT: ret <vscale x 4 x float> [[R]]231;232 %r = call <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 7.0), <vscale x 4 x float> splat (float 6.0))233 ret <vscale x 4 x float> %r234}235 236define <vscale x 4 x float> @constant_fmul_u(<vscale x 4 x i1> %pg) #0 {237; CHECK-LABEL: define <vscale x 4 x float> @constant_fmul_u(238; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {239; CHECK-NEXT: ret <vscale x 4 x float> splat (float 4.200000e+01)240;241 %r = call <vscale x 4 x float> @llvm.aarch64.sve.fmul.u.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 7.0), <vscale x 4 x float> splat (float 6.0))242 ret <vscale x 4 x float> %r243}244 245define <vscale x 4 x float> @constant_fsub(<vscale x 4 x i1> %pg) #0 {246; CHECK-LABEL: define <vscale x 4 x float> @constant_fsub(247; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {248; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x float> splat (float 1.000000e+00), <vscale x 4 x float> splat (float 7.000000e+00)249; CHECK-NEXT: ret <vscale x 4 x float> [[R]]250;251 %r = call <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 7.0), <vscale x 4 x float> splat (float 6.0))252 ret <vscale x 4 x float> %r253}254 255define <vscale x 4 x float> @constant_fsub_u(<vscale x 4 x i1> %pg) #0 {256; CHECK-LABEL: define <vscale x 4 x float> @constant_fsub_u(257; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {258; CHECK-NEXT: ret <vscale x 4 x float> splat (float 1.000000e+00)259;260 %r = call <vscale x 4 x float> @llvm.aarch64.sve.fsub.u.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 7.0), <vscale x 4 x float> splat (float 6.0))261 ret <vscale x 4 x float> %r262}263 264define <vscale x 4 x float> @constant_fsubr(<vscale x 4 x i1> %pg) #0 {265; CHECK-LABEL: define <vscale x 4 x float> @constant_fsubr(266; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {267; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fsubr.nxv4f32(<vscale x 4 x i1> [[PG]], <vscale x 4 x float> splat (float 6.000000e+00), <vscale x 4 x float> splat (float 7.000000e+00))268; CHECK-NEXT: ret <vscale x 4 x float> [[R]]269;270 %r = call <vscale x 4 x float> @llvm.aarch64.sve.fsubr.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 6.0), <vscale x 4 x float> splat (float 7.0))271 ret <vscale x 4 x float> %r272}273 274define <vscale x 4 x i32> @constant_mul(<vscale x 4 x i1> %pg) #0 {275; CHECK-LABEL: define <vscale x 4 x i32> @constant_mul(276; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {277; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 21), <vscale x 4 x i32> splat (i32 7)278; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]279;280 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))281 ret <vscale x 4 x i32> %r282}283 284define <vscale x 4 x i32> @constant_mul_u(<vscale x 4 x i1> %pg) #0 {285; CHECK-LABEL: define <vscale x 4 x i32> @constant_mul_u(286; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {287; CHECK-NEXT: ret <vscale x 4 x i32> splat (i32 21)288;289 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))290 ret <vscale x 4 x i32> %r291}292 293define <vscale x 4 x i32> @constant_orr(<vscale x 4 x i1> %pg) #0 {294; CHECK-LABEL: define <vscale x 4 x i32> @constant_orr(295; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {296; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 15), <vscale x 4 x i32> splat (i32 13)297; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]298;299 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 13), <vscale x 4 x i32> splat (i32 3))300 ret <vscale x 4 x i32> %r301}302 303define <vscale x 4 x i32> @constant_orr_u(<vscale x 4 x i1> %pg) #0 {304; CHECK-LABEL: define <vscale x 4 x i32> @constant_orr_u(305; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {306; CHECK-NEXT: ret <vscale x 4 x i32> splat (i32 15)307;308 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 13), <vscale x 4 x i32> splat (i32 3))309 ret <vscale x 4 x i32> %r310}311 312define <vscale x 4 x i32> @constant_sdiv(<vscale x 4 x i1> %pg) #0 {313; CHECK-LABEL: define <vscale x 4 x i32> @constant_sdiv(314; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {315; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -2), <vscale x 4 x i32> splat (i32 -7)316; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]317;318 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 -7), <vscale x 4 x i32> splat (i32 3))319 ret <vscale x 4 x i32> %r320}321 322; The intrinsic's IR equivalent does not support divide-by-zero.323define <vscale x 4 x i32> @constant_sdiv_by_zero(<vscale x 4 x i1> %pg) #0 {324; CHECK-LABEL: define <vscale x 4 x i32> @constant_sdiv_by_zero(325; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {326; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -7), <vscale x 4 x i32> zeroinitializer)327; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]328;329 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 -7), <vscale x 4 x i32> splat (i32 0))330 ret <vscale x 4 x i32> %r331}332 333; The intrinsic's IR equivalent does not support overflow.334define <vscale x 4 x i32> @constant_sdiv_with_overflow(<vscale x 4 x i1> %pg) #0 {335; CHECK-LABEL: define <vscale x 4 x i32> @constant_sdiv_with_overflow(336; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {337; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -2147483648), <vscale x 4 x i32> splat (i32 -1))338; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]339;340 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 -2147483648), <vscale x 4 x i32> splat (i32 -1))341 ret <vscale x 4 x i32> %r342}343 344define <vscale x 4 x i32> @constant_sdiv_u(<vscale x 4 x i1> %pg) #0 {345; CHECK-LABEL: define <vscale x 4 x i32> @constant_sdiv_u(346; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {347; CHECK-NEXT: ret <vscale x 4 x i32> splat (i32 2)348;349 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 -7), <vscale x 4 x i32> splat (i32 -3))350 ret <vscale x 4 x i32> %r351}352 353; The intrinsic's IR equivalent does not support divide-by-zero.354define <vscale x 4 x i32> @constant_sdiv_u_by_zero(<vscale x 4 x i1> %pg) #0 {355; CHECK-LABEL: define <vscale x 4 x i32> @constant_sdiv_u_by_zero(356; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {357; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -7), <vscale x 4 x i32> zeroinitializer)358; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]359;360 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 -7), <vscale x 4 x i32> splat (i32 0))361 ret <vscale x 4 x i32> %r362}363 364; The intrinsic's IR equivalent does not support overflow.365define <vscale x 4 x i32> @constant_sdiv_u_with_overflow(<vscale x 4 x i1> %pg) #0 {366; CHECK-LABEL: define <vscale x 4 x i32> @constant_sdiv_u_with_overflow(367; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {368; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -2147483648), <vscale x 4 x i32> splat (i32 -1))369; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]370;371 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 -2147483648), <vscale x 4 x i32> splat (i32 -1))372 ret <vscale x 4 x i32> %r373}374 375define <vscale x 4 x i32> @constant_sdivr(<vscale x 4 x i1> %pg) #0 {376; CHECK-LABEL: define <vscale x 4 x i32> @constant_sdivr(377; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {378; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 3), <vscale x 4 x i32> splat (i32 -7))379; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]380;381 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 3), <vscale x 4 x i32> splat (i32 -7))382 ret <vscale x 4 x i32> %r383}384 385; The intrinsic's IR equivalent does not support divide-by-zero.386define <vscale x 4 x i32> @constant_sdivr_by_zero(<vscale x 4 x i1> %pg) #0 {387; CHECK-LABEL: define <vscale x 4 x i32> @constant_sdivr_by_zero(388; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {389; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> splat (i32 -7))390; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]391;392 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 0), <vscale x 4 x i32> splat (i32 -7))393 ret <vscale x 4 x i32> %r394}395 396; The intrinsic's IR equivalent does not support overflow.397define <vscale x 4 x i32> @constant_sdivr_with_overflow(<vscale x 4 x i1> %pg) #0 {398; CHECK-LABEL: define <vscale x 4 x i32> @constant_sdivr_with_overflow(399; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {400; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i32> splat (i32 -2147483648))401; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]402;403 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i32> splat (i32 -2147483648))404 ret <vscale x 4 x i32> %r405}406 407define <vscale x 4 x i32> @constant_sub(<vscale x 4 x i1> %pg) #0 {408; CHECK-LABEL: define <vscale x 4 x i32> @constant_sub(409; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {410; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 4), <vscale x 4 x i32> splat (i32 7)411; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]412;413 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))414 ret <vscale x 4 x i32> %r415}416 417define <vscale x 4 x i32> @constant_sub_u(<vscale x 4 x i1> %pg) #0 {418; CHECK-LABEL: define <vscale x 4 x i32> @constant_sub_u(419; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {420; CHECK-NEXT: ret <vscale x 4 x i32> splat (i32 4)421;422 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))423 ret <vscale x 4 x i32> %r424}425 426define <vscale x 4 x i32> @constant_subr(<vscale x 4 x i1> %pg) #0 {427; CHECK-LABEL: define <vscale x 4 x i32> @constant_subr(428; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {429; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))430; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]431;432 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))433 ret <vscale x 4 x i32> %r434}435 436define <vscale x 4 x i32> @constant_udiv(<vscale x 4 x i1> %pg) #0 {437; CHECK-LABEL: define <vscale x 4 x i32> @constant_udiv(438; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {439; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 2), <vscale x 4 x i32> splat (i32 7)440; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]441;442 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))443 ret <vscale x 4 x i32> %r444}445 446; The intrinsic's IR equivalent does not support divide-by-zero.447define <vscale x 4 x i32> @constant_udiv_by_zero(<vscale x 4 x i1> %pg) #0 {448; CHECK-LABEL: define <vscale x 4 x i32> @constant_udiv_by_zero(449; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {450; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> zeroinitializer)451; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]452;453 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 0))454 ret <vscale x 4 x i32> %r455}456 457define <vscale x 4 x i32> @constant_udiv_u(<vscale x 4 x i1> %pg) #0 {458; CHECK-LABEL: define <vscale x 4 x i32> @constant_udiv_u(459; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {460; CHECK-NEXT: ret <vscale x 4 x i32> splat (i32 3)461;462 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 9), <vscale x 4 x i32> splat (i32 3))463 ret <vscale x 4 x i32> %r464}465 466; The intrinsic's IR equivalent does not support divide-by-zero.467define <vscale x 4 x i32> @constant_udiv_u_by_zero(<vscale x 4 x i1> %pg) #0 {468; CHECK-LABEL: define <vscale x 4 x i32> @constant_udiv_u_by_zero(469; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {470; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 9), <vscale x 4 x i32> zeroinitializer)471; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]472;473 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 9), <vscale x 4 x i32> splat (i32 0))474 ret <vscale x 4 x i32> %r475}476 477define <vscale x 4 x i32> @constant_udivr(<vscale x 4 x i1> %pg) #0 {478; CHECK-LABEL: define <vscale x 4 x i32> @constant_udivr(479; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {480; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 3), <vscale x 4 x i32> splat (i32 7))481; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]482;483 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 3), <vscale x 4 x i32> splat (i32 7))484 ret <vscale x 4 x i32> %r485}486 487; The intrinsic's IR equivalent does not support divide-by-zero.488define <vscale x 4 x i32> @constant_udivr_by_zero(<vscale x 4 x i1> %pg) #0 {489; CHECK-LABEL: define <vscale x 4 x i32> @constant_udivr_by_zero(490; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {491; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> splat (i32 7))492; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]493;494 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 0), <vscale x 4 x i32> splat (i32 7))495 ret <vscale x 4 x i32> %r496}497 498declare <vscale x 4 x i32> @llvm.aarch64.sve.dup.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32)499 500declare <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)501declare <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)502declare <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)503declare <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)504declare <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)505declare <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)506declare <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)507declare <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)508declare <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)509declare <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)510declare <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)511 512declare <vscale x 4 x i32> @llvm.aarch64.sve.add.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)513declare <vscale x 4 x i32> @llvm.aarch64.sve.and.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)514declare <vscale x 4 x i32> @llvm.aarch64.sve.eor.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)515declare <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)516declare <vscale x 4 x i32> @llvm.aarch64.sve.orr.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)517declare <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)518declare <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)519declare <vscale x 4 x i32> @llvm.aarch64.sve.udiv.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)520 521declare <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)522declare <vscale x 4 x float> @llvm.aarch64.sve.fdiv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)523declare <vscale x 4 x float> @llvm.aarch64.sve.fdivr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)524declare <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)525declare <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)526declare <vscale x 4 x float> @llvm.aarch64.sve.fsubr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)527 528declare <vscale x 4 x float> @llvm.aarch64.sve.fadd.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)529declare <vscale x 4 x float> @llvm.aarch64.sve.fdiv.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)530declare <vscale x 4 x float> @llvm.aarch64.sve.fmul.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)531declare <vscale x 4 x float> @llvm.aarch64.sve.fsub.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)532 533attributes #0 = { "target-features"="+sve" }534