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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S -passes=instcombine < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6define <vscale x 16 x i8> @constant_asr_i8_shift_by_0(<vscale x 16 x i1> %pg) #0 {7; CHECK-LABEL: define <vscale x 16 x i8> @constant_asr_i8_shift_by_0(8; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0:[0-9]+]] {9; CHECK-NEXT: ret <vscale x 16 x i8> splat (i8 7)10;11 %r = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 7), <vscale x 16 x i8> splat (i8 0))12 ret <vscale x 16 x i8> %r13}14 15define <vscale x 16 x i8> @constant_asr_i8_shift_by_1(<vscale x 16 x i1> %pg) #0 {16; CHECK-LABEL: define <vscale x 16 x i8> @constant_asr_i8_shift_by_1(17; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {18; CHECK-NEXT: [[R:%.*]] = select <vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 -32), <vscale x 16 x i8> splat (i8 -63)19; CHECK-NEXT: ret <vscale x 16 x i8> [[R]]20;21 %r = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 193), <vscale x 16 x i8> splat (i8 1))22 ret <vscale x 16 x i8> %r23}24 25; data = 0x8026define <vscale x 16 x i8> @constant_asr_i8_shift_by_7(<vscale x 16 x i1> %pg) #0 {27; CHECK-LABEL: define <vscale x 16 x i8> @constant_asr_i8_shift_by_7(28; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {29; CHECK-NEXT: [[R:%.*]] = select <vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i8> splat (i8 -128)30; CHECK-NEXT: ret <vscale x 16 x i8> [[R]]31;32 %r = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 128), <vscale x 16 x i8> splat (i8 7))33 ret <vscale x 16 x i8> %r34}35 36; The intrinsic's IR equivalent only supports shift amounts in the range 0-7.37; data = 0x8038define <vscale x 16 x i8> @constant_asr_i8_shift_by_8(<vscale x 16 x i1> %pg) #0 {39; CHECK-LABEL: define <vscale x 16 x i8> @constant_asr_i8_shift_by_8(40; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {41; CHECK-NEXT: [[R:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 -128), <vscale x 16 x i8> splat (i8 8))42; CHECK-NEXT: ret <vscale x 16 x i8> [[R]]43;44 %r = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 128), <vscale x 16 x i8> splat (i8 8))45 ret <vscale x 16 x i8> %r46}47 48; data = 0x800049define <vscale x 8 x i16> @constant_asr_i16_shift_by_15(<vscale x 8 x i1> %pg) #0 {50; CHECK-LABEL: define <vscale x 8 x i16> @constant_asr_i16_shift_by_15(51; CHECK-SAME: <vscale x 8 x i1> [[PG:%.*]]) #[[ATTR0]] {52; CHECK-NEXT: [[R:%.*]] = select <vscale x 8 x i1> [[PG]], <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i16> splat (i16 -32768)53; CHECK-NEXT: ret <vscale x 8 x i16> [[R]]54;55 %r = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> splat (i16 32768), <vscale x 8 x i16> splat (i16 15))56 ret <vscale x 8 x i16> %r57}58 59; The intrinsic's IR equivalent only supports shift amounts in the range 0-15.60; data = 0x800061define <vscale x 8 x i16> @constant_asr_i16_shift_by_16(<vscale x 8 x i1> %pg) #0 {62; CHECK-LABEL: define <vscale x 8 x i16> @constant_asr_i16_shift_by_16(63; CHECK-SAME: <vscale x 8 x i1> [[PG:%.*]]) #[[ATTR0]] {64; CHECK-NEXT: [[R:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> [[PG]], <vscale x 8 x i16> splat (i16 -32768), <vscale x 8 x i16> splat (i16 16))65; CHECK-NEXT: ret <vscale x 8 x i16> [[R]]66;67 %r = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> splat (i16 32768), <vscale x 8 x i16> splat (i16 16))68 ret <vscale x 8 x i16> %r69}70 71; data = 0x80000000072define <vscale x 4 x i32> @constant_asr_i32_shift_by_31(<vscale x 4 x i1> %pg) #0 {73; CHECK-LABEL: define <vscale x 4 x i32> @constant_asr_i32_shift_by_31(74; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {75; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i32> splat (i32 -2147483648)76; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]77;78 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 2147483648), <vscale x 4 x i32> splat (i32 31))79 ret <vscale x 4 x i32> %r80}81 82; The intrinsic's IR equivalent only supports shift amounts in the range 0-31.83; data = 0x8000000084define <vscale x 4 x i32> @constant_asr_i32_shift_by_32(<vscale x 4 x i1> %pg) #0 {85; CHECK-LABEL: define <vscale x 4 x i32> @constant_asr_i32_shift_by_32(86; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {87; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -2147483648), <vscale x 4 x i32> splat (i32 32))88; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]89;90 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 2147483648), <vscale x 4 x i32> splat (i32 32))91 ret <vscale x 4 x i32> %r92}93 94; data = 0x800000000000000095define <vscale x 2 x i64> @constant_asr_i64_shift_by_63(<vscale x 2 x i1> %pg) #0 {96; CHECK-LABEL: define <vscale x 2 x i64> @constant_asr_i64_shift_by_63(97; CHECK-SAME: <vscale x 2 x i1> [[PG:%.*]]) #[[ATTR0]] {98; CHECK-NEXT: [[R:%.*]] = select <vscale x 2 x i1> [[PG]], <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i64> splat (i64 -9223372036854775808)99; CHECK-NEXT: ret <vscale x 2 x i64> [[R]]100;101 %r = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> splat (i64 9223372036854775808), <vscale x 2 x i64> splat (i64 63))102 ret <vscale x 2 x i64> %r103}104 105; The intrinsic's IR equivalent only supports shift amounts in the range 0-63.106; data = 0x8000000000000000107define <vscale x 2 x i64> @constant_asr_i64_shift_by_64(<vscale x 2 x i1> %pg) #0 {108; CHECK-LABEL: define <vscale x 2 x i64> @constant_asr_i64_shift_by_64(109; CHECK-SAME: <vscale x 2 x i1> [[PG:%.*]]) #[[ATTR0]] {110; CHECK-NEXT: [[R:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> [[PG]], <vscale x 2 x i64> splat (i64 -9223372036854775808), <vscale x 2 x i64> splat (i64 64))111; CHECK-NEXT: ret <vscale x 2 x i64> [[R]]112;113 %r = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> splat (i64 9223372036854775808), <vscale x 2 x i64> splat (i64 64))114 ret <vscale x 2 x i64> %r115}116 117define <vscale x 16 x i8> @constant_lsl_i8_shift_by_0(<vscale x 16 x i1> %pg) #0 {118; CHECK-LABEL: define <vscale x 16 x i8> @constant_lsl_i8_shift_by_0(119; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {120; CHECK-NEXT: ret <vscale x 16 x i8> splat (i8 7)121;122 %r = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 7), <vscale x 16 x i8> splat (i8 0))123 ret <vscale x 16 x i8> %r124}125 126define <vscale x 16 x i8> @constant_lsl_i8_shift_by_1(<vscale x 16 x i1> %pg) #0 {127; CHECK-LABEL: define <vscale x 16 x i8> @constant_lsl_i8_shift_by_1(128; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {129; CHECK-NEXT: [[R:%.*]] = select <vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 -126), <vscale x 16 x i8> splat (i8 -63)130; CHECK-NEXT: ret <vscale x 16 x i8> [[R]]131;132 %r = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 193), <vscale x 16 x i8> splat (i8 1))133 ret <vscale x 16 x i8> %r134}135 136; result = 0x80137define <vscale x 16 x i8> @constant_lsl_i8_shift_by_7(<vscale x 16 x i1> %pg) #0 {138; CHECK-LABEL: define <vscale x 16 x i8> @constant_lsl_i8_shift_by_7(139; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {140; CHECK-NEXT: [[R:%.*]] = select <vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 -128), <vscale x 16 x i8> splat (i8 1)141; CHECK-NEXT: ret <vscale x 16 x i8> [[R]]142;143 %r = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 1), <vscale x 16 x i8> splat (i8 7))144 ret <vscale x 16 x i8> %r145}146 147; The intrinsic's IR equivalent only supports shift amounts in the range 0-7.148define <vscale x 16 x i8> @constant_lsl_i8_shift_by_8(<vscale x 16 x i1> %pg) #0 {149; CHECK-LABEL: define <vscale x 16 x i8> @constant_lsl_i8_shift_by_8(150; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {151; CHECK-NEXT: [[R:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 1), <vscale x 16 x i8> splat (i8 8))152; CHECK-NEXT: ret <vscale x 16 x i8> [[R]]153;154 %r = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 1), <vscale x 16 x i8> splat (i8 8))155 ret <vscale x 16 x i8> %r156}157 158; result = 0x8000159define <vscale x 8 x i16> @constant_lsl_i16_shift_by_15(<vscale x 8 x i1> %pg) #0 {160; CHECK-LABEL: define <vscale x 8 x i16> @constant_lsl_i16_shift_by_15(161; CHECK-SAME: <vscale x 8 x i1> [[PG:%.*]]) #[[ATTR0]] {162; CHECK-NEXT: [[R:%.*]] = select <vscale x 8 x i1> [[PG]], <vscale x 8 x i16> splat (i16 -32768), <vscale x 8 x i16> splat (i16 1)163; CHECK-NEXT: ret <vscale x 8 x i16> [[R]]164;165 %r = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> splat (i16 1), <vscale x 8 x i16> splat (i16 15))166 ret <vscale x 8 x i16> %r167}168 169; The intrinsic's IR equivalent only supports shift amounts in the range 0-15.170define <vscale x 8 x i16> @constant_lsl_i16_shift_by_16(<vscale x 8 x i1> %pg) #0 {171; CHECK-LABEL: define <vscale x 8 x i16> @constant_lsl_i16_shift_by_16(172; CHECK-SAME: <vscale x 8 x i1> [[PG:%.*]]) #[[ATTR0]] {173; CHECK-NEXT: [[R:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> [[PG]], <vscale x 8 x i16> splat (i16 1), <vscale x 8 x i16> splat (i16 16))174; CHECK-NEXT: ret <vscale x 8 x i16> [[R]]175;176 %r = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> splat (i16 1), <vscale x 8 x i16> splat (i16 16))177 ret <vscale x 8 x i16> %r178}179 180; result = 0x800000000181define <vscale x 4 x i32> @constant_lsl_i32_shift_by_31(<vscale x 4 x i1> %pg) #0 {182; CHECK-LABEL: define <vscale x 4 x i32> @constant_lsl_i32_shift_by_31(183; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {184; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -2147483648), <vscale x 4 x i32> splat (i32 1)185; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]186;187 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 1), <vscale x 4 x i32> splat (i32 31))188 ret <vscale x 4 x i32> %r189}190 191; The intrinsic's IR equivalent only supports shift amounts in the range 0-31.192define <vscale x 4 x i32> @constant_lsl_i32_shift_by_32(<vscale x 4 x i1> %pg) #0 {193; CHECK-LABEL: define <vscale x 4 x i32> @constant_lsl_i32_shift_by_32(194; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {195; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 1), <vscale x 4 x i32> splat (i32 32))196; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]197;198 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 1), <vscale x 4 x i32> splat (i32 32))199 ret <vscale x 4 x i32> %r200}201 202; result = 0x8000000000000000203define <vscale x 2 x i64> @constant_lsl_i64_shift_by_63(<vscale x 2 x i1> %pg) #0 {204; CHECK-LABEL: define <vscale x 2 x i64> @constant_lsl_i64_shift_by_63(205; CHECK-SAME: <vscale x 2 x i1> [[PG:%.*]]) #[[ATTR0]] {206; CHECK-NEXT: [[R:%.*]] = select <vscale x 2 x i1> [[PG]], <vscale x 2 x i64> splat (i64 -9223372036854775808), <vscale x 2 x i64> splat (i64 1)207; CHECK-NEXT: ret <vscale x 2 x i64> [[R]]208;209 %r = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> splat (i64 1), <vscale x 2 x i64> splat (i64 63))210 ret <vscale x 2 x i64> %r211}212 213; The intrinsic's IR equivalent only supports shift amounts in the range 0-63.214define <vscale x 2 x i64> @constant_lsl_i64_shift_by_64(<vscale x 2 x i1> %pg) #0 {215; CHECK-LABEL: define <vscale x 2 x i64> @constant_lsl_i64_shift_by_64(216; CHECK-SAME: <vscale x 2 x i1> [[PG:%.*]]) #[[ATTR0]] {217; CHECK-NEXT: [[R:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> [[PG]], <vscale x 2 x i64> splat (i64 1), <vscale x 2 x i64> splat (i64 64))218; CHECK-NEXT: ret <vscale x 2 x i64> [[R]]219;220 %r = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> splat (i64 1), <vscale x 2 x i64> splat (i64 64))221 ret <vscale x 2 x i64> %r222}223 224define <vscale x 16 x i8> @constant_lsr_i8_shift_by_0(<vscale x 16 x i1> %pg) #0 {225; CHECK-LABEL: define <vscale x 16 x i8> @constant_lsr_i8_shift_by_0(226; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {227; CHECK-NEXT: ret <vscale x 16 x i8> splat (i8 7)228;229 %r = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 7), <vscale x 16 x i8> splat (i8 0))230 ret <vscale x 16 x i8> %r231}232 233define <vscale x 16 x i8> @constant_lsr_i8_shift_by_1(<vscale x 16 x i1> %pg) #0 {234; CHECK-LABEL: define <vscale x 16 x i8> @constant_lsr_i8_shift_by_1(235; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {236; CHECK-NEXT: [[R:%.*]] = select <vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 96), <vscale x 16 x i8> splat (i8 -63)237; CHECK-NEXT: ret <vscale x 16 x i8> [[R]]238;239 %r = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 193), <vscale x 16 x i8> splat (i8 1))240 ret <vscale x 16 x i8> %r241}242 243; data = 0x80244define <vscale x 16 x i8> @constant_lsr_i8_shift_by_7(<vscale x 16 x i1> %pg) #0 {245; CHECK-LABEL: define <vscale x 16 x i8> @constant_lsr_i8_shift_by_7(246; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {247; CHECK-NEXT: [[R:%.*]] = select <vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 1), <vscale x 16 x i8> splat (i8 -128)248; CHECK-NEXT: ret <vscale x 16 x i8> [[R]]249;250 %r = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 128), <vscale x 16 x i8> splat (i8 7))251 ret <vscale x 16 x i8> %r252}253 254; The intrinsic's IR equivalent only supports shift amounts in the range 0-7.255; data = 0x80256define <vscale x 16 x i8> @constant_lsr_i8_shift_by_8(<vscale x 16 x i1> %pg) #0 {257; CHECK-LABEL: define <vscale x 16 x i8> @constant_lsr_i8_shift_by_8(258; CHECK-SAME: <vscale x 16 x i1> [[PG:%.*]]) #[[ATTR0]] {259; CHECK-NEXT: [[R:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> splat (i8 -128), <vscale x 16 x i8> splat (i8 8))260; CHECK-NEXT: ret <vscale x 16 x i8> [[R]]261;262 %r = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> splat (i8 128), <vscale x 16 x i8> splat (i8 8))263 ret <vscale x 16 x i8> %r264}265 266; data = 0x8000267define <vscale x 8 x i16> @constant_lsr_i16_shift_by_15(<vscale x 8 x i1> %pg) #0 {268; CHECK-LABEL: define <vscale x 8 x i16> @constant_lsr_i16_shift_by_15(269; CHECK-SAME: <vscale x 8 x i1> [[PG:%.*]]) #[[ATTR0]] {270; CHECK-NEXT: [[R:%.*]] = select <vscale x 8 x i1> [[PG]], <vscale x 8 x i16> splat (i16 1), <vscale x 8 x i16> splat (i16 -32768)271; CHECK-NEXT: ret <vscale x 8 x i16> [[R]]272;273 %r = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> splat (i16 32768), <vscale x 8 x i16> splat (i16 15))274 ret <vscale x 8 x i16> %r275}276 277; The intrinsic's IR equivalent only supports shift amounts in the range 0-15.278; data = 0x8000279define <vscale x 8 x i16> @constant_lsr_i16_shift_by_16(<vscale x 8 x i1> %pg) #0 {280; CHECK-LABEL: define <vscale x 8 x i16> @constant_lsr_i16_shift_by_16(281; CHECK-SAME: <vscale x 8 x i1> [[PG:%.*]]) #[[ATTR0]] {282; CHECK-NEXT: [[R:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> [[PG]], <vscale x 8 x i16> splat (i16 -32768), <vscale x 8 x i16> splat (i16 16))283; CHECK-NEXT: ret <vscale x 8 x i16> [[R]]284;285 %r = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> splat (i16 32768), <vscale x 8 x i16> splat (i16 16))286 ret <vscale x 8 x i16> %r287}288 289; data = 0x800000000290define <vscale x 4 x i32> @constant_lsr_i32_shift_by_31(<vscale x 4 x i1> %pg) #0 {291; CHECK-LABEL: define <vscale x 4 x i32> @constant_lsr_i32_shift_by_31(292; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {293; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 1), <vscale x 4 x i32> splat (i32 -2147483648)294; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]295;296 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 2147483648), <vscale x 4 x i32> splat (i32 31))297 ret <vscale x 4 x i32> %r298}299 300; The intrinsic's IR equivalent only supports shift amounts in the range 0-31.301; data = 0x80000000302define <vscale x 4 x i32> @constant_lsr_i32_shift_by_32(<vscale x 4 x i1> %pg) #0 {303; CHECK-LABEL: define <vscale x 4 x i32> @constant_lsr_i32_shift_by_32(304; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {305; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -2147483648), <vscale x 4 x i32> splat (i32 32))306; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]307;308 %r = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 2147483648), <vscale x 4 x i32> splat (i32 32))309 ret <vscale x 4 x i32> %r310}311 312; data = 0x8000000000000000313define <vscale x 2 x i64> @constant_lsr_i64_shift_by_63(<vscale x 2 x i1> %pg) #0 {314; CHECK-LABEL: define <vscale x 2 x i64> @constant_lsr_i64_shift_by_63(315; CHECK-SAME: <vscale x 2 x i1> [[PG:%.*]]) #[[ATTR0]] {316; CHECK-NEXT: [[R:%.*]] = select <vscale x 2 x i1> [[PG]], <vscale x 2 x i64> splat (i64 1), <vscale x 2 x i64> splat (i64 -9223372036854775808)317; CHECK-NEXT: ret <vscale x 2 x i64> [[R]]318;319 %r = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> splat (i64 9223372036854775808), <vscale x 2 x i64> splat (i64 63))320 ret <vscale x 2 x i64> %r321}322 323; The intrinsic's IR equivalent only supports shift amounts in the range 0-63.324; data = 0x8000000000000000325define <vscale x 2 x i64> @constant_lsr_i64_shift_by_64(<vscale x 2 x i1> %pg) #0 {326; CHECK-LABEL: define <vscale x 2 x i64> @constant_lsr_i64_shift_by_64(327; CHECK-SAME: <vscale x 2 x i1> [[PG:%.*]]) #[[ATTR0]] {328; CHECK-NEXT: [[R:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> [[PG]], <vscale x 2 x i64> splat (i64 -9223372036854775808), <vscale x 2 x i64> splat (i64 64))329; CHECK-NEXT: ret <vscale x 2 x i64> [[R]]330;331 %r = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> splat (i64 9223372036854775808), <vscale x 2 x i64> splat (i64 64))332 ret <vscale x 2 x i64> %r333}334 335declare <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)336declare <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)337declare <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)338declare <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)339 340declare <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)341declare <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)342declare <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)343declare <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)344 345declare <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)346declare <vscale x 8 x i16> @llvm.aarch64.sve.lsr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)347declare <vscale x 4 x i32> @llvm.aarch64.sve.lsr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)348declare <vscale x 2 x i64> @llvm.aarch64.sve.lsr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)349 350attributes #0 = { "target-features"="+sve" }351