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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -passes=instcombine -S < %s | FileCheck %s3 4; --------------------------------------------------------------------5; llvm.amdgcn.image.sample a16 is disabled on pre-gfx96; --------------------------------------------------------------------7 8declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32.v8i32.v4i32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #19declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32.v8i32.v4i32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #110declare <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32.v8i32.v4i32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #111declare <4 x float> @llvm.amdgcn.image.sample.cube.v4f32.f32.v8i32.v4i32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #112declare <4 x float> @llvm.amdgcn.image.sample.1darray.v4f32.f32.v8i32.v4i32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #113declare <4 x float> @llvm.amdgcn.image.sample.2darray.v4f32.f32.v8i32.v4i32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #114 15define amdgpu_kernel void @image_sample_a16_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s) {16; CHECK-LABEL: @image_sample_a16_1d(17; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float18; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32.v8i32.v4i32(i32 15, float [[S32]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)19; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 1620; CHECK-NEXT: ret void21;22 %s32 = fpext half %s to float23 %res = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32.v8i32(i32 15, float %s32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)24 store <4 x float> %res, ptr addrspace(1) %out25 ret void26}27 28define amdgpu_kernel void @image_sample_a16_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t) {29; CHECK-LABEL: @image_sample_a16_2d(30; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float31; CHECK-NEXT: [[T32:%.*]] = fpext half [[T:%.*]] to float32; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32.v8i32.v4i32(i32 15, float [[S32]], float [[T32]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)33; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 1634; CHECK-NEXT: ret void35;36 %s32 = fpext half %s to float37 %t32 = fpext half %t to float38 %res = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32.v8i32(i32 15, float %s32, float %t32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)39 store <4 x float> %res, ptr addrspace(1) %out40 ret void41}42 43define amdgpu_kernel void @image_sample_a16_3d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %r) {44; CHECK-LABEL: @image_sample_a16_3d(45; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float46; CHECK-NEXT: [[T32:%.*]] = fpext half [[T:%.*]] to float47; CHECK-NEXT: [[R32:%.*]] = fpext half [[R:%.*]] to float48; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32.v8i32.v4i32(i32 15, float [[S32]], float [[T32]], float [[R32]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)49; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 1650; CHECK-NEXT: ret void51;52 %s32 = fpext half %s to float53 %t32 = fpext half %t to float54 %r32 = fpext half %r to float55 %res = call <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32.v8i32(i32 15, float %s32, float %t32, float %r32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)56 store <4 x float> %res, ptr addrspace(1) %out57 ret void58}59 60define amdgpu_kernel void @image_sample_a16_cube(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %face) {61;62; CHECK-LABEL: @image_sample_a16_cube(63; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float64; CHECK-NEXT: [[T32:%.*]] = fpext half [[T:%.*]] to float65; CHECK-NEXT: [[FACE32:%.*]] = fpext half [[FACE:%.*]] to float66; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.cube.v4f32.f32.v8i32.v4i32(i32 15, float [[S32]], float [[T32]], float [[FACE32]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)67; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 1668; CHECK-NEXT: ret void69;70 %s32 = fpext half %s to float71 %t32 = fpext half %t to float72 %face32 = fpext half %face to float73 %res = call <4 x float> @llvm.amdgcn.image.sample.cube.v4f32.f32.v8i32(i32 15, float %s32, float %t32, float %face32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)74 store <4 x float> %res, ptr addrspace(1) %out75 ret void76}77 78define amdgpu_kernel void @image_sample_a16_1darray(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %slice) {79; CHECK-LABEL: @image_sample_a16_1darray(80; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float81; CHECK-NEXT: [[SLICE32:%.*]] = fpext half [[SLICE:%.*]] to float82; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.1darray.v4f32.f32.v8i32.v4i32(i32 15, float [[S32]], float [[SLICE32]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)83; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 1684; CHECK-NEXT: ret void85;86 %s32 = fpext half %s to float87 %slice32 = fpext half %slice to float88 %res = call <4 x float> @llvm.amdgcn.image.sample.1darray.v4f32.f32.v8i32(i32 15, float %s32, float %slice32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)89 store <4 x float> %res, ptr addrspace(1) %out90 ret void91}92 93define amdgpu_kernel void @image_sample_a16_2darray(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %slice) {94; CHECK-LABEL: @image_sample_a16_2darray(95; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float96; CHECK-NEXT: [[T32:%.*]] = fpext half [[T:%.*]] to float97; CHECK-NEXT: [[SLICE32:%.*]] = fpext half [[SLICE:%.*]] to float98; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.2darray.v4f32.f32.v8i32.v4i32(i32 15, float [[S32]], float [[T32]], float [[SLICE32]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)99; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 16100; CHECK-NEXT: ret void101;102 %s32 = fpext half %s to float103 %t32 = fpext half %t to float104 %slice32 = fpext half %slice to float105 %res = call <4 x float> @llvm.amdgcn.image.sample.2darray.v4f32.f32.v8i32(i32 15, float %s32, float %t32, float %slice32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)106 store <4 x float> %res, ptr addrspace(1) %out107 ret void108}109