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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -passes=instcombine -S < %s | FileCheck %s3 4; --------------------------------------------------------------------5; llvm.amdgcn.rcp6; --------------------------------------------------------------------7 8declare float @llvm.amdgcn.rcp.f32(float) nounwind readnone9declare double @llvm.amdgcn.rcp.f64(double) nounwind readnone10 11define float @test_constant_fold_rcp_f32_poison() nounwind {12; CHECK-LABEL: @test_constant_fold_rcp_f32_poison(13; CHECK-NEXT: ret float poison14;15 %val = call float @llvm.amdgcn.rcp.f32(float poison) nounwind readnone16 ret float %val17}18 19define float @test_constant_fold_rcp_f32_undef() nounwind {20; CHECK-LABEL: @test_constant_fold_rcp_f32_undef(21; CHECK-NEXT: ret float 0x7FF800000000000022;23 %val = call float @llvm.amdgcn.rcp.f32(float undef) nounwind readnone24 ret float %val25}26 27define float @test_constant_fold_rcp_f32_1() nounwind {28; CHECK-LABEL: @test_constant_fold_rcp_f32_1(29; CHECK-NEXT: ret float 1.000000e+0030;31 %val = call float @llvm.amdgcn.rcp.f32(float 1.0) nounwind readnone32 ret float %val33}34 35define double @test_constant_fold_rcp_f64_1() nounwind {36; CHECK-LABEL: @test_constant_fold_rcp_f64_1(37; CHECK-NEXT: ret double 1.000000e+0038;39 %val = call double @llvm.amdgcn.rcp.f64(double 1.0) nounwind readnone40 ret double %val41}42 43define float @test_constant_fold_rcp_f32_half() nounwind {44; CHECK-LABEL: @test_constant_fold_rcp_f32_half(45; CHECK-NEXT: ret float 2.000000e+0046;47 %val = call float @llvm.amdgcn.rcp.f32(float 0.5) nounwind readnone48 ret float %val49}50 51define double @test_constant_fold_rcp_f64_half() nounwind {52; CHECK-LABEL: @test_constant_fold_rcp_f64_half(53; CHECK-NEXT: ret double 2.000000e+0054;55 %val = call double @llvm.amdgcn.rcp.f64(double 0.5) nounwind readnone56 ret double %val57}58 59define float @test_constant_fold_rcp_f32_43() nounwind {60; CHECK-LABEL: @test_constant_fold_rcp_f32_43(61; CHECK-NEXT: ret float 0x3F97D05F4000000062;63 %val = call float @llvm.amdgcn.rcp.f32(float 4.300000e+01) nounwind readnone64 ret float %val65}66 67define double @test_constant_fold_rcp_f64_43() nounwind {68; CHECK-LABEL: @test_constant_fold_rcp_f64_43(69; CHECK-NEXT: ret double 0x3F97D05F417D05F470;71 %val = call double @llvm.amdgcn.rcp.f64(double 4.300000e+01) nounwind readnone72 ret double %val73}74 75define float @test_constant_fold_rcp_f32_43_strictfp() nounwind strictfp {76; CHECK-LABEL: @test_constant_fold_rcp_f32_43_strictfp(77; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.rcp.f32(float 4.300000e+01) #[[ATTR17:[0-9]+]]78; CHECK-NEXT: ret float [[VAL]]79;80 %val = call float @llvm.amdgcn.rcp.f32(float 4.300000e+01) strictfp nounwind readnone81 ret float %val82}83 84; --------------------------------------------------------------------85; llvm.amdgcn.sqrt86; --------------------------------------------------------------------87 88declare half @llvm.amdgcn.sqrt.f16(half) nounwind readnone89declare float @llvm.amdgcn.sqrt.f32(float) nounwind readnone90declare double @llvm.amdgcn.sqrt.f64(double) nounwind readnone91 92define half @test_constant_fold_sqrt_f16_poison() nounwind {93; CHECK-LABEL: @test_constant_fold_sqrt_f16_poison(94; CHECK-NEXT: ret half poison95;96 %val = call half @llvm.amdgcn.sqrt.f16(half poison) nounwind readnone97 ret half %val98}99 100define half @test_constant_fold_sqrt_f16_undef() nounwind {101; CHECK-LABEL: @test_constant_fold_sqrt_f16_undef(102; CHECK-NEXT: ret half 0xH7E00103;104 %val = call half @llvm.amdgcn.sqrt.f16(half undef) nounwind readnone105 ret half %val106}107 108define float @test_constant_fold_sqrt_f32_poison() nounwind {109; CHECK-LABEL: @test_constant_fold_sqrt_f32_poison(110; CHECK-NEXT: ret float poison111;112 %val = call float @llvm.amdgcn.sqrt.f32(float poison) nounwind readnone113 ret float %val114}115 116define float @test_constant_fold_sqrt_f32_undef() nounwind {117; CHECK-LABEL: @test_constant_fold_sqrt_f32_undef(118; CHECK-NEXT: ret float 0x7FF8000000000000119;120 %val = call float @llvm.amdgcn.sqrt.f32(float undef) nounwind readnone121 ret float %val122}123 124define double @test_constant_fold_sqrt_f64_undef() nounwind {125; CHECK-LABEL: @test_constant_fold_sqrt_f64_undef(126; CHECK-NEXT: ret double 0x7FF8000000000000127;128 %val = call double @llvm.amdgcn.sqrt.f64(double undef) nounwind readnone129 ret double %val130}131 132define half @test_constant_fold_sqrt_f16_0() nounwind {133; CHECK-LABEL: @test_constant_fold_sqrt_f16_0(134; CHECK-NEXT: ret half 0xH0000135;136 %val = call half @llvm.amdgcn.sqrt.f16(half 0.0) nounwind readnone137 ret half %val138}139 140define float @test_constant_fold_sqrt_f32_0() nounwind {141; CHECK-LABEL: @test_constant_fold_sqrt_f32_0(142; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.sqrt.f32(float 0.000000e+00) #[[ATTR18:[0-9]+]]143; CHECK-NEXT: ret float [[VAL]]144;145 %val = call float @llvm.amdgcn.sqrt.f32(float 0.0) nounwind readnone146 ret float %val147}148 149define double @test_constant_fold_sqrt_f64_0() nounwind {150; CHECK-LABEL: @test_constant_fold_sqrt_f64_0(151; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.sqrt.f64(double 0.000000e+00) #[[ATTR18]]152; CHECK-NEXT: ret double [[VAL]]153;154 %val = call double @llvm.amdgcn.sqrt.f64(double 0.0) nounwind readnone155 ret double %val156}157 158define half @test_constant_fold_sqrt_f16_neg0() nounwind {159; CHECK-LABEL: @test_constant_fold_sqrt_f16_neg0(160; CHECK-NEXT: ret half 0xH8000161;162 %val = call half @llvm.amdgcn.sqrt.f16(half -0.0) nounwind readnone163 ret half %val164}165 166define float @test_constant_fold_sqrt_f32_neg0() nounwind {167; CHECK-LABEL: @test_constant_fold_sqrt_f32_neg0(168; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.sqrt.f32(float -0.000000e+00) #[[ATTR18]]169; CHECK-NEXT: ret float [[VAL]]170;171 %val = call float @llvm.amdgcn.sqrt.f32(float -0.0) nounwind readnone172 ret float %val173}174 175define double @test_constant_fold_sqrt_f64_neg0() nounwind {176; CHECK-LABEL: @test_constant_fold_sqrt_f64_neg0(177; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.sqrt.f64(double -0.000000e+00) #[[ATTR18]]178; CHECK-NEXT: ret double [[VAL]]179;180 %val = call double @llvm.amdgcn.sqrt.f64(double -0.0) nounwind readnone181 ret double %val182}183 184define double @test_constant_fold_sqrt_snan_f64() nounwind {185; CHECK-LABEL: @test_constant_fold_sqrt_snan_f64(186; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.sqrt.f64(double 0x7FF0000000000001)187; CHECK-NEXT: ret double [[VAL]]188;189 %val = call double @llvm.amdgcn.sqrt.f64(double 0x7FF0000000000001)190 ret double %val191}192 193define double @test_constant_fold_sqrt_qnan_f64() nounwind {194; CHECK-LABEL: @test_constant_fold_sqrt_qnan_f64(195; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.sqrt.f64(double 0x7FF8000000000000)196; CHECK-NEXT: ret double [[VAL]]197;198 %val = call double @llvm.amdgcn.sqrt.f64(double 0x7FF8000000000000)199 ret double %val200}201 202define double @test_constant_fold_sqrt_neg1() nounwind {203; CHECK-LABEL: @test_constant_fold_sqrt_neg1(204; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.sqrt.f64(double -1.000000e+00)205; CHECK-NEXT: ret double [[VAL]]206;207 %val = call double @llvm.amdgcn.sqrt.f64(double -1.0)208 ret double %val209}210 211define half @test_amdgcn_sqrt_f16(half %arg) {212; CHECK-LABEL: @test_amdgcn_sqrt_f16(213; CHECK-NEXT: [[VAL:%.*]] = call half @llvm.sqrt.f16(half [[ARG:%.*]])214; CHECK-NEXT: ret half [[VAL]]215;216 %val = call half @llvm.amdgcn.sqrt.f16(half %arg)217 ret half %val218}219 220define half @test_amdgcn_sqrt_f16_flags(half %arg) {221; CHECK-LABEL: @test_amdgcn_sqrt_f16_flags(222; CHECK-NEXT: [[VAL:%.*]] = call nnan half @llvm.sqrt.f16(half [[ARG:%.*]])223; CHECK-NEXT: ret half [[VAL]]224;225 %val = call nnan half @llvm.amdgcn.sqrt.f16(half %arg)226 ret half %val227}228 229define float @test_amdgcn_sqrt_f32(float %arg) {230; CHECK-LABEL: @test_amdgcn_sqrt_f32(231; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.sqrt.f32(float [[ARG:%.*]])232; CHECK-NEXT: ret float [[VAL]]233;234 %val = call float @llvm.amdgcn.sqrt.f32(float %arg)235 ret float %val236}237 238define double @test_amdgcn_sqrt_f64(double %arg) {239; CHECK-LABEL: @test_amdgcn_sqrt_f64(240; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.sqrt.f64(double [[ARG:%.*]])241; CHECK-NEXT: ret double [[VAL]]242;243 %val = call double @llvm.amdgcn.sqrt.f64(double %arg)244 ret double %val245}246 247; --------------------------------------------------------------------248; llvm.amdgcn.rsq249; --------------------------------------------------------------------250 251declare float @llvm.amdgcn.rsq.f32(float) nounwind readnone252 253define float @test_constant_fold_rsq_f32_poison() nounwind {254; CHECK-LABEL: @test_constant_fold_rsq_f32_poison(255; CHECK-NEXT: ret float poison256;257 %val = call float @llvm.amdgcn.rsq.f32(float poison) nounwind readnone258 ret float %val259}260 261define float @test_constant_fold_rsq_f32_undef() nounwind {262; CHECK-LABEL: @test_constant_fold_rsq_f32_undef(263; CHECK-NEXT: ret float 0x7FF8000000000000264;265 %val = call float @llvm.amdgcn.rsq.f32(float undef) nounwind readnone266 ret float %val267}268 269; --------------------------------------------------------------------270; llvm.amdgcn.frexp.mant271; --------------------------------------------------------------------272 273declare float @llvm.amdgcn.frexp.mant.f32(float) nounwind readnone274declare double @llvm.amdgcn.frexp.mant.f64(double) nounwind readnone275 276 277define float @test_constant_fold_frexp_mant_f32_poison() nounwind {278; CHECK-LABEL: @test_constant_fold_frexp_mant_f32_poison(279; CHECK-NEXT: ret float poison280;281 %val = call float @llvm.amdgcn.frexp.mant.f32(float poison)282 ret float %val283}284 285define float @test_constant_fold_frexp_mant_f32_undef() nounwind {286; CHECK-LABEL: @test_constant_fold_frexp_mant_f32_undef(287; CHECK-NEXT: ret float undef288;289 %val = call float @llvm.amdgcn.frexp.mant.f32(float undef)290 ret float %val291}292 293define double @test_constant_fold_frexp_mant_f64_undef() nounwind {294; CHECK-LABEL: @test_constant_fold_frexp_mant_f64_undef(295; CHECK-NEXT: ret double undef296;297 %val = call double @llvm.amdgcn.frexp.mant.f64(double undef)298 ret double %val299}300 301define float @test_constant_fold_frexp_mant_f32_0() nounwind {302; CHECK-LABEL: @test_constant_fold_frexp_mant_f32_0(303; CHECK-NEXT: ret float 0.000000e+00304;305 %val = call float @llvm.amdgcn.frexp.mant.f32(float 0.0)306 ret float %val307}308 309define double @test_constant_fold_frexp_mant_f64_0() nounwind {310; CHECK-LABEL: @test_constant_fold_frexp_mant_f64_0(311; CHECK-NEXT: ret double 0.000000e+00312;313 %val = call double @llvm.amdgcn.frexp.mant.f64(double 0.0)314 ret double %val315}316 317define float @test_constant_fold_frexp_mant_f32_n0() nounwind {318; CHECK-LABEL: @test_constant_fold_frexp_mant_f32_n0(319; CHECK-NEXT: ret float -0.000000e+00320;321 %val = call float @llvm.amdgcn.frexp.mant.f32(float -0.0)322 ret float %val323}324 325define double @test_constant_fold_frexp_mant_f64_n0() nounwind {326; CHECK-LABEL: @test_constant_fold_frexp_mant_f64_n0(327; CHECK-NEXT: ret double -0.000000e+00328;329 %val = call double @llvm.amdgcn.frexp.mant.f64(double -0.0)330 ret double %val331}332 333define float @test_constant_fold_frexp_mant_f32_1() nounwind {334; CHECK-LABEL: @test_constant_fold_frexp_mant_f32_1(335; CHECK-NEXT: ret float 5.000000e-01336;337 %val = call float @llvm.amdgcn.frexp.mant.f32(float 1.0)338 ret float %val339}340 341define double @test_constant_fold_frexp_mant_f64_1() nounwind {342; CHECK-LABEL: @test_constant_fold_frexp_mant_f64_1(343; CHECK-NEXT: ret double 5.000000e-01344;345 %val = call double @llvm.amdgcn.frexp.mant.f64(double 1.0)346 ret double %val347}348 349define float @test_constant_fold_frexp_mant_f32_n1() nounwind {350; CHECK-LABEL: @test_constant_fold_frexp_mant_f32_n1(351; CHECK-NEXT: ret float -5.000000e-01352;353 %val = call float @llvm.amdgcn.frexp.mant.f32(float -1.0)354 ret float %val355}356 357define double @test_constant_fold_frexp_mant_f64_n1() nounwind {358; CHECK-LABEL: @test_constant_fold_frexp_mant_f64_n1(359; CHECK-NEXT: ret double -5.000000e-01360;361 %val = call double @llvm.amdgcn.frexp.mant.f64(double -1.0)362 ret double %val363}364 365define float @test_constant_fold_frexp_mant_f32_nan() nounwind {366; CHECK-LABEL: @test_constant_fold_frexp_mant_f32_nan(367; CHECK-NEXT: ret float 0x7FF8000000000000368;369 %val = call float @llvm.amdgcn.frexp.mant.f32(float 0x7FF8000000000000)370 ret float %val371}372 373define double @test_constant_fold_frexp_mant_f64_nan() nounwind {374; CHECK-LABEL: @test_constant_fold_frexp_mant_f64_nan(375; CHECK-NEXT: ret double 0x7FF8000000000000376;377 %val = call double @llvm.amdgcn.frexp.mant.f64(double 0x7FF8000000000000)378 ret double %val379}380 381define float @test_constant_fold_frexp_mant_f32_inf() nounwind {382; CHECK-LABEL: @test_constant_fold_frexp_mant_f32_inf(383; CHECK-NEXT: ret float 0x7FF0000000000000384;385 %val = call float @llvm.amdgcn.frexp.mant.f32(float 0x7FF0000000000000)386 ret float %val387}388 389define double @test_constant_fold_frexp_mant_f64_inf() nounwind {390; CHECK-LABEL: @test_constant_fold_frexp_mant_f64_inf(391; CHECK-NEXT: ret double 0x7FF0000000000000392;393 %val = call double @llvm.amdgcn.frexp.mant.f64(double 0x7FF0000000000000)394 ret double %val395}396 397define float @test_constant_fold_frexp_mant_f32_ninf() nounwind {398; CHECK-LABEL: @test_constant_fold_frexp_mant_f32_ninf(399; CHECK-NEXT: ret float 0xFFF0000000000000400;401 %val = call float @llvm.amdgcn.frexp.mant.f32(float 0xFFF0000000000000)402 ret float %val403}404 405define double @test_constant_fold_frexp_mant_f64_ninf() nounwind {406; CHECK-LABEL: @test_constant_fold_frexp_mant_f64_ninf(407; CHECK-NEXT: ret double 0xFFF0000000000000408;409 %val = call double @llvm.amdgcn.frexp.mant.f64(double 0xFFF0000000000000)410 ret double %val411}412 413define float @test_constant_fold_frexp_mant_f32_max_num() nounwind {414; CHECK-LABEL: @test_constant_fold_frexp_mant_f32_max_num(415; CHECK-NEXT: ret float 0x3FEFFFFFE0000000416;417 %val = call float @llvm.amdgcn.frexp.mant.f32(float 0x47EFFFFFE0000000)418 ret float %val419}420 421define double @test_constant_fold_frexp_mant_f64_max_num() nounwind {422; CHECK-LABEL: @test_constant_fold_frexp_mant_f64_max_num(423; CHECK-NEXT: ret double 0x3FEFFFFFFFFFFFFF424;425 %val = call double @llvm.amdgcn.frexp.mant.f64(double 0x7FEFFFFFFFFFFFFF)426 ret double %val427}428 429define float @test_constant_fold_frexp_mant_f32_min_num() nounwind {430; CHECK-LABEL: @test_constant_fold_frexp_mant_f32_min_num(431; CHECK-NEXT: ret float 5.000000e-01432;433 %val = call float @llvm.amdgcn.frexp.mant.f32(float 0x36A0000000000000)434 ret float %val435}436 437define double @test_constant_fold_frexp_mant_f64_min_num() nounwind {438; CHECK-LABEL: @test_constant_fold_frexp_mant_f64_min_num(439; CHECK-NEXT: ret double 5.000000e-01440;441 %val = call double @llvm.amdgcn.frexp.mant.f64(double 4.940656e-324)442 ret double %val443}444 445 446; --------------------------------------------------------------------447; llvm.amdgcn.frexp.exp448; --------------------------------------------------------------------449 450declare i32 @llvm.amdgcn.frexp.exp.f32(float) nounwind readnone451declare i32 @llvm.amdgcn.frexp.exp.f64(double) nounwind readnone452 453define i32 @test_constant_fold_frexp_exp_f32_poison() nounwind {454; CHECK-LABEL: @test_constant_fold_frexp_exp_f32_poison(455; CHECK-NEXT: ret i32 poison456;457 %val = call i32 @llvm.amdgcn.frexp.exp.f32(float poison)458 ret i32 %val459}460 461define i32 @test_constant_fold_frexp_exp_f32_undef() nounwind {462; CHECK-LABEL: @test_constant_fold_frexp_exp_f32_undef(463; CHECK-NEXT: ret i32 undef464;465 %val = call i32 @llvm.amdgcn.frexp.exp.f32(float undef)466 ret i32 %val467}468 469define i32 @test_constant_fold_frexp_exp_f64_undef() nounwind {470; CHECK-LABEL: @test_constant_fold_frexp_exp_f64_undef(471; CHECK-NEXT: ret i32 undef472;473 %val = call i32 @llvm.amdgcn.frexp.exp.f64(double undef)474 ret i32 %val475}476 477define i32 @test_constant_fold_frexp_exp_f32_0() nounwind {478; CHECK-LABEL: @test_constant_fold_frexp_exp_f32_0(479; CHECK-NEXT: ret i32 0480;481 %val = call i32 @llvm.amdgcn.frexp.exp.f32(float 0.0)482 ret i32 %val483}484 485define i32 @test_constant_fold_frexp_exp_f64_0() nounwind {486; CHECK-LABEL: @test_constant_fold_frexp_exp_f64_0(487; CHECK-NEXT: ret i32 0488;489 %val = call i32 @llvm.amdgcn.frexp.exp.f64(double 0.0)490 ret i32 %val491}492 493define i32 @test_constant_fold_frexp_exp_f32_n0() nounwind {494; CHECK-LABEL: @test_constant_fold_frexp_exp_f32_n0(495; CHECK-NEXT: ret i32 0496;497 %val = call i32 @llvm.amdgcn.frexp.exp.f32(float -0.0)498 ret i32 %val499}500 501define i32 @test_constant_fold_frexp_exp_f64_n0() nounwind {502; CHECK-LABEL: @test_constant_fold_frexp_exp_f64_n0(503; CHECK-NEXT: ret i32 0504;505 %val = call i32 @llvm.amdgcn.frexp.exp.f64(double -0.0)506 ret i32 %val507}508 509define i32 @test_constant_fold_frexp_exp_f32_1024() nounwind {510; CHECK-LABEL: @test_constant_fold_frexp_exp_f32_1024(511; CHECK-NEXT: ret i32 11512;513 %val = call i32 @llvm.amdgcn.frexp.exp.f32(float 1024.0)514 ret i32 %val515}516 517define i32 @test_constant_fold_frexp_exp_f64_1024() nounwind {518; CHECK-LABEL: @test_constant_fold_frexp_exp_f64_1024(519; CHECK-NEXT: ret i32 11520;521 %val = call i32 @llvm.amdgcn.frexp.exp.f64(double 1024.0)522 ret i32 %val523}524 525define i32 @test_constant_fold_frexp_exp_f32_n1024() nounwind {526; CHECK-LABEL: @test_constant_fold_frexp_exp_f32_n1024(527; CHECK-NEXT: ret i32 11528;529 %val = call i32 @llvm.amdgcn.frexp.exp.f32(float -1024.0)530 ret i32 %val531}532 533define i32 @test_constant_fold_frexp_exp_f64_n1024() nounwind {534; CHECK-LABEL: @test_constant_fold_frexp_exp_f64_n1024(535; CHECK-NEXT: ret i32 11536;537 %val = call i32 @llvm.amdgcn.frexp.exp.f64(double -1024.0)538 ret i32 %val539}540 541define i32 @test_constant_fold_frexp_exp_f32_1_1024() nounwind {542; CHECK-LABEL: @test_constant_fold_frexp_exp_f32_1_1024(543; CHECK-NEXT: ret i32 -9544;545 %val = call i32 @llvm.amdgcn.frexp.exp.f32(float 0.0009765625)546 ret i32 %val547}548 549define i32 @test_constant_fold_frexp_exp_f64_1_1024() nounwind {550; CHECK-LABEL: @test_constant_fold_frexp_exp_f64_1_1024(551; CHECK-NEXT: ret i32 -9552;553 %val = call i32 @llvm.amdgcn.frexp.exp.f64(double 0.0009765625)554 ret i32 %val555}556 557define i32 @test_constant_fold_frexp_exp_f32_nan() nounwind {558; CHECK-LABEL: @test_constant_fold_frexp_exp_f32_nan(559; CHECK-NEXT: ret i32 0560;561 %val = call i32 @llvm.amdgcn.frexp.exp.f32(float 0x7FF8000000000000)562 ret i32 %val563}564 565define i32 @test_constant_fold_frexp_exp_f64_nan() nounwind {566; CHECK-LABEL: @test_constant_fold_frexp_exp_f64_nan(567; CHECK-NEXT: ret i32 0568;569 %val = call i32 @llvm.amdgcn.frexp.exp.f64(double 0x7FF8000000000000)570 ret i32 %val571}572 573define i32 @test_constant_fold_frexp_exp_f32_inf() nounwind {574; CHECK-LABEL: @test_constant_fold_frexp_exp_f32_inf(575; CHECK-NEXT: ret i32 0576;577 %val = call i32 @llvm.amdgcn.frexp.exp.f32(float 0x7FF0000000000000)578 ret i32 %val579}580 581define i32 @test_constant_fold_frexp_exp_f64_inf() nounwind {582; CHECK-LABEL: @test_constant_fold_frexp_exp_f64_inf(583; CHECK-NEXT: ret i32 0584;585 %val = call i32 @llvm.amdgcn.frexp.exp.f64(double 0x7FF0000000000000)586 ret i32 %val587}588 589define i32 @test_constant_fold_frexp_exp_f32_ninf() nounwind {590; CHECK-LABEL: @test_constant_fold_frexp_exp_f32_ninf(591; CHECK-NEXT: ret i32 0592;593 %val = call i32 @llvm.amdgcn.frexp.exp.f32(float 0xFFF0000000000000)594 ret i32 %val595}596 597define i32 @test_constant_fold_frexp_exp_f64_ninf() nounwind {598; CHECK-LABEL: @test_constant_fold_frexp_exp_f64_ninf(599; CHECK-NEXT: ret i32 0600;601 %val = call i32 @llvm.amdgcn.frexp.exp.f64(double 0xFFF0000000000000)602 ret i32 %val603}604 605define i32 @test_constant_fold_frexp_exp_f32_max_num() nounwind {606; CHECK-LABEL: @test_constant_fold_frexp_exp_f32_max_num(607; CHECK-NEXT: ret i32 128608;609 %val = call i32 @llvm.amdgcn.frexp.exp.f32(float 0x47EFFFFFE0000000)610 ret i32 %val611}612 613define i32 @test_constant_fold_frexp_exp_f64_max_num() nounwind {614; CHECK-LABEL: @test_constant_fold_frexp_exp_f64_max_num(615; CHECK-NEXT: ret i32 1024616;617 %val = call i32 @llvm.amdgcn.frexp.exp.f64(double 0x7FEFFFFFFFFFFFFF)618 ret i32 %val619}620 621define i32 @test_constant_fold_frexp_exp_f32_min_num() nounwind {622; CHECK-LABEL: @test_constant_fold_frexp_exp_f32_min_num(623; CHECK-NEXT: ret i32 -148624;625 %val = call i32 @llvm.amdgcn.frexp.exp.f32(float 0x36A0000000000000)626 ret i32 %val627}628 629define i32 @test_constant_fold_frexp_exp_f64_min_num() nounwind {630; CHECK-LABEL: @test_constant_fold_frexp_exp_f64_min_num(631; CHECK-NEXT: ret i32 -1073632;633 %val = call i32 @llvm.amdgcn.frexp.exp.f64(double 4.940656e-324)634 ret i32 %val635}636 637; --------------------------------------------------------------------638; llvm.amdgcn.class639; --------------------------------------------------------------------640 641declare i1 @llvm.amdgcn.class.f32(float, i32) nounwind readnone642declare i1 @llvm.amdgcn.class.f64(double, i32) nounwind readnone643 644define i1 @test_class_undef_mask_f32(float %x) nounwind {645; CHECK-LABEL: @test_class_undef_mask_f32(646; CHECK-NEXT: ret i1 false647;648 %val = call i1 @llvm.amdgcn.class.f32(float %x, i32 undef)649 ret i1 %val650}651 652define i1 @test_class_poison_poison_f32(float %x) nounwind {653; CHECK-LABEL: @test_class_poison_poison_f32(654; CHECK-NEXT: ret i1 poison655;656 %val = call i1 @llvm.amdgcn.class.f32(float poison, i32 poison)657 ret i1 %val658}659define i1 @test_class_val_poison_f32(float %arg) nounwind {660; CHECK-LABEL: @test_class_val_poison_f32(661; CHECK-NEXT: ret i1 poison662;663 %val = call i1 @llvm.amdgcn.class.f32(float %arg, i32 poison)664 ret i1 %val665}666 667define i1 @test_class_poison_val_f32(i32 %arg) nounwind {668; CHECK-LABEL: @test_class_poison_val_f32(669; CHECK-NEXT: ret i1 poison670;671 %val = call i1 @llvm.amdgcn.class.f32(float poison, i32 %arg)672 ret i1 %val673}674 675define i1 @test_class_over_max_mask_f32(float %x) nounwind {676; CHECK-LABEL: @test_class_over_max_mask_f32(677; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 1)678; CHECK-NEXT: ret i1 [[VAL]]679;680 %val = call i1 @llvm.amdgcn.class.f32(float %x, i32 1025)681 ret i1 %val682}683 684define i1 @test_class_no_mask_f32(float %x) nounwind {685; CHECK-LABEL: @test_class_no_mask_f32(686; CHECK-NEXT: ret i1 false687;688 %val = call i1 @llvm.amdgcn.class.f32(float %x, i32 0)689 ret i1 %val690}691 692define i1 @test_class_full_mask_f32(float %x) nounwind {693; CHECK-LABEL: @test_class_full_mask_f32(694; CHECK-NEXT: ret i1 true695;696 %val = call i1 @llvm.amdgcn.class.f32(float %x, i32 1023)697 ret i1 %val698}699 700define i1 @test_class_undef_no_mask_f32() nounwind {701; CHECK-LABEL: @test_class_undef_no_mask_f32(702; CHECK-NEXT: ret i1 false703;704 %val = call i1 @llvm.amdgcn.class.f32(float undef, i32 0)705 ret i1 %val706}707 708define i1 @test_class_undef_full_mask_f32() nounwind {709; CHECK-LABEL: @test_class_undef_full_mask_f32(710; CHECK-NEXT: ret i1 true711;712 %val = call i1 @llvm.amdgcn.class.f32(float undef, i32 1023)713 ret i1 %val714}715 716define i1 @test_class_undef_val_f32() nounwind {717; CHECK-LABEL: @test_class_undef_val_f32(718; CHECK-NEXT: ret i1 undef719;720 %val = call i1 @llvm.amdgcn.class.f32(float undef, i32 4)721 ret i1 %val722}723 724define i1 @test_class_undef_val_f32_var(i32 %arg) nounwind {725; CHECK-LABEL: @test_class_undef_val_f32_var(726; CHECK-NEXT: [[VAL:%.*]] = icmp ne i32 [[ARG:%.*]], 0727; CHECK-NEXT: ret i1 [[VAL]]728;729 %val = call i1 @llvm.amdgcn.class.f32(float undef, i32 %arg)730 ret i1 %val731}732 733define i1 @test_class_val_undef_f32(float %arg) nounwind {734; CHECK-LABEL: @test_class_val_undef_f32(735; CHECK-NEXT: ret i1 false736;737 %val = call i1 @llvm.amdgcn.class.f32(float %arg, i32 undef)738 ret i1 %val739}740 741define i1 @test_class_undef_undef_f32() nounwind {742; CHECK-LABEL: @test_class_undef_undef_f32(743; CHECK-NEXT: ret i1 false744;745 %val = call i1 @llvm.amdgcn.class.f32(float undef, i32 undef)746 ret i1 %val747}748 749define i1 @test_class_var_mask_f32(float %x, i32 %mask) nounwind {750; CHECK-LABEL: @test_class_var_mask_f32(751; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.amdgcn.class.f32(float [[X:%.*]], i32 [[MASK:%.*]])752; CHECK-NEXT: ret i1 [[VAL]]753;754 %val = call i1 @llvm.amdgcn.class.f32(float %x, i32 %mask)755 ret i1 %val756}757 758define i1 @test_class_isnan_f32(float %x) nounwind {759; CHECK-LABEL: @test_class_isnan_f32(760; CHECK-NEXT: [[VAL:%.*]] = fcmp uno float [[X:%.*]], 0.000000e+00761; CHECK-NEXT: ret i1 [[VAL]]762;763 %val = call i1 @llvm.amdgcn.class.f32(float %x, i32 3)764 ret i1 %val765}766 767define i1 @test_class_isnan_f32_strict(float %x) nounwind strictfp {768; CHECK-LABEL: @test_class_isnan_f32_strict(769; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 3) #[[ATTR19:[0-9]+]]770; CHECK-NEXT: ret i1 [[VAL]]771;772 %val = call i1 @llvm.amdgcn.class.f32(float %x, i32 3) strictfp773 ret i1 %val774}775 776define i1 @test_class_is_p0_n0_f32(float %x) nounwind {777; CHECK-LABEL: @test_class_is_p0_n0_f32(778; CHECK-NEXT: [[VAL:%.*]] = fcmp oeq float [[X:%.*]], 0.000000e+00779; CHECK-NEXT: ret i1 [[VAL]]780;781 %val = call i1 @llvm.amdgcn.class.f32(float %x, i32 96)782 ret i1 %val783}784 785define i1 @test_class_is_p0_n0_f32_strict(float %x) nounwind strictfp {786; CHECK-LABEL: @test_class_is_p0_n0_f32_strict(787; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 96) #[[ATTR19]]788; CHECK-NEXT: ret i1 [[VAL]]789;790 %val = call i1 @llvm.amdgcn.class.f32(float %x, i32 96) strictfp791 ret i1 %val792}793 794define i1 @test_constant_class_snan_test_snan_f64() nounwind {795; CHECK-LABEL: @test_constant_class_snan_test_snan_f64(796; CHECK-NEXT: ret i1 true797;798 %val = call i1 @llvm.amdgcn.class.f64(double 0x7FF0000000000001, i32 1)799 ret i1 %val800}801 802define i1 @test_constant_class_qnan_test_qnan_f64() nounwind {803; CHECK-LABEL: @test_constant_class_qnan_test_qnan_f64(804; CHECK-NEXT: ret i1 true805;806 %val = call i1 @llvm.amdgcn.class.f64(double 0x7FF8000000000000, i32 2)807 ret i1 %val808}809 810define i1 @test_constant_class_qnan_test_snan_f64() nounwind {811; CHECK-LABEL: @test_constant_class_qnan_test_snan_f64(812; CHECK-NEXT: ret i1 false813;814 %val = call i1 @llvm.amdgcn.class.f64(double 0x7FF8000000000000, i32 1)815 ret i1 %val816}817 818define i1 @test_constant_class_ninf_test_ninf_f64() nounwind {819; CHECK-LABEL: @test_constant_class_ninf_test_ninf_f64(820; CHECK-NEXT: ret i1 true821;822 %val = call i1 @llvm.amdgcn.class.f64(double 0xFFF0000000000000, i32 4)823 ret i1 %val824}825 826define i1 @test_constant_class_pinf_test_ninf_f64() nounwind {827; CHECK-LABEL: @test_constant_class_pinf_test_ninf_f64(828; CHECK-NEXT: ret i1 false829;830 %val = call i1 @llvm.amdgcn.class.f64(double 0x7FF0000000000000, i32 4)831 ret i1 %val832}833 834define i1 @test_constant_class_qnan_test_ninf_f64() nounwind {835; CHECK-LABEL: @test_constant_class_qnan_test_ninf_f64(836; CHECK-NEXT: ret i1 false837;838 %val = call i1 @llvm.amdgcn.class.f64(double 0x7FF8000000000000, i32 4)839 ret i1 %val840}841 842define i1 @test_constant_class_snan_test_ninf_f64() nounwind {843; CHECK-LABEL: @test_constant_class_snan_test_ninf_f64(844; CHECK-NEXT: ret i1 false845;846 %val = call i1 @llvm.amdgcn.class.f64(double 0x7FF0000000000001, i32 4)847 ret i1 %val848}849 850define i1 @test_constant_class_nnormal_test_nnormal_f64() nounwind {851; CHECK-LABEL: @test_constant_class_nnormal_test_nnormal_f64(852; CHECK-NEXT: ret i1 true853;854 %val = call i1 @llvm.amdgcn.class.f64(double -1.0, i32 8)855 ret i1 %val856}857 858define i1 @test_constant_class_pnormal_test_nnormal_f64() nounwind {859; CHECK-LABEL: @test_constant_class_pnormal_test_nnormal_f64(860; CHECK-NEXT: ret i1 false861;862 %val = call i1 @llvm.amdgcn.class.f64(double 1.0, i32 8)863 ret i1 %val864}865 866define i1 @test_constant_class_nsubnormal_test_nsubnormal_f64() nounwind {867; CHECK-LABEL: @test_constant_class_nsubnormal_test_nsubnormal_f64(868; CHECK-NEXT: ret i1 true869;870 %val = call i1 @llvm.amdgcn.class.f64(double 0x800fffffffffffff, i32 16)871 ret i1 %val872}873 874define i1 @test_constant_class_psubnormal_test_nsubnormal_f64() nounwind {875; CHECK-LABEL: @test_constant_class_psubnormal_test_nsubnormal_f64(876; CHECK-NEXT: ret i1 false877;878 %val = call i1 @llvm.amdgcn.class.f64(double 0x000fffffffffffff, i32 16)879 ret i1 %val880}881 882define i1 @test_constant_class_nzero_test_nzero_f64() nounwind {883; CHECK-LABEL: @test_constant_class_nzero_test_nzero_f64(884; CHECK-NEXT: ret i1 true885;886 %val = call i1 @llvm.amdgcn.class.f64(double -0.0, i32 32)887 ret i1 %val888}889 890define i1 @test_constant_class_pzero_test_nzero_f64() nounwind {891; CHECK-LABEL: @test_constant_class_pzero_test_nzero_f64(892; CHECK-NEXT: ret i1 false893;894 %val = call i1 @llvm.amdgcn.class.f64(double 0.0, i32 32)895 ret i1 %val896}897 898define i1 @test_constant_class_pzero_test_pzero_f64() nounwind {899; CHECK-LABEL: @test_constant_class_pzero_test_pzero_f64(900; CHECK-NEXT: ret i1 true901;902 %val = call i1 @llvm.amdgcn.class.f64(double 0.0, i32 64)903 ret i1 %val904}905 906define i1 @test_constant_class_nzero_test_pzero_f64() nounwind {907; CHECK-LABEL: @test_constant_class_nzero_test_pzero_f64(908; CHECK-NEXT: ret i1 false909;910 %val = call i1 @llvm.amdgcn.class.f64(double -0.0, i32 64)911 ret i1 %val912}913 914define i1 @test_constant_class_psubnormal_test_psubnormal_f64() nounwind {915; CHECK-LABEL: @test_constant_class_psubnormal_test_psubnormal_f64(916; CHECK-NEXT: ret i1 true917;918 %val = call i1 @llvm.amdgcn.class.f64(double 0x000fffffffffffff, i32 128)919 ret i1 %val920}921 922define i1 @test_constant_class_nsubnormal_test_psubnormal_f64() nounwind {923; CHECK-LABEL: @test_constant_class_nsubnormal_test_psubnormal_f64(924; CHECK-NEXT: ret i1 false925;926 %val = call i1 @llvm.amdgcn.class.f64(double 0x800fffffffffffff, i32 128)927 ret i1 %val928}929 930define i1 @test_constant_class_pnormal_test_pnormal_f64() nounwind {931; CHECK-LABEL: @test_constant_class_pnormal_test_pnormal_f64(932; CHECK-NEXT: ret i1 true933;934 %val = call i1 @llvm.amdgcn.class.f64(double 1.0, i32 256)935 ret i1 %val936}937 938define i1 @test_constant_class_nnormal_test_pnormal_f64() nounwind {939; CHECK-LABEL: @test_constant_class_nnormal_test_pnormal_f64(940; CHECK-NEXT: ret i1 false941;942 %val = call i1 @llvm.amdgcn.class.f64(double -1.0, i32 256)943 ret i1 %val944}945 946define i1 @test_constant_class_pinf_test_pinf_f64() nounwind {947; CHECK-LABEL: @test_constant_class_pinf_test_pinf_f64(948; CHECK-NEXT: ret i1 true949;950 %val = call i1 @llvm.amdgcn.class.f64(double 0x7FF0000000000000, i32 512)951 ret i1 %val952}953 954define i1 @test_constant_class_ninf_test_pinf_f64() nounwind {955; CHECK-LABEL: @test_constant_class_ninf_test_pinf_f64(956; CHECK-NEXT: ret i1 false957;958 %val = call i1 @llvm.amdgcn.class.f64(double 0xFFF0000000000000, i32 512)959 ret i1 %val960}961 962define i1 @test_constant_class_qnan_test_pinf_f64() nounwind {963; CHECK-LABEL: @test_constant_class_qnan_test_pinf_f64(964; CHECK-NEXT: ret i1 false965;966 %val = call i1 @llvm.amdgcn.class.f64(double 0x7FF8000000000000, i32 512)967 ret i1 %val968}969 970define i1 @test_constant_class_snan_test_pinf_f64() nounwind {971; CHECK-LABEL: @test_constant_class_snan_test_pinf_f64(972; CHECK-NEXT: ret i1 false973;974 %val = call i1 @llvm.amdgcn.class.f64(double 0x7FF0000000000001, i32 512)975 ret i1 %val976}977 978define i1 @test_class_is_snan_nnan_src(float %x) {979; CHECK-LABEL: @test_class_is_snan_nnan_src(980; CHECK-NEXT: ret i1 false981;982 %nnan = fadd nnan float %x, 1.0983 %class = call i1 @llvm.amdgcn.class.f32(float %nnan, i32 1)984 ret i1 %class985}986 987define i1 @test_class_is_qnan_nnan_src(float %x) {988; CHECK-LABEL: @test_class_is_qnan_nnan_src(989; CHECK-NEXT: ret i1 false990;991 %nnan = fadd nnan float %x, 1.0992 %class = call i1 @llvm.amdgcn.class.f32(float %nnan, i32 2)993 ret i1 %class994}995 996define i1 @test_class_is_nan_nnan_src(float %x) {997; CHECK-LABEL: @test_class_is_nan_nnan_src(998; CHECK-NEXT: ret i1 false999;1000 %nnan = fadd nnan float %x, 1.01001 %class = call i1 @llvm.amdgcn.class.f32(float %nnan, i32 3)1002 ret i1 %class1003}1004 1005define i1 @test_class_is_nan_other_nnan_src(float %x) {1006; CHECK-LABEL: @test_class_is_nan_other_nnan_src(1007; CHECK-NEXT: [[NNAN:%.*]] = fadd nnan float [[X:%.*]], 1.000000e+001008; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NNAN]], i32 264)1009; CHECK-NEXT: ret i1 [[CLASS]]1010;1011 %nnan = fadd nnan float %x, 1.01012 %class = call i1 @llvm.amdgcn.class.f32(float %nnan, i32 267)1013 ret i1 %class1014}1015 1016; --------------------------------------------------------------------1017; llvm.amdgcn.cos1018; --------------------------------------------------------------------1019declare float @llvm.amdgcn.cos.f32(float) nounwind readnone1020declare float @llvm.fabs.f32(float) nounwind readnone1021 1022define float @cos_fneg_f32(float %x) {1023; CHECK-LABEL: @cos_fneg_f32(1024; CHECK-NEXT: [[COS:%.*]] = call float @llvm.amdgcn.cos.f32(float [[X:%.*]])1025; CHECK-NEXT: ret float [[COS]]1026;1027 %x.fneg = fsub float -0.0, %x1028 %cos = call float @llvm.amdgcn.cos.f32(float %x.fneg)1029 ret float %cos1030}1031 1032define float @cos_unary_fneg_f32(float %x) {1033; CHECK-LABEL: @cos_unary_fneg_f32(1034; CHECK-NEXT: [[COS:%.*]] = call float @llvm.amdgcn.cos.f32(float [[X:%.*]])1035; CHECK-NEXT: ret float [[COS]]1036;1037 %x.fneg = fneg float %x1038 %cos = call float @llvm.amdgcn.cos.f32(float %x.fneg)1039 ret float %cos1040}1041 1042define float @cos_fabs_f32(float %x) {1043; CHECK-LABEL: @cos_fabs_f32(1044; CHECK-NEXT: [[COS:%.*]] = call float @llvm.amdgcn.cos.f32(float [[X:%.*]])1045; CHECK-NEXT: ret float [[COS]]1046;1047 %x.fabs = call float @llvm.fabs.f32(float %x)1048 %cos = call float @llvm.amdgcn.cos.f32(float %x.fabs)1049 ret float %cos1050}1051 1052define float @cos_fabs_fneg_f32(float %x) {1053; CHECK-LABEL: @cos_fabs_fneg_f32(1054; CHECK-NEXT: [[COS:%.*]] = call float @llvm.amdgcn.cos.f32(float [[X:%.*]])1055; CHECK-NEXT: ret float [[COS]]1056;1057 %x.fabs = call float @llvm.fabs.f32(float %x)1058 %x.fabs.fneg = fsub float -0.0, %x.fabs1059 %cos = call float @llvm.amdgcn.cos.f32(float %x.fabs.fneg)1060 ret float %cos1061}1062 1063define float @cos_fabs_unary_fneg_f32(float %x) {1064; CHECK-LABEL: @cos_fabs_unary_fneg_f32(1065; CHECK-NEXT: [[COS:%.*]] = call float @llvm.amdgcn.cos.f32(float [[X:%.*]])1066; CHECK-NEXT: ret float [[COS]]1067;1068 %x.fabs = call float @llvm.fabs.f32(float %x)1069 %x.fabs.fneg = fneg float %x.fabs1070 %cos = call float @llvm.amdgcn.cos.f32(float %x.fabs.fneg)1071 ret float %cos1072}1073 1074 1075; --------------------------------------------------------------------1076; llvm.amdgcn.sin1077; --------------------------------------------------------------------1078declare float @llvm.amdgcn.sin.f32(float) nounwind readnone1079 1080define float @sin_fneg_f32(float %x) {1081; CHECK-LABEL: @sin_fneg_f32(1082; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.amdgcn.sin.f32(float [[X:%.*]])1083; CHECK-NEXT: [[SIN:%.*]] = fneg float [[TMP1]]1084; CHECK-NEXT: ret float [[SIN]]1085;1086 %x.fneg = fneg float %x1087 %sin = call float @llvm.amdgcn.sin.f32(float %x.fneg)1088 ret float %sin1089}1090 1091define float @sin_fabs_f32(float %x) {1092; CHECK-LABEL: @sin_fabs_f32(1093; CHECK-NEXT: [[X_FABS:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])1094; CHECK-NEXT: [[SIN:%.*]] = call float @llvm.amdgcn.sin.f32(float [[X_FABS]])1095; CHECK-NEXT: ret float [[SIN]]1096;1097 %x.fabs = call float @llvm.fabs.f32(float %x)1098 %sin = call float @llvm.amdgcn.sin.f32(float %x.fabs)1099 ret float %sin1100}1101 1102define float @sin_fabs_fneg_f32(float %x) {1103; CHECK-LABEL: @sin_fabs_fneg_f32(1104; CHECK-NEXT: [[X_FABS:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]])1105; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.amdgcn.sin.f32(float [[X_FABS]])1106; CHECK-NEXT: [[SIN:%.*]] = fneg float [[TMP1]]1107; CHECK-NEXT: ret float [[SIN]]1108;1109 %x.fabs = call float @llvm.fabs.f32(float %x)1110 %x.fabs.fneg = fneg float %x.fabs1111 %sin = call float @llvm.amdgcn.sin.f32(float %x.fabs.fneg)1112 ret float %sin1113}1114 1115define float @sin_fabs_fneg_fast_f32(float %x) {1116; CHECK-LABEL: @sin_fabs_fneg_fast_f32(1117; CHECK-NEXT: [[X_FABS:%.*]] = call fast float @llvm.fabs.f32(float [[X:%.*]])1118; CHECK-NEXT: [[TMP1:%.*]] = call fast float @llvm.amdgcn.sin.f32(float [[X_FABS]])1119; CHECK-NEXT: [[SIN:%.*]] = fneg fast float [[TMP1]]1120; CHECK-NEXT: ret float [[SIN]]1121;1122 %x.fabs = call fast float @llvm.fabs.f32(float %x)1123 %x.fabs.fneg = fneg float %x.fabs1124 %sin = call fast float @llvm.amdgcn.sin.f32(float %x.fabs.fneg)1125 ret float %sin1126}1127 1128; --------------------------------------------------------------------1129; llvm.amdgcn.cvt.pkrtz1130; --------------------------------------------------------------------1131 1132declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) nounwind readnone1133 1134define <2 x half> @vars_lhs_cvt_pkrtz(float %x, float %y) {1135; CHECK-LABEL: @vars_lhs_cvt_pkrtz(1136; CHECK-NEXT: [[CVT:%.*]] = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float [[X:%.*]], float [[Y:%.*]])1137; CHECK-NEXT: ret <2 x half> [[CVT]]1138;1139 %cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %x, float %y)1140 ret <2 x half> %cvt1141}1142 1143define <2 x half> @constant_lhs_cvt_pkrtz(float %y) {1144; CHECK-LABEL: @constant_lhs_cvt_pkrtz(1145; CHECK-NEXT: [[CVT:%.*]] = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float 0.000000e+00, float [[Y:%.*]])1146; CHECK-NEXT: ret <2 x half> [[CVT]]1147;1148 %cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float 0.0, float %y)1149 ret <2 x half> %cvt1150}1151 1152define <2 x half> @constant_rhs_cvt_pkrtz(float %x) {1153; CHECK-LABEL: @constant_rhs_cvt_pkrtz(1154; CHECK-NEXT: [[CVT:%.*]] = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float [[X:%.*]], float 0.000000e+00)1155; CHECK-NEXT: ret <2 x half> [[CVT]]1156;1157 %cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %x, float 0.0)1158 ret <2 x half> %cvt1159}1160 1161define <2 x half> @undef_lhs_cvt_pkrtz(float %y) {1162; CHECK-LABEL: @undef_lhs_cvt_pkrtz(1163; CHECK-NEXT: [[CVT:%.*]] = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float [[Y:%.*]])1164; CHECK-NEXT: ret <2 x half> [[CVT]]1165;1166 %cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float %y)1167 ret <2 x half> %cvt1168}1169 1170define <2 x half> @undef_rhs_cvt_pkrtz(float %x) {1171; CHECK-LABEL: @undef_rhs_cvt_pkrtz(1172; CHECK-NEXT: [[CVT:%.*]] = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float [[X:%.*]], float undef)1173; CHECK-NEXT: ret <2 x half> [[CVT]]1174;1175 %cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %x, float undef)1176 ret <2 x half> %cvt1177}1178 1179define <2 x half> @undef_cvt_pkrtz() {1180; CHECK-LABEL: @undef_cvt_pkrtz(1181; CHECK-NEXT: ret <2 x half> undef1182;1183 %cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float undef)1184 ret <2 x half> %cvt1185}1186 1187define <2 x half> @constant_splat0_cvt_pkrtz() {1188; CHECK-LABEL: @constant_splat0_cvt_pkrtz(1189; CHECK-NEXT: ret <2 x half> zeroinitializer1190;1191 %cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float 0.0, float 0.0)1192 ret <2 x half> %cvt1193}1194 1195define <2 x half> @constant_cvt_pkrtz() {1196; CHECK-LABEL: @constant_cvt_pkrtz(1197; CHECK-NEXT: ret <2 x half> <half 0xH4000, half 0xH4400>1198;1199 %cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float 2.0, float 4.0)1200 ret <2 x half> %cvt1201}1202 1203; Test constant values where rtz changes result1204define <2 x half> @constant_rtz_pkrtz() {1205; CHECK-LABEL: @constant_rtz_pkrtz(1206; CHECK-NEXT: ret <2 x half> splat (half 0xH7BFF)1207;1208 %cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float 65535.0, float 65535.0)1209 ret <2 x half> %cvt1210}1211 1212define <2 x half> @fpext_const_cvt_pkrtz(half %x) {1213; CHECK-LABEL: @fpext_const_cvt_pkrtz(1214; CHECK-NEXT: [[CVT:%.*]] = insertelement <2 x half> <half poison, half 0xH4200>, half [[X:%.*]], i64 01215; CHECK-NEXT: ret <2 x half> [[CVT]]1216;1217 %ext = fpext half %x to float1218 %cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %ext, float 3.0)1219 ret <2 x half> %cvt1220}1221 1222define <2 x half> @const_fpext_cvt_pkrtz(half %y) {1223; CHECK-LABEL: @const_fpext_cvt_pkrtz(1224; CHECK-NEXT: [[CVT:%.*]] = insertelement <2 x half> <half 0xH4500, half poison>, half [[Y:%.*]], i64 11225; CHECK-NEXT: ret <2 x half> [[CVT]]1226;1227 %ext = fpext half %y to float1228 %cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float 5.0, float %ext)1229 ret <2 x half> %cvt1230}1231 1232define <2 x half> @const_fpext_multi_cvt_pkrtz(half %y) {1233; CHECK-LABEL: @const_fpext_multi_cvt_pkrtz(1234; CHECK-NEXT: [[CVT1:%.*]] = insertelement <2 x half> <half 0xH4500, half poison>, half [[Y:%.*]], i64 11235; CHECK-NEXT: [[CVT2:%.*]] = insertelement <2 x half> <half 0xH4200, half poison>, half [[Y]], i64 11236; CHECK-NEXT: [[ADD:%.*]] = fadd <2 x half> [[CVT1]], [[CVT2]]1237; CHECK-NEXT: ret <2 x half> [[ADD]]1238;1239 %ext = fpext half %y to float1240 %cvt1 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float 5.0, float %ext)1241 %cvt2 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float 3.0, float %ext)1242 %add = fadd <2 x half> %cvt1, %cvt21243 ret <2 x half> %add1244}1245 1246define <2 x half> @fpext_fpext_cvt_pkrtz(half %x, half %y) {1247; CHECK-LABEL: @fpext_fpext_cvt_pkrtz(1248; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x half> poison, half [[X:%.*]], i64 01249; CHECK-NEXT: [[CVT:%.*]] = insertelement <2 x half> [[TMP1]], half [[Y:%.*]], i64 11250; CHECK-NEXT: ret <2 x half> [[CVT]]1251;1252 %extx = fpext half %x to float1253 %exty = fpext half %y to float1254 %cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %extx, float %exty)1255 ret <2 x half> %cvt1256}1257 1258define <2 x half> @fpext_fpext_bf16_cvt_pkrtz(bfloat %x, bfloat %y) {1259; CHECK-LABEL: @fpext_fpext_bf16_cvt_pkrtz(1260; CHECK-NEXT: [[EXTX:%.*]] = fpext bfloat [[X:%.*]] to float1261; CHECK-NEXT: [[EXTY:%.*]] = fpext bfloat [[Y:%.*]] to float1262; CHECK-NEXT: [[CVT:%.*]] = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float [[EXTX]], float [[EXTY]])1263; CHECK-NEXT: ret <2 x half> [[CVT]]1264;1265 %extx = fpext bfloat %x to float1266 %exty = fpext bfloat %y to float1267 %cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %extx, float %exty)1268 ret <2 x half> %cvt1269}1270 1271define <2 x half> @poison_fpext_cvt_pkrtz(half %y) {1272; CHECK-LABEL: @poison_fpext_cvt_pkrtz(1273; CHECK-NEXT: [[CVT:%.*]] = insertelement <2 x half> poison, half [[Y:%.*]], i64 11274; CHECK-NEXT: ret <2 x half> [[CVT]]1275;1276 %ext = fpext half %y to float1277 %cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float poison, float %ext)1278 ret <2 x half> %cvt1279}1280 1281define <2 x half> @fpext_poison_cvt_pkrtz(half %x) {1282; CHECK-LABEL: @fpext_poison_cvt_pkrtz(1283; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x half> poison, half [[X:%.*]], i64 01284; CHECK-NEXT: ret <2 x half> [[TMP1]]1285;1286 %ext = fpext half %x to float1287 %cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %ext, float poison)1288 ret <2 x half> %cvt1289}1290 1291; --------------------------------------------------------------------1292; llvm.amdgcn.cvt.pknorm.i161293; --------------------------------------------------------------------1294 1295declare <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float, float) nounwind readnone1296 1297define <2 x i16> @undef_lhs_cvt_pknorm_i16(float %y) {1298; CHECK-LABEL: @undef_lhs_cvt_pknorm_i16(1299; CHECK-NEXT: [[CVT:%.*]] = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float undef, float [[Y:%.*]])1300; CHECK-NEXT: ret <2 x i16> [[CVT]]1301;1302 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float undef, float %y)1303 ret <2 x i16> %cvt1304}1305 1306define <2 x i16> @undef_rhs_cvt_pknorm_i16(float %x) {1307; CHECK-LABEL: @undef_rhs_cvt_pknorm_i16(1308; CHECK-NEXT: [[CVT:%.*]] = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float [[X:%.*]], float undef)1309; CHECK-NEXT: ret <2 x i16> [[CVT]]1310;1311 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float %x, float undef)1312 ret <2 x i16> %cvt1313}1314 1315define <2 x i16> @undef_cvt_pknorm_i16() {1316; CHECK-LABEL: @undef_cvt_pknorm_i16(1317; CHECK-NEXT: ret <2 x i16> undef1318;1319 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float undef, float undef)1320 ret <2 x i16> %cvt1321}1322 1323define <2 x i16> @poison_lhs_cvt_pknorm_i16(float %y) {1324; CHECK-LABEL: @poison_lhs_cvt_pknorm_i16(1325; CHECK-NEXT: [[CVT:%.*]] = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float poison, float [[Y:%.*]])1326; CHECK-NEXT: ret <2 x i16> [[CVT]]1327;1328 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float poison, float %y)1329 ret <2 x i16> %cvt1330}1331 1332define <2 x i16> @poison_rhs_cvt_pknorm_i16(float %x) {1333; CHECK-LABEL: @poison_rhs_cvt_pknorm_i16(1334; CHECK-NEXT: [[CVT:%.*]] = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float [[X:%.*]], float poison)1335; CHECK-NEXT: ret <2 x i16> [[CVT]]1336;1337 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float %x, float poison)1338 ret <2 x i16> %cvt1339}1340 1341define <2 x i16> @poison_cvt_pknorm_i16() {1342; CHECK-LABEL: @poison_cvt_pknorm_i16(1343; CHECK-NEXT: ret <2 x i16> poison1344;1345 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.i16(float poison, float poison)1346 ret <2 x i16> %cvt1347}1348 1349; --------------------------------------------------------------------1350; llvm.amdgcn.cvt.pknorm.u161351; --------------------------------------------------------------------1352 1353declare <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float, float) nounwind readnone1354 1355define <2 x i16> @undef_lhs_cvt_pknorm_u16(float %y) {1356; CHECK-LABEL: @undef_lhs_cvt_pknorm_u16(1357; CHECK-NEXT: [[CVT:%.*]] = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float undef, float [[Y:%.*]])1358; CHECK-NEXT: ret <2 x i16> [[CVT]]1359;1360 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float undef, float %y)1361 ret <2 x i16> %cvt1362}1363 1364define <2 x i16> @undef_rhs_cvt_pknorm_u16(float %x) {1365; CHECK-LABEL: @undef_rhs_cvt_pknorm_u16(1366; CHECK-NEXT: [[CVT:%.*]] = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float [[X:%.*]], float undef)1367; CHECK-NEXT: ret <2 x i16> [[CVT]]1368;1369 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float %x, float undef)1370 ret <2 x i16> %cvt1371}1372 1373define <2 x i16> @undef_cvt_pknorm_u16() {1374; CHECK-LABEL: @undef_cvt_pknorm_u16(1375; CHECK-NEXT: ret <2 x i16> undef1376;1377 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float undef, float undef)1378 ret <2 x i16> %cvt1379}1380 1381define <2 x i16> @poison_lhs_cvt_pknorm_u16(float %y) {1382; CHECK-LABEL: @poison_lhs_cvt_pknorm_u16(1383; CHECK-NEXT: [[CVT:%.*]] = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float poison, float [[Y:%.*]])1384; CHECK-NEXT: ret <2 x i16> [[CVT]]1385;1386 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float poison, float %y)1387 ret <2 x i16> %cvt1388}1389 1390define <2 x i16> @poison_rhs_cvt_pknorm_u16(float %x) {1391; CHECK-LABEL: @poison_rhs_cvt_pknorm_u16(1392; CHECK-NEXT: [[CVT:%.*]] = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float [[X:%.*]], float poison)1393; CHECK-NEXT: ret <2 x i16> [[CVT]]1394;1395 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float %x, float poison)1396 ret <2 x i16> %cvt1397}1398 1399define <2 x i16> @poison_cvt_pknorm_u16() {1400; CHECK-LABEL: @poison_cvt_pknorm_u16(1401; CHECK-NEXT: ret <2 x i16> poison1402;1403 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pknorm.u16(float poison, float poison)1404 ret <2 x i16> %cvt1405}1406 1407; --------------------------------------------------------------------1408; llvm.amdgcn.cvt.pk.i161409; --------------------------------------------------------------------1410 1411declare <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32, i32) nounwind readnone1412 1413define <2 x i16> @undef_lhs_cvt_pk_i16(i32 %y) {1414; CHECK-LABEL: @undef_lhs_cvt_pk_i16(1415; CHECK-NEXT: [[CVT:%.*]] = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 undef, i32 [[Y:%.*]])1416; CHECK-NEXT: ret <2 x i16> [[CVT]]1417;1418 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 undef, i32 %y)1419 ret <2 x i16> %cvt1420}1421 1422define <2 x i16> @undef_rhs_cvt_pk_i16(i32 %x) {1423; CHECK-LABEL: @undef_rhs_cvt_pk_i16(1424; CHECK-NEXT: [[CVT:%.*]] = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 [[X:%.*]], i32 undef)1425; CHECK-NEXT: ret <2 x i16> [[CVT]]1426;1427 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %x, i32 undef)1428 ret <2 x i16> %cvt1429}1430 1431define <2 x i16> @undef_cvt_pk_i16() {1432; CHECK-LABEL: @undef_cvt_pk_i16(1433; CHECK-NEXT: ret <2 x i16> undef1434;1435 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 undef, i32 undef)1436 ret <2 x i16> %cvt1437}1438 1439define <2 x i16> @poison_lhs_cvt_pk_i16(i32 %y) {1440; CHECK-LABEL: @poison_lhs_cvt_pk_i16(1441; CHECK-NEXT: [[CVT:%.*]] = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 poison, i32 [[Y:%.*]])1442; CHECK-NEXT: ret <2 x i16> [[CVT]]1443;1444 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 poison, i32 %y)1445 ret <2 x i16> %cvt1446}1447 1448define <2 x i16> @poison_rhs_cvt_pk_i16(i32 %x) {1449; CHECK-LABEL: @poison_rhs_cvt_pk_i16(1450; CHECK-NEXT: [[CVT:%.*]] = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 [[X:%.*]], i32 poison)1451; CHECK-NEXT: ret <2 x i16> [[CVT]]1452;1453 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 %x, i32 poison)1454 ret <2 x i16> %cvt1455}1456 1457define <2 x i16> @poison_cvt_pk_i16() {1458; CHECK-LABEL: @poison_cvt_pk_i16(1459; CHECK-NEXT: ret <2 x i16> poison1460;1461 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.i16(i32 poison, i32 poison)1462 ret <2 x i16> %cvt1463}1464 1465; --------------------------------------------------------------------1466; llvm.amdgcn.cvt.pk.u161467; --------------------------------------------------------------------1468 1469declare <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32, i32) nounwind readnone1470 1471define <2 x i16> @undef_lhs_cvt_pk_u16(i32 %y) {1472; CHECK-LABEL: @undef_lhs_cvt_pk_u16(1473; CHECK-NEXT: [[CVT:%.*]] = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 undef, i32 [[Y:%.*]])1474; CHECK-NEXT: ret <2 x i16> [[CVT]]1475;1476 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 undef, i32 %y)1477 ret <2 x i16> %cvt1478}1479 1480define <2 x i16> @undef_rhs_cvt_pk_u16(i32 %x) {1481; CHECK-LABEL: @undef_rhs_cvt_pk_u16(1482; CHECK-NEXT: [[CVT:%.*]] = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 [[X:%.*]], i32 undef)1483; CHECK-NEXT: ret <2 x i16> [[CVT]]1484;1485 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %x, i32 undef)1486 ret <2 x i16> %cvt1487}1488 1489define <2 x i16> @undef_cvt_pk_u16() {1490; CHECK-LABEL: @undef_cvt_pk_u16(1491; CHECK-NEXT: ret <2 x i16> undef1492;1493 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 undef, i32 undef)1494 ret <2 x i16> %cvt1495}1496 1497define <2 x i16> @poison_lhs_cvt_pk_u16(i32 %y) {1498; CHECK-LABEL: @poison_lhs_cvt_pk_u16(1499; CHECK-NEXT: [[CVT:%.*]] = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 poison, i32 [[Y:%.*]])1500; CHECK-NEXT: ret <2 x i16> [[CVT]]1501;1502 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 poison, i32 %y)1503 ret <2 x i16> %cvt1504}1505 1506define <2 x i16> @poison_rhs_cvt_pk_u16(i32 %x) {1507; CHECK-LABEL: @poison_rhs_cvt_pk_u16(1508; CHECK-NEXT: [[CVT:%.*]] = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 [[X:%.*]], i32 poison)1509; CHECK-NEXT: ret <2 x i16> [[CVT]]1510;1511 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %x, i32 poison)1512 ret <2 x i16> %cvt1513}1514 1515define <2 x i16> @poison_cvt_pk_u16() {1516; CHECK-LABEL: @poison_cvt_pk_u16(1517; CHECK-NEXT: ret <2 x i16> poison1518;1519 %cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 poison, i32 poison)1520 ret <2 x i16> %cvt1521}1522 1523; --------------------------------------------------------------------1524; llvm.amdgcn.ubfe1525; --------------------------------------------------------------------1526 1527declare i32 @llvm.amdgcn.ubfe.i32(i32, i32, i32) nounwind readnone1528declare i64 @llvm.amdgcn.ubfe.i64(i64, i32, i32) nounwind readnone1529 1530define i32 @ubfe_var_i32(i32 %src, i32 %offset, i32 %width) {1531; CHECK-LABEL: @ubfe_var_i32(1532; CHECK-NEXT: [[BFE:%.*]] = call i32 @llvm.amdgcn.ubfe.i32(i32 [[SRC:%.*]], i32 [[OFFSET:%.*]], i32 [[WIDTH:%.*]])1533; CHECK-NEXT: ret i32 [[BFE]]1534;1535 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %src, i32 %offset, i32 %width)1536 ret i32 %bfe1537}1538 1539define i32 @ubfe_clear_high_bits_constant_offset_i32(i32 %src, i32 %width) {1540; CHECK-LABEL: @ubfe_clear_high_bits_constant_offset_i32(1541; CHECK-NEXT: [[BFE:%.*]] = call i32 @llvm.amdgcn.ubfe.i32(i32 [[SRC:%.*]], i32 5, i32 [[WIDTH:%.*]])1542; CHECK-NEXT: ret i32 [[BFE]]1543;1544 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %src, i32 133, i32 %width)1545 ret i32 %bfe1546}1547 1548define i32 @ubfe_clear_high_bits_constant_width_i32(i32 %src, i32 %offset) {1549; CHECK-LABEL: @ubfe_clear_high_bits_constant_width_i32(1550; CHECK-NEXT: [[BFE:%.*]] = call i32 @llvm.amdgcn.ubfe.i32(i32 [[SRC:%.*]], i32 [[OFFSET:%.*]], i32 5)1551; CHECK-NEXT: ret i32 [[BFE]]1552;1553 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %src, i32 %offset, i32 133)1554 ret i32 %bfe1555}1556 1557define i32 @ubfe_width_0(i32 %src, i32 %offset) {1558; CHECK-LABEL: @ubfe_width_0(1559; CHECK-NEXT: ret i32 01560;1561 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %src, i32 %offset, i32 0)1562 ret i32 %bfe1563}1564 1565define i32 @ubfe_width_31(i32 %src, i32 %offset) {1566; CHECK-LABEL: @ubfe_width_31(1567; CHECK-NEXT: [[BFE:%.*]] = call i32 @llvm.amdgcn.ubfe.i32(i32 [[SRC:%.*]], i32 [[OFFSET:%.*]], i32 31)1568; CHECK-NEXT: ret i32 [[BFE]]1569;1570 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %src, i32 %offset, i32 31)1571 ret i32 %bfe1572}1573 1574define i32 @ubfe_width_32(i32 %src, i32 %offset) {1575; CHECK-LABEL: @ubfe_width_32(1576; CHECK-NEXT: ret i32 01577;1578 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %src, i32 %offset, i32 32)1579 ret i32 %bfe1580}1581 1582define i32 @ubfe_width_33(i32 %src, i32 %offset) {1583; CHECK-LABEL: @ubfe_width_33(1584; CHECK-NEXT: [[BFE:%.*]] = call i32 @llvm.amdgcn.ubfe.i32(i32 [[SRC:%.*]], i32 [[OFFSET:%.*]], i32 1)1585; CHECK-NEXT: ret i32 [[BFE]]1586;1587 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %src, i32 %offset, i32 33)1588 ret i32 %bfe1589}1590 1591define i32 @ubfe_offset_33(i32 %src, i32 %width) {1592; CHECK-LABEL: @ubfe_offset_33(1593; CHECK-NEXT: [[BFE:%.*]] = call i32 @llvm.amdgcn.ubfe.i32(i32 [[SRC:%.*]], i32 1, i32 [[WIDTH:%.*]])1594; CHECK-NEXT: ret i32 [[BFE]]1595;1596 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %src, i32 33, i32 %width)1597 ret i32 %bfe1598}1599 1600define i32 @ubfe_offset_0(i32 %src, i32 %width) {1601; CHECK-LABEL: @ubfe_offset_0(1602; CHECK-NEXT: [[BFE:%.*]] = call i32 @llvm.amdgcn.ubfe.i32(i32 [[SRC:%.*]], i32 0, i32 [[WIDTH:%.*]])1603; CHECK-NEXT: ret i32 [[BFE]]1604;1605 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %src, i32 0, i32 %width)1606 ret i32 %bfe1607}1608 1609define i32 @ubfe_offset_32(i32 %src, i32 %width) {1610; CHECK-LABEL: @ubfe_offset_32(1611; CHECK-NEXT: [[BFE:%.*]] = call i32 @llvm.amdgcn.ubfe.i32(i32 [[SRC:%.*]], i32 0, i32 [[WIDTH:%.*]])1612; CHECK-NEXT: ret i32 [[BFE]]1613;1614 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %src, i32 32, i32 %width)1615 ret i32 %bfe1616}1617 1618define i32 @ubfe_offset_31(i32 %src, i32 %width) {1619; CHECK-LABEL: @ubfe_offset_31(1620; CHECK-NEXT: [[BFE:%.*]] = call i32 @llvm.amdgcn.ubfe.i32(i32 [[SRC:%.*]], i32 31, i32 [[WIDTH:%.*]])1621; CHECK-NEXT: ret i32 [[BFE]]1622;1623 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %src, i32 31, i32 %width)1624 ret i32 %bfe1625}1626 1627define i32 @ubfe_offset_0_width_0(i32 %src) {1628; CHECK-LABEL: @ubfe_offset_0_width_0(1629; CHECK-NEXT: ret i32 01630;1631 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %src, i32 0, i32 0)1632 ret i32 %bfe1633}1634 1635define i32 @ubfe_offset_0_width_3(i32 %src) {1636; CHECK-LABEL: @ubfe_offset_0_width_3(1637; CHECK-NEXT: [[BFE:%.*]] = and i32 [[SRC:%.*]], 71638; CHECK-NEXT: ret i32 [[BFE]]1639;1640 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %src, i32 0, i32 3)1641 ret i32 %bfe1642}1643 1644define i32 @ubfe_offset_3_width_1(i32 %src) {1645; CHECK-LABEL: @ubfe_offset_3_width_1(1646; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[SRC:%.*]], 31647; CHECK-NEXT: [[BFE:%.*]] = and i32 [[TMP1]], 11648; CHECK-NEXT: ret i32 [[BFE]]1649;1650 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %src, i32 3, i32 1)1651 ret i32 %bfe1652}1653 1654define i32 @ubfe_offset_3_width_4(i32 %src) {1655; CHECK-LABEL: @ubfe_offset_3_width_4(1656; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[SRC:%.*]], 31657; CHECK-NEXT: [[BFE:%.*]] = and i32 [[TMP1]], 151658; CHECK-NEXT: ret i32 [[BFE]]1659;1660 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %src, i32 3, i32 4)1661 ret i32 %bfe1662}1663 1664define i32 @ubfe_0_0_0() {1665; CHECK-LABEL: @ubfe_0_0_0(1666; CHECK-NEXT: ret i32 01667;1668 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 0, i32 0, i32 0)1669 ret i32 %bfe1670}1671 1672define i32 @ubfe_neg1_5_7() {1673; CHECK-LABEL: @ubfe_neg1_5_7(1674; CHECK-NEXT: ret i32 1271675;1676 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 -1, i32 5, i32 7)1677 ret i32 %bfe1678}1679 1680define i32 @ubfe_undef_src_i32(i32 %offset, i32 %width) {1681; CHECK-LABEL: @ubfe_undef_src_i32(1682; CHECK-NEXT: ret i32 undef1683;1684 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 undef, i32 %offset, i32 %width)1685 ret i32 %bfe1686}1687 1688define i32 @ubfe_undef_offset_i32(i32 %src, i32 %width) {1689; CHECK-LABEL: @ubfe_undef_offset_i32(1690; CHECK-NEXT: [[BFE:%.*]] = call i32 @llvm.amdgcn.ubfe.i32(i32 [[SRC:%.*]], i32 undef, i32 [[WIDTH:%.*]])1691; CHECK-NEXT: ret i32 [[BFE]]1692;1693 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %src, i32 undef, i32 %width)1694 ret i32 %bfe1695}1696 1697define i32 @ubfe_undef_width_i32(i32 %src, i32 %offset) {1698; CHECK-LABEL: @ubfe_undef_width_i32(1699; CHECK-NEXT: [[BFE:%.*]] = call i32 @llvm.amdgcn.ubfe.i32(i32 [[SRC:%.*]], i32 [[OFFSET:%.*]], i32 undef)1700; CHECK-NEXT: ret i32 [[BFE]]1701;1702 %bfe = call i32 @llvm.amdgcn.ubfe.i32(i32 %src, i32 %offset, i32 undef)1703 ret i32 %bfe1704}1705 1706define i64 @ubfe_offset_33_width_4_i64(i64 %src) {1707; CHECK-LABEL: @ubfe_offset_33_width_4_i64(1708; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[SRC:%.*]], 331709; CHECK-NEXT: [[BFE:%.*]] = and i64 [[TMP1]], 151710; CHECK-NEXT: ret i64 [[BFE]]1711;1712 %bfe = call i64 @llvm.amdgcn.ubfe.i64(i64 %src, i32 33, i32 4)1713 ret i64 %bfe1714}1715 1716define i64 @ubfe_offset_0_i64(i64 %src, i32 %width) {1717; CHECK-LABEL: @ubfe_offset_0_i64(1718; CHECK-NEXT: [[BFE:%.*]] = call i64 @llvm.amdgcn.ubfe.i64(i64 [[SRC:%.*]], i32 0, i32 [[WIDTH:%.*]])1719; CHECK-NEXT: ret i64 [[BFE]]1720;1721 %bfe = call i64 @llvm.amdgcn.ubfe.i64(i64 %src, i32 0, i32 %width)1722 ret i64 %bfe1723}1724 1725define i64 @ubfe_offset_32_width_32_i64(i64 %src) {1726; CHECK-LABEL: @ubfe_offset_32_width_32_i64(1727; CHECK-NEXT: [[BFE:%.*]] = lshr i64 [[SRC:%.*]], 321728; CHECK-NEXT: ret i64 [[BFE]]1729;1730 %bfe = call i64 @llvm.amdgcn.ubfe.i64(i64 %src, i32 32, i32 32)1731 ret i64 %bfe1732}1733 1734; --------------------------------------------------------------------1735; llvm.amdgcn.sbfe1736; --------------------------------------------------------------------1737 1738declare i32 @llvm.amdgcn.sbfe.i32(i32, i32, i32) nounwind readnone1739declare i64 @llvm.amdgcn.sbfe.i64(i64, i32, i32) nounwind readnone1740 1741define i32 @sbfe_offset_31(i32 %src, i32 %width) {1742; CHECK-LABEL: @sbfe_offset_31(1743; CHECK-NEXT: [[BFE:%.*]] = call i32 @llvm.amdgcn.sbfe.i32(i32 [[SRC:%.*]], i32 31, i32 [[WIDTH:%.*]])1744; CHECK-NEXT: ret i32 [[BFE]]1745;1746 %bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 %src, i32 31, i32 %width)1747 ret i32 %bfe1748}1749 1750define i32 @sbfe_neg1_5_7() {1751; CHECK-LABEL: @sbfe_neg1_5_7(1752; CHECK-NEXT: ret i32 -11753;1754 %bfe = call i32 @llvm.amdgcn.sbfe.i32(i32 -1, i32 5, i32 7)1755 ret i32 %bfe1756}1757 1758define i64 @sbfe_offset_32_width_32_i64(i64 %src) {1759; CHECK-LABEL: @sbfe_offset_32_width_32_i64(1760; CHECK-NEXT: [[BFE:%.*]] = ashr i64 [[SRC:%.*]], 321761; CHECK-NEXT: ret i64 [[BFE]]1762;1763 %bfe = call i64 @llvm.amdgcn.sbfe.i64(i64 %src, i32 32, i32 32)1764 ret i64 %bfe1765}1766 1767; --------------------------------------------------------------------1768; llvm.amdgcn.exp1769; --------------------------------------------------------------------1770 1771declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg) nounwind inaccessiblememonly1772 1773 1774 1775 1776define void @exp_disabled_inputs_to_undef(float %x, float %y, float %z, float %w) {1777 ; enable src0..src3 constants1778; CHECK-LABEL: @exp_disabled_inputs_to_undef(1779; CHECK-NEXT: call void @llvm.amdgcn.exp.f32(i32 0, i32 1, float 1.000000e+00, float poison, float poison, float poison, i1 true, i1 false)1780; CHECK-NEXT: call void @llvm.amdgcn.exp.f32(i32 0, i32 2, float poison, float 2.000000e+00, float poison, float poison, i1 true, i1 false)1781; CHECK-NEXT: call void @llvm.amdgcn.exp.f32(i32 0, i32 4, float poison, float poison, float 5.000000e-01, float poison, i1 true, i1 false)1782; CHECK-NEXT: call void @llvm.amdgcn.exp.f32(i32 0, i32 8, float poison, float poison, float poison, float 4.000000e+00, i1 true, i1 false)1783; CHECK-NEXT: call void @llvm.amdgcn.exp.f32(i32 0, i32 1, float [[X:%.*]], float poison, float poison, float poison, i1 true, i1 false)1784; CHECK-NEXT: call void @llvm.amdgcn.exp.f32(i32 0, i32 2, float poison, float [[Y:%.*]], float poison, float poison, i1 true, i1 false)1785; CHECK-NEXT: call void @llvm.amdgcn.exp.f32(i32 0, i32 4, float poison, float poison, float [[Z:%.*]], float poison, i1 true, i1 false)1786; CHECK-NEXT: call void @llvm.amdgcn.exp.f32(i32 0, i32 8, float poison, float poison, float poison, float [[W:%.*]], i1 true, i1 false)1787; CHECK-NEXT: call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float poison, float poison, float poison, float poison, i1 true, i1 false)1788; CHECK-NEXT: call void @llvm.amdgcn.exp.f32(i32 0, i32 3, float 1.000000e+00, float 2.000000e+00, float poison, float poison, i1 true, i1 false)1789; CHECK-NEXT: call void @llvm.amdgcn.exp.f32(i32 0, i32 5, float 1.000000e+00, float poison, float 5.000000e-01, float poison, i1 true, i1 false)1790; CHECK-NEXT: call void @llvm.amdgcn.exp.f32(i32 0, i32 9, float 1.000000e+00, float poison, float poison, float 4.000000e+00, i1 false, i1 false)1791; CHECK-NEXT: call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float 1.000000e+00, float 2.000000e+00, float 5.000000e-01, float 4.000000e+00, i1 false, i1 false)1792; CHECK-NEXT: ret void1793;1794 call void @llvm.amdgcn.exp.f32(i32 0, i32 1, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)1795 call void @llvm.amdgcn.exp.f32(i32 0, i32 2, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)1796 call void @llvm.amdgcn.exp.f32(i32 0, i32 4, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)1797 call void @llvm.amdgcn.exp.f32(i32 0, i32 8, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)1798 1799 ; enable src0..src3 variables1800 call void @llvm.amdgcn.exp.f32(i32 0, i32 1, float %x, float %y, float %z, float %w, i1 true, i1 false)1801 call void @llvm.amdgcn.exp.f32(i32 0, i32 2, float %x, float %y, float %z, float %w, i1 true, i1 false)1802 call void @llvm.amdgcn.exp.f32(i32 0, i32 4, float %x, float %y, float %z, float %w, i1 true, i1 false)1803 call void @llvm.amdgcn.exp.f32(i32 0, i32 8, float %x, float %y, float %z, float %w, i1 true, i1 false)1804 1805 ; enable none1806 call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float %x, float %y, float %z, float %w, i1 true, i1 false)1807 1808 ; enable different source combinations1809 call void @llvm.amdgcn.exp.f32(i32 0, i32 3, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)1810 call void @llvm.amdgcn.exp.f32(i32 0, i32 5, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)1811 call void @llvm.amdgcn.exp.f32(i32 0, i32 9, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 false)1812 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 false)1813 1814 ret void1815}1816 1817; --------------------------------------------------------------------1818; llvm.amdgcn.exp.compr1819; --------------------------------------------------------------------1820 1821declare void @llvm.amdgcn.exp.compr.v2f16(i32 immarg, i32 immarg, <2 x half>, <2 x half>, i1 immarg, i1 immarg) nounwind inaccessiblememonly1822 1823 1824 1825define void @exp_compr_disabled_inputs_to_undef(<2 x half> %xy, <2 x half> %zw) {1826; CHECK-LABEL: @exp_compr_disabled_inputs_to_undef(1827; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> poison, <2 x half> poison, i1 true, i1 false)1828; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 1, <2 x half> <half 0xH3C00, half 0xH4000>, <2 x half> poison, i1 true, i1 false)1829; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 2, <2 x half> <half 0xH3C00, half 0xH4000>, <2 x half> poison, i1 true, i1 false)1830; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 3, <2 x half> <half 0xH3C00, half 0xH4000>, <2 x half> poison, i1 true, i1 false)1831; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> poison, <2 x half> poison, i1 true, i1 false)1832; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 1, <2 x half> [[XY:%.*]], <2 x half> poison, i1 true, i1 false)1833; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 2, <2 x half> [[XY]], <2 x half> poison, i1 true, i1 false)1834; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 3, <2 x half> [[XY]], <2 x half> poison, i1 true, i1 false)1835; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 12, <2 x half> poison, <2 x half> [[ZW:%.*]], i1 true, i1 false)1836; CHECK-NEXT: call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> [[XY]], <2 x half> [[ZW]], i1 true, i1 false)1837; CHECK-NEXT: ret void1838;1839 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 true, i1 false)1840 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 1, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 true, i1 false)1841 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 2, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 true, i1 false)1842 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 3, <2 x half> <half 1.0, half 2.0>, <2 x half> <half 0.5, half 4.0>, i1 true, i1 false)1843 1844 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> %xy, <2 x half> %zw, i1 true, i1 false)1845 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 1, <2 x half> %xy, <2 x half> %zw, i1 true, i1 false)1846 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 2, <2 x half> %xy, <2 x half> %zw, i1 true, i1 false)1847 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 3, <2 x half> %xy, <2 x half> %zw, i1 true, i1 false)1848 1849 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 12, <2 x half> %xy, <2 x half> %zw, i1 true, i1 false)1850 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %xy, <2 x half> %zw, i1 true, i1 false)1851 ret void1852}1853 1854; --------------------------------------------------------------------1855; llvm.amdgcn.icmp1856; --------------------------------------------------------------------1857 1858declare i64 @llvm.amdgcn.icmp.i64.i32(i32, i32, i32 immarg) nounwind readnone convergent1859declare i64 @llvm.amdgcn.icmp.i64.i64(i64, i64, i32 immarg) nounwind readnone convergent1860declare i64 @llvm.amdgcn.icmp.i64.i1(i1, i1, i32 immarg) nounwind readnone convergent1861 1862define i64 @invalid_icmp_code(i32 %a, i32 %b) {1863; CHECK-LABEL: @invalid_icmp_code(1864; CHECK-NEXT: [[UNDER:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[A:%.*]], i32 [[B:%.*]], i32 31)1865; CHECK-NEXT: [[OVER:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[A]], i32 [[B]], i32 42)1866; CHECK-NEXT: [[OR:%.*]] = or i64 [[UNDER]], [[OVER]]1867; CHECK-NEXT: ret i64 [[OR]]1868;1869 %under = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %a, i32 %b, i32 31)1870 %over = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %a, i32 %b, i32 42)1871 %or = or i64 %under, %over1872 ret i64 %or1873}1874 1875define i64 @icmp_constant_inputs_false() {1876; CHECK-LABEL: @icmp_constant_inputs_false(1877; CHECK-NEXT: ret i64 01878;1879 %result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 9, i32 8, i32 32)1880 ret i64 %result1881}1882 1883define i64 @icmp_constant_inputs_true() {1884; CHECK-LABEL: @icmp_constant_inputs_true(1885; CHECK-NEXT: [[RESULT:%.*]] = call i64 @llvm.read_register.i64(metadata [[META0:![0-9]+]]) #[[ATTR20:[0-9]+]]1886; CHECK-NEXT: ret i64 [[RESULT]]1887;1888 %result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 9, i32 8, i32 34)1889 ret i64 %result1890}1891 1892define i64 @icmp_constant_to_rhs_slt(i32 %x) {1893; CHECK-LABEL: @icmp_constant_to_rhs_slt(1894; CHECK-NEXT: [[RESULT:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[X:%.*]], i32 9, i32 38)1895; CHECK-NEXT: ret i64 [[RESULT]]1896;1897 %result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 9, i32 %x, i32 40)1898 ret i64 %result1899}1900 1901define i64 @fold_icmp_ne_0_zext_icmp_eq_i32(i32 %a, i32 %b) {1902; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_eq_i32(1903; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[A:%.*]], i32 [[B:%.*]], i32 32)1904; CHECK-NEXT: ret i64 [[MASK]]1905;1906 %cmp = icmp eq i32 %a, %b1907 %zext.cmp = zext i1 %cmp to i321908 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)1909 ret i64 %mask1910}1911 1912define i64 @fold_icmp_ne_0_zext_icmp_ne_i32(i32 %a, i32 %b) {1913; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_ne_i32(1914; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[A:%.*]], i32 [[B:%.*]], i32 33)1915; CHECK-NEXT: ret i64 [[MASK]]1916;1917 %cmp = icmp ne i32 %a, %b1918 %zext.cmp = zext i1 %cmp to i321919 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)1920 ret i64 %mask1921}1922 1923define i64 @fold_icmp_ne_0_zext_icmp_sle_i32(i32 %a, i32 %b) {1924; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_sle_i32(1925; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[A:%.*]], i32 [[B:%.*]], i32 41)1926; CHECK-NEXT: ret i64 [[MASK]]1927;1928 %cmp = icmp sle i32 %a, %b1929 %zext.cmp = zext i1 %cmp to i321930 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)1931 ret i64 %mask1932}1933 1934define i64 @fold_icmp_ne_0_zext_icmp_ugt_i64(i64 %a, i64 %b) {1935; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_ugt_i64(1936; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i64(i64 [[A:%.*]], i64 [[B:%.*]], i32 34)1937; CHECK-NEXT: ret i64 [[MASK]]1938;1939 %cmp = icmp ugt i64 %a, %b1940 %zext.cmp = zext i1 %cmp to i321941 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)1942 ret i64 %mask1943}1944 1945define i64 @fold_icmp_ne_0_zext_icmp_ult_swap_i64(i64 %a, i64 %b) {1946; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_ult_swap_i64(1947; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i64(i64 [[A:%.*]], i64 [[B:%.*]], i32 34)1948; CHECK-NEXT: ret i64 [[MASK]]1949;1950 %cmp = icmp ugt i64 %a, %b1951 %zext.cmp = zext i1 %cmp to i321952 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 0, i32 %zext.cmp, i32 33)1953 ret i64 %mask1954}1955 1956define i64 @fold_icmp_ne_0_zext_fcmp_oeq_f32(float %a, float %b) {1957; CHECK-LABEL: @fold_icmp_ne_0_zext_fcmp_oeq_f32(1958; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.fcmp.i64.f32(float [[A:%.*]], float [[B:%.*]], i32 1)1959; CHECK-NEXT: ret i64 [[MASK]]1960;1961 %cmp = fcmp oeq float %a, %b1962 %zext.cmp = zext i1 %cmp to i321963 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)1964 ret i64 %mask1965}1966 1967define i64 @fold_icmp_ne_0_zext_fcmp_une_f32(float %a, float %b) {1968; CHECK-LABEL: @fold_icmp_ne_0_zext_fcmp_une_f32(1969; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.fcmp.i64.f32(float [[A:%.*]], float [[B:%.*]], i32 14)1970; CHECK-NEXT: ret i64 [[MASK]]1971;1972 %cmp = fcmp une float %a, %b1973 %zext.cmp = zext i1 %cmp to i321974 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)1975 ret i64 %mask1976}1977 1978define i64 @fold_icmp_ne_0_zext_fcmp_olt_f64(double %a, double %b) {1979; CHECK-LABEL: @fold_icmp_ne_0_zext_fcmp_olt_f64(1980; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.fcmp.i64.f64(double [[A:%.*]], double [[B:%.*]], i32 4)1981; CHECK-NEXT: ret i64 [[MASK]]1982;1983 %cmp = fcmp olt double %a, %b1984 %zext.cmp = zext i1 %cmp to i321985 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)1986 ret i64 %mask1987}1988 1989define i64 @fold_icmp_sext_icmp_ne_0_i32(i32 %a, i32 %b) {1990; CHECK-LABEL: @fold_icmp_sext_icmp_ne_0_i32(1991; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[A:%.*]], i32 [[B:%.*]], i32 32)1992; CHECK-NEXT: ret i64 [[MASK]]1993;1994 %cmp = icmp eq i32 %a, %b1995 %sext.cmp = sext i1 %cmp to i321996 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %sext.cmp, i32 0, i32 33)1997 ret i64 %mask1998}1999 2000define i64 @fold_icmp_eq_0_zext_icmp_eq_i32(i32 %a, i32 %b) {2001; CHECK-LABEL: @fold_icmp_eq_0_zext_icmp_eq_i32(2002; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[A:%.*]], i32 [[B:%.*]], i32 33)2003; CHECK-NEXT: ret i64 [[MASK]]2004;2005 %cmp = icmp eq i32 %a, %b2006 %zext.cmp = zext i1 %cmp to i322007 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 32)2008 ret i64 %mask2009}2010 2011define i64 @fold_icmp_eq_0_zext_icmp_slt_i32(i32 %a, i32 %b) {2012; CHECK-LABEL: @fold_icmp_eq_0_zext_icmp_slt_i32(2013; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[A:%.*]], i32 [[B:%.*]], i32 39)2014; CHECK-NEXT: ret i64 [[MASK]]2015;2016 %cmp = icmp slt i32 %a, %b2017 %zext.cmp = zext i1 %cmp to i322018 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 32)2019 ret i64 %mask2020}2021 2022define i64 @fold_icmp_eq_0_zext_fcmp_oeq_f32(float %a, float %b) {2023; CHECK-LABEL: @fold_icmp_eq_0_zext_fcmp_oeq_f32(2024; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.fcmp.i64.f32(float [[A:%.*]], float [[B:%.*]], i32 14)2025; CHECK-NEXT: ret i64 [[MASK]]2026;2027 %cmp = fcmp oeq float %a, %b2028 %zext.cmp = zext i1 %cmp to i322029 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 32)2030 ret i64 %mask2031}2032 2033define i64 @fold_icmp_eq_0_zext_fcmp_ule_f32(float %a, float %b) {2034; CHECK-LABEL: @fold_icmp_eq_0_zext_fcmp_ule_f32(2035; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.fcmp.i64.f32(float [[A:%.*]], float [[B:%.*]], i32 2)2036; CHECK-NEXT: ret i64 [[MASK]]2037;2038 %cmp = fcmp ule float %a, %b2039 %zext.cmp = zext i1 %cmp to i322040 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 32)2041 ret i64 %mask2042}2043 2044define i64 @fold_icmp_eq_0_zext_fcmp_ogt_f32(float %a, float %b) {2045; CHECK-LABEL: @fold_icmp_eq_0_zext_fcmp_ogt_f32(2046; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.fcmp.i64.f32(float [[A:%.*]], float [[B:%.*]], i32 13)2047; CHECK-NEXT: ret i64 [[MASK]]2048;2049 %cmp = fcmp ogt float %a, %b2050 %zext.cmp = zext i1 %cmp to i322051 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 32)2052 ret i64 %mask2053}2054 2055define i64 @fold_icmp_zext_icmp_eq_1_i32(i32 %a, i32 %b) {2056; CHECK-LABEL: @fold_icmp_zext_icmp_eq_1_i32(2057; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[A:%.*]], i32 [[B:%.*]], i32 32)2058; CHECK-NEXT: ret i64 [[MASK]]2059;2060 %cmp = icmp eq i32 %a, %b2061 %zext.cmp = zext i1 %cmp to i322062 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 1, i32 32)2063 ret i64 %mask2064}2065 2066define i64 @fold_icmp_zext_argi1_eq_1_i32(i1 %cond) {2067; CHECK-LABEL: @fold_icmp_zext_argi1_eq_1_i32(2068; CHECK-NEXT: [[ZEXT_COND:%.*]] = zext i1 [[COND:%.*]] to i322069; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[ZEXT_COND]], i32 0, i32 33)2070; CHECK-NEXT: ret i64 [[MASK]]2071;2072 %zext.cond = zext i1 %cond to i322073 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cond, i32 1, i32 32)2074 ret i64 %mask2075}2076 2077define i64 @fold_icmp_zext_argi1_eq_neg1_i32(i1 %cond) {2078; CHECK-LABEL: @fold_icmp_zext_argi1_eq_neg1_i32(2079; CHECK-NEXT: [[ZEXT_COND:%.*]] = zext i1 [[COND:%.*]] to i322080; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[ZEXT_COND]], i32 -1, i32 32)2081; CHECK-NEXT: ret i64 [[MASK]]2082;2083 %zext.cond = zext i1 %cond to i322084 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cond, i32 -1, i32 32)2085 ret i64 %mask2086}2087 2088define i64 @fold_icmp_sext_argi1_eq_1_i32(i1 %cond) {2089; CHECK-LABEL: @fold_icmp_sext_argi1_eq_1_i32(2090; CHECK-NEXT: [[SEXT_COND:%.*]] = sext i1 [[COND:%.*]] to i322091; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[SEXT_COND]], i32 1, i32 32)2092; CHECK-NEXT: ret i64 [[MASK]]2093;2094 %sext.cond = sext i1 %cond to i322095 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %sext.cond, i32 1, i32 32)2096 ret i64 %mask2097}2098 2099define i64 @fold_icmp_sext_argi1_eq_neg1_i32(i1 %cond) {2100; CHECK-LABEL: @fold_icmp_sext_argi1_eq_neg1_i32(2101; CHECK-NEXT: [[SEXT_COND:%.*]] = sext i1 [[COND:%.*]] to i322102; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[SEXT_COND]], i32 0, i32 33)2103; CHECK-NEXT: ret i64 [[MASK]]2104;2105 %sext.cond = sext i1 %cond to i322106 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %sext.cond, i32 -1, i32 32)2107 ret i64 %mask2108}2109 2110define i64 @fold_icmp_sext_argi1_eq_neg1_i64(i1 %cond) {2111; CHECK-LABEL: @fold_icmp_sext_argi1_eq_neg1_i64(2112; CHECK-NEXT: [[SEXT_COND:%.*]] = sext i1 [[COND:%.*]] to i642113; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i64(i64 [[SEXT_COND]], i64 0, i32 33)2114; CHECK-NEXT: ret i64 [[MASK]]2115;2116 %sext.cond = sext i1 %cond to i642117 %mask = call i64 @llvm.amdgcn.icmp.i64.i64(i64 %sext.cond, i64 -1, i32 32)2118 ret i64 %mask2119}2120 2121; TODO: Should be able to fold to false2122define i64 @fold_icmp_sext_icmp_eq_1_i32(i32 %a, i32 %b) {2123; CHECK-LABEL: @fold_icmp_sext_icmp_eq_1_i32(2124; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]]2125; CHECK-NEXT: [[SEXT_CMP:%.*]] = sext i1 [[CMP]] to i322126; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[SEXT_CMP]], i32 1, i32 32)2127; CHECK-NEXT: ret i64 [[MASK]]2128;2129 %cmp = icmp eq i32 %a, %b2130 %sext.cmp = sext i1 %cmp to i322131 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %sext.cmp, i32 1, i32 32)2132 ret i64 %mask2133}2134 2135define i64 @fold_icmp_sext_icmp_eq_neg1_i32(i32 %a, i32 %b) {2136; CHECK-LABEL: @fold_icmp_sext_icmp_eq_neg1_i32(2137; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[A:%.*]], i32 [[B:%.*]], i32 32)2138; CHECK-NEXT: ret i64 [[MASK]]2139;2140 %cmp = icmp eq i32 %a, %b2141 %sext.cmp = sext i1 %cmp to i322142 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %sext.cmp, i32 -1, i32 32)2143 ret i64 %mask2144}2145 2146define i64 @fold_icmp_sext_icmp_sge_neg1_i32(i32 %a, i32 %b) {2147; CHECK-LABEL: @fold_icmp_sext_icmp_sge_neg1_i32(2148; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[A:%.*]], i32 [[B:%.*]], i32 39)2149; CHECK-NEXT: ret i64 [[MASK]]2150;2151 %cmp = icmp sge i32 %a, %b2152 %sext.cmp = sext i1 %cmp to i322153 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %sext.cmp, i32 -1, i32 32)2154 ret i64 %mask2155}2156 2157define i64 @fold_not_icmp_ne_0_zext_icmp_sle_i32(i32 %a, i32 %b) {2158; CHECK-LABEL: @fold_not_icmp_ne_0_zext_icmp_sle_i32(2159; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[A:%.*]], i32 [[B:%.*]], i32 38)2160; CHECK-NEXT: ret i64 [[MASK]]2161;2162 %cmp = icmp sle i32 %a, %b2163 %not = xor i1 %cmp, true2164 %zext.cmp = zext i1 %not to i322165 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)2166 ret i64 %mask2167}2168 2169define i64 @fold_icmp_ne_0_zext_icmp_eq_i4(i4 %a, i4 %b) {2170; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_eq_i4(2171; CHECK-NEXT: [[TMP1:%.*]] = zext i4 [[A:%.*]] to i162172; CHECK-NEXT: [[TMP2:%.*]] = zext i4 [[B:%.*]] to i162173; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i16(i16 [[TMP1]], i16 [[TMP2]], i32 32)2174; CHECK-NEXT: ret i64 [[MASK]]2175;2176 %cmp = icmp eq i4 %a, %b2177 %zext.cmp = zext i1 %cmp to i322178 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)2179 ret i64 %mask2180}2181 2182define i64 @fold_icmp_ne_0_zext_icmp_eq_i8(i8 %a, i8 %b) {2183; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_eq_i8(2184; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i162185; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[B:%.*]] to i162186; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i16(i16 [[TMP1]], i16 [[TMP2]], i32 32)2187; CHECK-NEXT: ret i64 [[MASK]]2188;2189 %cmp = icmp eq i8 %a, %b2190 %zext.cmp = zext i1 %cmp to i322191 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)2192 ret i64 %mask2193}2194 2195define i64 @fold_icmp_ne_0_zext_icmp_eq_i16(i16 %a, i16 %b) {2196; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_eq_i16(2197; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i16(i16 [[A:%.*]], i16 [[B:%.*]], i32 32)2198; CHECK-NEXT: ret i64 [[MASK]]2199;2200 %cmp = icmp eq i16 %a, %b2201 %zext.cmp = zext i1 %cmp to i322202 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)2203 ret i64 %mask2204}2205 2206define i64 @fold_icmp_ne_0_zext_icmp_eq_i36(i36 %a, i36 %b) {2207; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_eq_i36(2208; CHECK-NEXT: [[TMP1:%.*]] = zext i36 [[A:%.*]] to i642209; CHECK-NEXT: [[TMP2:%.*]] = zext i36 [[B:%.*]] to i642210; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i64(i64 [[TMP1]], i64 [[TMP2]], i32 32)2211; CHECK-NEXT: ret i64 [[MASK]]2212;2213 %cmp = icmp eq i36 %a, %b2214 %zext.cmp = zext i1 %cmp to i322215 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)2216 ret i64 %mask2217}2218 2219define i64 @fold_icmp_ne_0_zext_icmp_eq_i128(i128 %a, i128 %b) {2220; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_eq_i128(2221; CHECK-NEXT: [[CMP:%.*]] = icmp eq i128 [[A:%.*]], [[B:%.*]]2222; CHECK-NEXT: [[ZEXT_CMP:%.*]] = zext i1 [[CMP]] to i322223; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[ZEXT_CMP]], i32 0, i32 33)2224; CHECK-NEXT: ret i64 [[MASK]]2225;2226 %cmp = icmp eq i128 %a, %b2227 %zext.cmp = zext i1 %cmp to i322228 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)2229 ret i64 %mask2230}2231 2232define i64 @fold_icmp_ne_0_zext_fcmp_oeq_f16(half %a, half %b) {2233; CHECK-LABEL: @fold_icmp_ne_0_zext_fcmp_oeq_f16(2234; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.fcmp.i64.f16(half [[A:%.*]], half [[B:%.*]], i32 1)2235; CHECK-NEXT: ret i64 [[MASK]]2236;2237 %cmp = fcmp oeq half %a, %b2238 %zext.cmp = zext i1 %cmp to i322239 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)2240 ret i64 %mask2241}2242 2243define i64 @fold_icmp_ne_0_zext_fcmp_oeq_f128(fp128 %a, fp128 %b) {2244; CHECK-LABEL: @fold_icmp_ne_0_zext_fcmp_oeq_f128(2245; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq fp128 [[A:%.*]], [[B:%.*]]2246; CHECK-NEXT: [[ZEXT_CMP:%.*]] = zext i1 [[CMP]] to i322247; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i32(i32 [[ZEXT_CMP]], i32 0, i32 33)2248; CHECK-NEXT: ret i64 [[MASK]]2249;2250 %cmp = fcmp oeq fp128 %a, %b2251 %zext.cmp = zext i1 %cmp to i322252 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)2253 ret i64 %mask2254}2255 2256define i64 @fold_icmp_ne_0_zext_icmp_slt_i4(i4 %a, i4 %b) {2257; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_slt_i4(2258; CHECK-NEXT: [[TMP1:%.*]] = sext i4 [[A:%.*]] to i162259; CHECK-NEXT: [[TMP2:%.*]] = sext i4 [[B:%.*]] to i162260; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i16(i16 [[TMP1]], i16 [[TMP2]], i32 40)2261; CHECK-NEXT: ret i64 [[MASK]]2262;2263 %cmp = icmp slt i4 %a, %b2264 %zext.cmp = zext i1 %cmp to i322265 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)2266 ret i64 %mask2267}2268 2269define i64 @fold_icmp_ne_0_zext_icmp_slt_i8(i8 %a, i8 %b) {2270; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_slt_i8(2271; CHECK-NEXT: [[TMP1:%.*]] = sext i8 [[A:%.*]] to i162272; CHECK-NEXT: [[TMP2:%.*]] = sext i8 [[B:%.*]] to i162273; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i16(i16 [[TMP1]], i16 [[TMP2]], i32 40)2274; CHECK-NEXT: ret i64 [[MASK]]2275;2276 %cmp = icmp slt i8 %a, %b2277 %zext.cmp = zext i1 %cmp to i322278 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)2279 ret i64 %mask2280}2281 2282define i64 @fold_icmp_ne_0_zext_icmp_slt_i16(i16 %a, i16 %b) {2283; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_slt_i16(2284; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i16(i16 [[A:%.*]], i16 [[B:%.*]], i32 40)2285; CHECK-NEXT: ret i64 [[MASK]]2286;2287 %cmp = icmp slt i16 %a, %b2288 %zext.cmp = zext i1 %cmp to i322289 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)2290 ret i64 %mask2291}2292 2293define i64 @fold_icmp_ne_0_zext_icmp_ult_i4(i4 %a, i4 %b) {2294; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_ult_i4(2295; CHECK-NEXT: [[TMP1:%.*]] = zext i4 [[A:%.*]] to i162296; CHECK-NEXT: [[TMP2:%.*]] = zext i4 [[B:%.*]] to i162297; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i16(i16 [[TMP1]], i16 [[TMP2]], i32 36)2298; CHECK-NEXT: ret i64 [[MASK]]2299;2300 %cmp = icmp ult i4 %a, %b2301 %zext.cmp = zext i1 %cmp to i322302 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)2303 ret i64 %mask2304}2305 2306define i64 @fold_icmp_ne_0_zext_icmp_ult_i8(i8 %a, i8 %b) {2307; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_ult_i8(2308; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[A:%.*]] to i162309; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[B:%.*]] to i162310; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i16(i16 [[TMP1]], i16 [[TMP2]], i32 36)2311; CHECK-NEXT: ret i64 [[MASK]]2312;2313 %cmp = icmp ult i8 %a, %b2314 %zext.cmp = zext i1 %cmp to i322315 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)2316 ret i64 %mask2317}2318 2319define i64 @fold_icmp_ne_0_zext_icmp_ult_i16(i16 %a, i16 %b) {2320; CHECK-LABEL: @fold_icmp_ne_0_zext_icmp_ult_i16(2321; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i16(i16 [[A:%.*]], i16 [[B:%.*]], i32 36)2322; CHECK-NEXT: ret i64 [[MASK]]2323;2324 %cmp = icmp ult i16 %a, %b2325 %zext.cmp = zext i1 %cmp to i322326 %mask = call i64 @llvm.amdgcn.icmp.i64.i32(i32 %zext.cmp, i32 0, i32 33)2327 ret i64 %mask2328}2329 2330; 1-bit NE comparisons2331 2332define i64 @fold_icmp_i1_ne_0_icmp_eq_i1(i32 %a, i32 %b) {2333; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_eq_i1(2334; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]]2335; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)2336; CHECK-NEXT: ret i64 [[MASK]]2337;2338 %cmp = icmp eq i32 %a, %b2339 %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)2340 ret i64 %mask2341}2342 2343define i64 @fold_icmp_i1_ne_0_icmp_ne_i1(i32 %a, i32 %b) {2344; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_ne_i1(2345; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[A:%.*]], [[B:%.*]]2346; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)2347; CHECK-NEXT: ret i64 [[MASK]]2348;2349 %cmp = icmp ne i32 %a, %b2350 %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)2351 ret i64 %mask2352}2353 2354define i64 @fold_icmp_i1_ne_0_icmp_sle_i1(i32 %a, i32 %b) {2355; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_sle_i1(2356; CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[A:%.*]], [[B:%.*]]2357; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)2358; CHECK-NEXT: ret i64 [[MASK]]2359;2360 %cmp = icmp sle i32 %a, %b2361 %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)2362 ret i64 %mask2363}2364 2365define i64 @fold_icmp_i1_ne_0_icmp_ugt_i64(i64 %a, i64 %b) {2366; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_ugt_i64(2367; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i64 [[A:%.*]], [[B:%.*]]2368; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)2369; CHECK-NEXT: ret i64 [[MASK]]2370;2371 %cmp = icmp ugt i64 %a, %b2372 %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)2373 ret i64 %mask2374}2375 2376define i64 @fold_icmp_i1_ne_0_icmp_ult_swap_i64(i64 %a, i64 %b) {2377; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_ult_swap_i64(2378; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i64 [[A:%.*]], [[B:%.*]]2379; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)2380; CHECK-NEXT: ret i64 [[MASK]]2381;2382 %cmp = icmp ugt i64 %a, %b2383 %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 false, i1 %cmp, i32 33)2384 ret i64 %mask2385}2386 2387define i64 @fold_icmp_i1_ne_0_fcmp_oeq_f32(float %a, float %b) {2388; CHECK-LABEL: @fold_icmp_i1_ne_0_fcmp_oeq_f32(2389; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq float [[A:%.*]], [[B:%.*]]2390; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)2391; CHECK-NEXT: ret i64 [[MASK]]2392;2393 %cmp = fcmp oeq float %a, %b2394 %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)2395 ret i64 %mask2396}2397 2398define i64 @fold_icmp_i1_ne_0_fcmp_une_f32(float %a, float %b) {2399; CHECK-LABEL: @fold_icmp_i1_ne_0_fcmp_une_f32(2400; CHECK-NEXT: [[CMP:%.*]] = fcmp une float [[A:%.*]], [[B:%.*]]2401; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)2402; CHECK-NEXT: ret i64 [[MASK]]2403;2404 %cmp = fcmp une float %a, %b2405 %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)2406 ret i64 %mask2407}2408 2409define i64 @fold_icmp_i1_ne_0_fcmp_olt_f64(double %a, double %b) {2410; CHECK-LABEL: @fold_icmp_i1_ne_0_fcmp_olt_f64(2411; CHECK-NEXT: [[CMP:%.*]] = fcmp olt double [[A:%.*]], [[B:%.*]]2412; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)2413; CHECK-NEXT: ret i64 [[MASK]]2414;2415 %cmp = fcmp olt double %a, %b2416 %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)2417 ret i64 %mask2418}2419 2420define i64 @fold_icmp_i1_ne_0_icmp_eq_i4(i4 %a, i4 %b) {2421; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_eq_i4(2422; CHECK-NEXT: [[CMP:%.*]] = icmp eq i4 [[A:%.*]], [[B:%.*]]2423; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)2424; CHECK-NEXT: ret i64 [[MASK]]2425;2426 %cmp = icmp eq i4 %a, %b2427 %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)2428 ret i64 %mask2429}2430 2431define i64 @fold_icmp_i1_ne_0_icmp_eq_i8(i8 %a, i8 %b) {2432; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_eq_i8(2433; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[A:%.*]], [[B:%.*]]2434; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)2435; CHECK-NEXT: ret i64 [[MASK]]2436;2437 %cmp = icmp eq i8 %a, %b2438 %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)2439 ret i64 %mask2440}2441 2442define i64 @fold_icmp_i1_ne_0_icmp_eq_i16(i16 %a, i16 %b) {2443; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_eq_i16(2444; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[A:%.*]], [[B:%.*]]2445; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)2446; CHECK-NEXT: ret i64 [[MASK]]2447;2448 %cmp = icmp eq i16 %a, %b2449 %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)2450 ret i64 %mask2451}2452 2453define i64 @fold_icmp_i1_ne_0_icmp_eq_i36(i36 %a, i36 %b) {2454; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_eq_i36(2455; CHECK-NEXT: [[CMP:%.*]] = icmp eq i36 [[A:%.*]], [[B:%.*]]2456; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)2457; CHECK-NEXT: ret i64 [[MASK]]2458;2459 %cmp = icmp eq i36 %a, %b2460 %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)2461 ret i64 %mask2462}2463 2464define i64 @fold_icmp_i1_ne_0_icmp_eq_i128(i128 %a, i128 %b) {2465; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_eq_i128(2466; CHECK-NEXT: [[CMP:%.*]] = icmp eq i128 [[A:%.*]], [[B:%.*]]2467; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)2468; CHECK-NEXT: ret i64 [[MASK]]2469;2470 %cmp = icmp eq i128 %a, %b2471 %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)2472 ret i64 %mask2473}2474 2475define i64 @fold_icmp_i1_ne_0_fcmp_oeq_f16(half %a, half %b) {2476; CHECK-LABEL: @fold_icmp_i1_ne_0_fcmp_oeq_f16(2477; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq half [[A:%.*]], [[B:%.*]]2478; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)2479; CHECK-NEXT: ret i64 [[MASK]]2480;2481 %cmp = fcmp oeq half %a, %b2482 %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)2483 ret i64 %mask2484}2485 2486define i64 @fold_icmp_i1_ne_0_fcmp_oeq_f128(fp128 %a, fp128 %b) {2487; CHECK-LABEL: @fold_icmp_i1_ne_0_fcmp_oeq_f128(2488; CHECK-NEXT: [[CMP:%.*]] = fcmp oeq fp128 [[A:%.*]], [[B:%.*]]2489; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)2490; CHECK-NEXT: ret i64 [[MASK]]2491;2492 %cmp = fcmp oeq fp128 %a, %b2493 %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)2494 ret i64 %mask2495}2496 2497define i64 @fold_icmp_i1_ne_0_icmp_slt_i4(i4 %a, i4 %b) {2498; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_slt_i4(2499; CHECK-NEXT: [[CMP:%.*]] = icmp slt i4 [[A:%.*]], [[B:%.*]]2500; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)2501; CHECK-NEXT: ret i64 [[MASK]]2502;2503 %cmp = icmp slt i4 %a, %b2504 %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)2505 ret i64 %mask2506}2507 2508define i64 @fold_icmp_i1_ne_0_icmp_slt_i8(i8 %a, i8 %b) {2509; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_slt_i8(2510; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[A:%.*]], [[B:%.*]]2511; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)2512; CHECK-NEXT: ret i64 [[MASK]]2513;2514 %cmp = icmp slt i8 %a, %b2515 %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)2516 ret i64 %mask2517}2518 2519define i64 @fold_icmp_i1_ne_0_icmp_slt_i16(i16 %a, i16 %b) {2520; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_slt_i16(2521; CHECK-NEXT: [[CMP:%.*]] = icmp slt i16 [[A:%.*]], [[B:%.*]]2522; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)2523; CHECK-NEXT: ret i64 [[MASK]]2524;2525 %cmp = icmp slt i16 %a, %b2526 %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)2527 ret i64 %mask2528}2529 2530define i64 @fold_icmp_i1_ne_0_icmp_ult_i4(i4 %a, i4 %b) {2531; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_ult_i4(2532; CHECK-NEXT: [[CMP:%.*]] = icmp ult i4 [[A:%.*]], [[B:%.*]]2533; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)2534; CHECK-NEXT: ret i64 [[MASK]]2535;2536 %cmp = icmp ult i4 %a, %b2537 %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)2538 ret i64 %mask2539}2540 2541define i64 @fold_icmp_i1_ne_0_icmp_ult_i8(i8 %a, i8 %b) {2542; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_ult_i8(2543; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[A:%.*]], [[B:%.*]]2544; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)2545; CHECK-NEXT: ret i64 [[MASK]]2546;2547 %cmp = icmp ult i8 %a, %b2548 %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)2549 ret i64 %mask2550}2551 2552define i64 @fold_icmp_i1_ne_0_icmp_ult_i16(i16 %a, i16 %b) {2553; CHECK-LABEL: @fold_icmp_i1_ne_0_icmp_ult_i16(2554; CHECK-NEXT: [[CMP:%.*]] = icmp ult i16 [[A:%.*]], [[B:%.*]]2555; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.amdgcn.icmp.i64.i1(i1 [[CMP]], i1 false, i32 33)2556; CHECK-NEXT: ret i64 [[MASK]]2557;2558 %cmp = icmp ult i16 %a, %b2559 %mask = call i64 @llvm.amdgcn.icmp.i64.i1(i1 %cmp, i1 false, i32 33)2560 ret i64 %mask2561}2562 2563; --------------------------------------------------------------------2564; llvm.amdgcn.fcmp2565; --------------------------------------------------------------------2566 2567declare i64 @llvm.amdgcn.fcmp.i64.f32(float, float, i32 immarg) nounwind readnone convergent2568 2569define i64 @invalid_fcmp_code(float %a, float %b) {2570; CHECK-LABEL: @invalid_fcmp_code(2571; CHECK-NEXT: [[UNDER:%.*]] = call i64 @llvm.amdgcn.fcmp.i64.f32(float [[A:%.*]], float [[B:%.*]], i32 -1)2572; CHECK-NEXT: [[OVER:%.*]] = call i64 @llvm.amdgcn.fcmp.i64.f32(float [[A]], float [[B]], i32 16)2573; CHECK-NEXT: [[OR:%.*]] = or i64 [[UNDER]], [[OVER]]2574; CHECK-NEXT: ret i64 [[OR]]2575;2576 %under = call i64 @llvm.amdgcn.fcmp.i64.f32(float %a, float %b, i32 -1)2577 %over = call i64 @llvm.amdgcn.fcmp.i64.f32(float %a, float %b, i32 16)2578 %or = or i64 %under, %over2579 ret i64 %or2580}2581 2582define i64 @fcmp_constant_inputs_false() {2583; CHECK-LABEL: @fcmp_constant_inputs_false(2584; CHECK-NEXT: ret i64 02585;2586 %result = call i64 @llvm.amdgcn.fcmp.i64.f32(float 2.0, float 4.0, i32 1)2587 ret i64 %result2588}2589 2590define i64 @fcmp_constant_inputs_true() {2591; CHECK-LABEL: @fcmp_constant_inputs_true(2592; CHECK-NEXT: [[RESULT:%.*]] = call i64 @llvm.read_register.i64(metadata [[META0]]) #[[ATTR20]]2593; CHECK-NEXT: ret i64 [[RESULT]]2594;2595 %result = call i64 @llvm.amdgcn.fcmp.i64.f32(float 2.0, float 4.0, i32 4)2596 ret i64 %result2597}2598 2599define i64 @fcmp_constant_to_rhs_olt(float %x) {2600; CHECK-LABEL: @fcmp_constant_to_rhs_olt(2601; CHECK-NEXT: [[RESULT:%.*]] = call i64 @llvm.amdgcn.fcmp.i64.f32(float [[X:%.*]], float 4.000000e+00, i32 2)2602; CHECK-NEXT: ret i64 [[RESULT]]2603;2604 %result = call i64 @llvm.amdgcn.fcmp.i64.f32(float 4.0, float %x, i32 4)2605 ret i64 %result2606}2607 2608; --------------------------------------------------------------------2609; llvm.amdgcn.ballot2610; --------------------------------------------------------------------2611 2612declare i64 @llvm.amdgcn.ballot.i64(i1) nounwind readnone convergent2613declare i32 @llvm.amdgcn.ballot.i32(i1) nounwind readnone convergent2614 2615define i64 @ballot_nocombine_64(i1 %i) {2616; CHECK-LABEL: @ballot_nocombine_64(2617; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[I:%.*]])2618; CHECK-NEXT: [[B:%.*]] = zext i32 [[TMP1]] to i642619; CHECK-NEXT: ret i64 [[B]]2620;2621 %b = call i64 @llvm.amdgcn.ballot.i64(i1 %i)2622 ret i64 %b2623}2624 2625define i64 @ballot_zero_64() {2626; CHECK-LABEL: @ballot_zero_64(2627; CHECK-NEXT: ret i64 02628;2629 %b = call i64 @llvm.amdgcn.ballot.i64(i1 0)2630 ret i64 %b2631}2632 2633define i64 @ballot_one_64() {2634; CHECK-LABEL: @ballot_one_64(2635; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 true)2636; CHECK-NEXT: [[B:%.*]] = zext i32 [[TMP1]] to i642637; CHECK-NEXT: ret i64 [[B]]2638;2639 %b = call i64 @llvm.amdgcn.ballot.i64(i1 1)2640 ret i64 %b2641}2642 2643define i32 @ballot_nocombine_32(i1 %i) {2644; CHECK-LABEL: @ballot_nocombine_32(2645; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 [[I:%.*]])2646; CHECK-NEXT: ret i32 [[B]]2647;2648 %b = call i32 @llvm.amdgcn.ballot.i32(i1 %i)2649 ret i32 %b2650}2651 2652define i32 @ballot_zero_32() {2653; CHECK-LABEL: @ballot_zero_32(2654; CHECK-NEXT: ret i32 02655;2656 %b = call i32 @llvm.amdgcn.ballot.i32(i1 0)2657 ret i32 %b2658}2659 2660define i32 @ballot_one_32() {2661; CHECK-LABEL: @ballot_one_32(2662; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.amdgcn.ballot.i32(i1 true)2663; CHECK-NEXT: ret i32 [[B]]2664;2665 %b = call i32 @llvm.amdgcn.ballot.i32(i1 1)2666 ret i32 %b2667}2668 2669define i64 @ballot_poison_64() {2670; CHECK-LABEL: @ballot_poison_64(2671; CHECK-NEXT: ret i64 poison2672;2673 %b = call i64 @llvm.amdgcn.ballot.i64(i1 poison)2674 ret i64 %b2675}2676 2677define i32 @ballot_poison_32() {2678; CHECK-LABEL: @ballot_poison_32(2679; CHECK-NEXT: ret i32 poison2680;2681 %b = call i32 @llvm.amdgcn.ballot.i32(i1 poison)2682 ret i32 %b2683}2684 2685; --------------------------------------------------------------------2686; llvm.amdgcn.wqm.vote2687; --------------------------------------------------------------------2688 2689declare i1 @llvm.amdgcn.wqm.vote(i1)2690 2691define float @wqm_vote_true() {2692; CHECK-LABEL: @wqm_vote_true(2693; CHECK-NEXT: main_body:2694; CHECK-NEXT: ret float 1.000000e+002695;2696main_body:2697 %w = call i1 @llvm.amdgcn.wqm.vote(i1 true)2698 %r = select i1 %w, float 1.0, float 0.02699 ret float %r2700}2701 2702define float @wqm_vote_false() {2703; CHECK-LABEL: @wqm_vote_false(2704; CHECK-NEXT: main_body:2705; CHECK-NEXT: ret float 0.000000e+002706;2707main_body:2708 %w = call i1 @llvm.amdgcn.wqm.vote(i1 false)2709 %r = select i1 %w, float 1.0, float 0.02710 ret float %r2711}2712 2713define float @wqm_vote_undef() {2714; CHECK-LABEL: @wqm_vote_undef(2715; CHECK-NEXT: main_body:2716; CHECK-NEXT: ret float 0.000000e+002717;2718main_body:2719 %w = call i1 @llvm.amdgcn.wqm.vote(i1 undef)2720 %r = select i1 %w, float 1.0, float 0.02721 ret float %r2722}2723 2724; --------------------------------------------------------------------2725; llvm.amdgcn.kill2726; --------------------------------------------------------------------2727 2728declare void @llvm.amdgcn.kill(i1)2729 2730define void @kill_true() {2731; CHECK-LABEL: @kill_true(2732; CHECK-NEXT: ret void2733;2734 call void @llvm.amdgcn.kill(i1 true)2735 ret void2736}2737 2738; --------------------------------------------------------------------2739; llvm.amdgcn.readfirstlane2740; --------------------------------------------------------------------2741 2742declare i32 @llvm.amdgcn.readfirstlane(i32)2743 2744@gv = constant i32 02745 2746define amdgpu_cs void @readfirstlane_constant(i32 %arg, ptr %ptr) {2747; CHECK-LABEL: @readfirstlane_constant(2748; CHECK-NEXT: [[VAR:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[ARG:%.*]])2749; CHECK-NEXT: store volatile i32 [[VAR]], ptr [[PTR:%.*]], align 42750; CHECK-NEXT: store volatile i32 0, ptr [[PTR]], align 42751; CHECK-NEXT: store volatile i32 123, ptr [[PTR]], align 42752; CHECK-NEXT: store volatile i32 ptrtoint (ptr @gv to i32), ptr [[PTR]], align 42753; CHECK-NEXT: store volatile i32 undef, ptr [[PTR]], align 42754; CHECK-NEXT: ret void2755;2756 %var = call i32 @llvm.amdgcn.readfirstlane(i32 %arg)2757 %zero = call i32 @llvm.amdgcn.readfirstlane(i32 0)2758 %imm = call i32 @llvm.amdgcn.readfirstlane(i32 123)2759 %constexpr = call i32 @llvm.amdgcn.readfirstlane(i32 ptrtoint (ptr @gv to i32))2760 %undef = call i32 @llvm.amdgcn.readfirstlane(i32 undef)2761 store volatile i32 %var, ptr %ptr2762 store volatile i32 %zero, ptr %ptr2763 store volatile i32 %imm, ptr %ptr2764 store volatile i32 %constexpr, ptr %ptr2765 store volatile i32 %undef, ptr %ptr2766 ret void2767}2768 2769define i32 @readfirstlane_idempotent(i32 %arg) {2770; CHECK-LABEL: @readfirstlane_idempotent(2771; CHECK-NEXT: [[READ0:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[ARG:%.*]])2772; CHECK-NEXT: ret i32 [[READ0]]2773;2774 %read0 = call i32 @llvm.amdgcn.readfirstlane(i32 %arg)2775 %read1 = call i32 @llvm.amdgcn.readfirstlane(i32 %read0)2776 %read2 = call i32 @llvm.amdgcn.readfirstlane(i32 %read1)2777 ret i32 %read22778}2779 2780define i32 @readfirstlane_readlane(i32 %arg) {2781; CHECK-LABEL: @readfirstlane_readlane(2782; CHECK-NEXT: [[READ0:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[ARG:%.*]])2783; CHECK-NEXT: ret i32 [[READ0]]2784;2785 %read0 = call i32 @llvm.amdgcn.readfirstlane(i32 %arg)2786 %read1 = call i32 @llvm.amdgcn.readlane(i32 %read0, i32 0)2787 ret i32 %read12788}2789 2790define i32 @readfirstlane_readfirstlane_different_block(i32 %arg) {2791; CHECK-LABEL: @readfirstlane_readfirstlane_different_block(2792; CHECK-NEXT: bb0:2793; CHECK-NEXT: [[READ0:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[ARG:%.*]])2794; CHECK-NEXT: br label [[BB1:%.*]]2795; CHECK: bb1:2796; CHECK-NEXT: [[READ1:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[READ0]])2797; CHECK-NEXT: ret i32 [[READ1]]2798;2799bb0:2800 %read0 = call i32 @llvm.amdgcn.readfirstlane(i32 %arg)2801 br label %bb12802 2803bb1:2804 %read1 = call i32 @llvm.amdgcn.readfirstlane(i32 %read0)2805 ret i32 %read12806}2807 2808define i32 @readfirstlane_readlane_different_block(i32 %arg) {2809; CHECK-LABEL: @readfirstlane_readlane_different_block(2810; CHECK-NEXT: bb0:2811; CHECK-NEXT: [[READ0:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG:%.*]], i32 0)2812; CHECK-NEXT: br label [[BB1:%.*]]2813; CHECK: bb1:2814; CHECK-NEXT: [[READ1:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[READ0]])2815; CHECK-NEXT: ret i32 [[READ1]]2816;2817bb0:2818 %read0 = call i32 @llvm.amdgcn.readlane(i32 %arg, i32 0)2819 br label %bb12820 2821bb1:2822 %read1 = call i32 @llvm.amdgcn.readfirstlane(i32 %read0)2823 ret i32 %read12824}2825 2826; --------------------------------------------------------------------2827; llvm.amdgcn.readlane2828; --------------------------------------------------------------------2829 2830declare i32 @llvm.amdgcn.readlane(i32, i32)2831 2832define amdgpu_cs void @readlane_constant(i32 %arg, i32 %lane, ptr %ptr) {2833; CHECK-LABEL: @readlane_constant(2834; CHECK-NEXT: [[VAR:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG:%.*]], i32 7)2835; CHECK-NEXT: store volatile i32 [[VAR]], ptr [[PTR:%.*]], align 42836; CHECK-NEXT: store volatile i32 0, ptr [[PTR]], align 42837; CHECK-NEXT: store volatile i32 123, ptr [[PTR]], align 42838; CHECK-NEXT: store volatile i32 ptrtoint (ptr @gv to i32), ptr [[PTR]], align 42839; CHECK-NEXT: store volatile i32 undef, ptr [[PTR]], align 42840; CHECK-NEXT: ret void2841;2842 %var = call i32 @llvm.amdgcn.readlane(i32 %arg, i32 7)2843 %zero = call i32 @llvm.amdgcn.readlane(i32 0, i32 %lane)2844 %imm = call i32 @llvm.amdgcn.readlane(i32 123, i32 %lane)2845 %constexpr = call i32 @llvm.amdgcn.readlane(i32 ptrtoint (ptr @gv to i32), i32 %lane)2846 %undef = call i32 @llvm.amdgcn.readlane(i32 undef, i32 %lane)2847 store volatile i32 %var, ptr %ptr2848 store volatile i32 %zero, ptr %ptr2849 store volatile i32 %imm, ptr %ptr2850 store volatile i32 %constexpr, ptr %ptr2851 store volatile i32 %undef, ptr %ptr2852 ret void2853}2854 2855define i32 @readlane_idempotent(i32 %arg, i32 %lane) {2856; CHECK-LABEL: @readlane_idempotent(2857; CHECK-NEXT: [[READ0:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG:%.*]], i32 [[LANE:%.*]])2858; CHECK-NEXT: ret i32 [[READ0]]2859;2860 %read0 = call i32 @llvm.amdgcn.readlane(i32 %arg, i32 %lane)2861 %read1 = call i32 @llvm.amdgcn.readlane(i32 %read0, i32 %lane)2862 ret i32 %read12863}2864 2865define i32 @readlane_idempotent_different_lanes(i32 %arg, i32 %lane0, i32 %lane1) {2866; CHECK-LABEL: @readlane_idempotent_different_lanes(2867; CHECK-NEXT: [[READ0:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG:%.*]], i32 [[LANE0:%.*]])2868; CHECK-NEXT: ret i32 [[READ0]]2869;2870 %read0 = call i32 @llvm.amdgcn.readlane(i32 %arg, i32 %lane0)2871 %read1 = call i32 @llvm.amdgcn.readlane(i32 %read0, i32 %lane1)2872 ret i32 %read12873}2874 2875define i32 @readlane_readfirstlane(i32 %arg) {2876; CHECK-LABEL: @readlane_readfirstlane(2877; CHECK-NEXT: [[READ0:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[ARG:%.*]])2878; CHECK-NEXT: ret i32 [[READ0]]2879;2880 %read0 = call i32 @llvm.amdgcn.readfirstlane(i32 %arg)2881 %read1 = call i32 @llvm.amdgcn.readlane(i32 %read0, i32 0)2882 ret i32 %read12883}2884 2885define i32 @readlane_idempotent_different_block(i32 %arg, i32 %lane) {2886; CHECK-LABEL: @readlane_idempotent_different_block(2887; CHECK-NEXT: bb0:2888; CHECK-NEXT: [[READ0:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG:%.*]], i32 [[LANE:%.*]])2889; CHECK-NEXT: br label [[BB1:%.*]]2890; CHECK: bb1:2891; CHECK-NEXT: [[READ1:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[READ0]], i32 [[LANE]])2892; CHECK-NEXT: ret i32 [[READ1]]2893;2894bb0:2895 %read0 = call i32 @llvm.amdgcn.readlane(i32 %arg, i32 %lane)2896 br label %bb12897 2898bb1:2899 %read1 = call i32 @llvm.amdgcn.readlane(i32 %read0, i32 %lane)2900 ret i32 %read12901}2902 2903 2904define i32 @readlane_readfirstlane_different_block(i32 %arg) {2905; CHECK-LABEL: @readlane_readfirstlane_different_block(2906; CHECK-NEXT: bb0:2907; CHECK-NEXT: [[READ0:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[ARG:%.*]])2908; CHECK-NEXT: br label [[BB1:%.*]]2909; CHECK: bb1:2910; CHECK-NEXT: [[READ1:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[READ0]], i32 0)2911; CHECK-NEXT: ret i32 [[READ1]]2912;2913bb0:2914 %read0 = call i32 @llvm.amdgcn.readfirstlane(i32 %arg)2915 br label %bb12916 2917bb1:2918 %read1 = call i32 @llvm.amdgcn.readlane(i32 %read0, i32 0)2919 ret i32 %read12920}2921 2922; --------------------------------------------------------------------2923; llvm.amdgcn.update.dpp.i322924; --------------------------------------------------------------------2925 2926declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1)2927 2928define amdgpu_kernel void @update_dpp_no_combine(ptr addrspace(1) %out, i32 %in1, i32 %in2) {2929; CHECK-LABEL: @update_dpp_no_combine(2930; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 [[IN1:%.*]], i32 [[IN2:%.*]], i32 1, i32 1, i32 1, i1 false)2931; CHECK-NEXT: store i32 [[TMP0]], ptr addrspace(1) [[OUT:%.*]], align 42932; CHECK-NEXT: ret void2933;2934 %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 0)2935 store i32 %tmp0, ptr addrspace(1) %out2936 ret void2937}2938 2939define amdgpu_kernel void @update_dpp_drop_old(ptr addrspace(1) %out, i32 %in1, i32 %in2) {2940; CHECK-LABEL: @update_dpp_drop_old(2941; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 poison, i32 [[IN2:%.*]], i32 3, i32 15, i32 15, i1 true)2942; CHECK-NEXT: store i32 [[TMP0]], ptr addrspace(1) [[OUT:%.*]], align 42943; CHECK-NEXT: ret void2944;2945 %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 3, i32 15, i32 15, i1 1)2946 store i32 %tmp0, ptr addrspace(1) %out2947 ret void2948}2949 2950define amdgpu_kernel void @update_dpp_undef_old(ptr addrspace(1) %out, i32 %in1) {2951; CHECK-LABEL: @update_dpp_undef_old(2952; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 poison, i32 [[IN1:%.*]], i32 4, i32 15, i32 15, i1 true)2953; CHECK-NEXT: store i32 [[TMP0]], ptr addrspace(1) [[OUT:%.*]], align 42954; CHECK-NEXT: ret void2955;2956 %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 undef, i32 %in1, i32 4, i32 15, i32 15, i1 1)2957 store i32 %tmp0, ptr addrspace(1) %out2958 ret void2959}2960 2961 2962; --------------------------------------------------------------------2963; llvm.amdgcn.permlane162964; --------------------------------------------------------------------2965 2966declare i32 @llvm.amdgcn.permlane16.i32(i32, i32, i32, i32, i1 immarg, i1 immarg)2967 2968define amdgpu_kernel void @permlane16(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) {2969; CHECK-LABEL: @permlane16(2970; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.permlane16.i32(i32 12345, i32 [[SRC0:%.*]], i32 [[SRC1:%.*]], i32 [[SRC2:%.*]], i1 false, i1 false)2971; CHECK-NEXT: store i32 [[RES]], ptr addrspace(1) [[OUT:%.*]], align 42972; CHECK-NEXT: ret void2973;2974 %res = call i32 @llvm.amdgcn.permlane16.i32(i32 12345, i32 %src0, i32 %src1, i32 %src2, i1 false, i1 false)2975 store i32 %res, ptr addrspace(1) %out2976 ret void2977}2978 2979define amdgpu_kernel void @permlane16_bound_ctrl(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) {2980; CHECK-LABEL: @permlane16_bound_ctrl(2981; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.permlane16.i32(i32 poison, i32 [[SRC0:%.*]], i32 [[SRC1:%.*]], i32 [[SRC2:%.*]], i1 false, i1 true)2982; CHECK-NEXT: store i32 [[RES]], ptr addrspace(1) [[OUT:%.*]], align 42983; CHECK-NEXT: ret void2984;2985 %res = call i32 @llvm.amdgcn.permlane16.i32(i32 12345, i32 %src0, i32 %src1, i32 %src2, i1 false, i1 true)2986 store i32 %res, ptr addrspace(1) %out2987 ret void2988}2989 2990define amdgpu_kernel void @permlane16_fetch_invalid_bound_ctrl(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) {2991; CHECK-LABEL: @permlane16_fetch_invalid_bound_ctrl(2992; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.permlane16.i32(i32 poison, i32 [[SRC0:%.*]], i32 [[SRC1:%.*]], i32 [[SRC2:%.*]], i1 true, i1 true)2993; CHECK-NEXT: store i32 [[RES]], ptr addrspace(1) [[OUT:%.*]], align 42994; CHECK-NEXT: ret void2995;2996 %res = call i32 @llvm.amdgcn.permlane16.i32(i32 12345, i32 %src0, i32 %src1, i32 %src2, i1 true, i1 true)2997 store i32 %res, ptr addrspace(1) %out2998 ret void2999}3000 3001; --------------------------------------------------------------------3002; llvm.amdgcn.permlanex163003; --------------------------------------------------------------------3004 3005declare i32 @llvm.amdgcn.permlanex16.i32(i32, i32, i32, i32, i1 immarg, i1 immarg)3006 3007define amdgpu_kernel void @permlanex16(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) {3008; CHECK-LABEL: @permlanex16(3009; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.permlanex16.i32(i32 12345, i32 [[SRC0:%.*]], i32 [[SRC1:%.*]], i32 [[SRC2:%.*]], i1 false, i1 false)3010; CHECK-NEXT: store i32 [[RES]], ptr addrspace(1) [[OUT:%.*]], align 43011; CHECK-NEXT: ret void3012;3013 %res = call i32 @llvm.amdgcn.permlanex16.i32(i32 12345, i32 %src0, i32 %src1, i32 %src2, i1 false, i1 false)3014 store i32 %res, ptr addrspace(1) %out3015 ret void3016}3017 3018define amdgpu_kernel void @permlanex16_bound_ctrl(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) {3019; CHECK-LABEL: @permlanex16_bound_ctrl(3020; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.permlanex16.i32(i32 poison, i32 [[SRC0:%.*]], i32 [[SRC1:%.*]], i32 [[SRC2:%.*]], i1 false, i1 true)3021; CHECK-NEXT: store i32 [[RES]], ptr addrspace(1) [[OUT:%.*]], align 43022; CHECK-NEXT: ret void3023;3024 %res = call i32 @llvm.amdgcn.permlanex16.i32(i32 12345, i32 %src0, i32 %src1, i32 %src2, i1 false, i1 true)3025 store i32 %res, ptr addrspace(1) %out3026 ret void3027}3028 3029define amdgpu_kernel void @permlanex16_fetch_invalid_bound_ctrl(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) {3030; CHECK-LABEL: @permlanex16_fetch_invalid_bound_ctrl(3031; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.permlanex16.i32(i32 poison, i32 [[SRC0:%.*]], i32 [[SRC1:%.*]], i32 [[SRC2:%.*]], i1 true, i1 true)3032; CHECK-NEXT: store i32 [[RES]], ptr addrspace(1) [[OUT:%.*]], align 43033; CHECK-NEXT: ret void3034;3035 %res = call i32 @llvm.amdgcn.permlanex16.i32(i32 12345, i32 %src0, i32 %src1, i32 %src2, i1 true, i1 true)3036 store i32 %res, ptr addrspace(1) %out3037 ret void3038}3039 3040; --------------------------------------------------------------------3041; llvm.amdgcn.permlane643042; --------------------------------------------------------------------3043 3044define amdgpu_kernel void @permlane64_uniform(ptr addrspace(1) %out, i32 %src) {3045; CHECK-LABEL: @permlane64_uniform(3046; CHECK-NEXT: store i32 [[SRC1:%.*]], ptr addrspace(1) [[OUT:%.*]], align 43047; CHECK-NEXT: ret void3048;3049 %res = call i32 @llvm.amdgcn.permlane64(i32 %src)3050 store i32 %res, ptr addrspace(1) %out3051 ret void3052}3053 3054; --------------------------------------------------------------------3055; llvm.amdgcn.image.sample a163056; --------------------------------------------------------------------3057 3058declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32.v8i32.v4i32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13059declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32.v8i32.v4i32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13060declare <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32.v8i32.v4i32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13061declare <4 x float> @llvm.amdgcn.image.sample.cube.v4f32.f32.v8i32.v4i32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13062declare <4 x float> @llvm.amdgcn.image.sample.1darray.v4f32.f32.v8i32.v4i32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13063declare <4 x float> @llvm.amdgcn.image.sample.2darray.v4f32.f32.v8i32.v4i32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13064 3065declare <4 x float> @llvm.amdgcn.image.sample.c.1d.v4f32.f32.v8i32.v4i32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13066declare <4 x float> @llvm.amdgcn.image.sample.c.2d.v4f32.f32.v8i32.v4i32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13067declare <4 x float> @llvm.amdgcn.image.sample.cl.1d.v4f32.f32.v8i32.v4i32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13068declare <4 x float> @llvm.amdgcn.image.sample.cl.2d.v4f32.f32.v8i32.v4i32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13069declare <4 x float> @llvm.amdgcn.image.sample.c.cl.1d.v4f32.f32.v8i32.v4i32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13070declare <4 x float> @llvm.amdgcn.image.sample.c.cl.2d.v4f32.f32.v8i32.v4i32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13071 3072declare <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13073declare <4 x float> @llvm.amdgcn.image.sample.b.2d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13074declare <4 x float> @llvm.amdgcn.image.sample.c.b.1d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13075declare <4 x float> @llvm.amdgcn.image.sample.c.b.2d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13076declare <4 x float> @llvm.amdgcn.image.sample.b.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13077declare <4 x float> @llvm.amdgcn.image.sample.b.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13078declare <4 x float> @llvm.amdgcn.image.sample.c.b.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13079declare <4 x float> @llvm.amdgcn.image.sample.c.b.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13080 3081declare <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13082declare <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13083declare <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13084declare <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13085declare <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13086declare <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13087declare <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13088declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13089declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13090 3091declare <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13092declare <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13093declare <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13094declare <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13095declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13096declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13097declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13098declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32, float, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13099 3100declare <4 x float> @llvm.amdgcn.image.sample.l.1d.v4f32.f32.v8i32.v4i32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13101declare <4 x float> @llvm.amdgcn.image.sample.l.2d.v4f32.f32.v8i32.v4i32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13102declare <4 x float> @llvm.amdgcn.image.sample.c.l.1d.v4f32.f32.v8i32.v4i32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13103declare <4 x float> @llvm.amdgcn.image.sample.c.l.2d.v4f32.f32.v8i32.v4i32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13104 3105declare <4 x float> @llvm.amdgcn.image.sample.lz.1d.v4f32.f32.v8i32.v4i32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13106declare <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32.v8i32.v4i32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13107declare <4 x float> @llvm.amdgcn.image.sample.c.lz.1d.v4f32.f32.v8i32.v4i32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13108declare <4 x float> @llvm.amdgcn.image.sample.c.lz.2d.v4f32.f32.v8i32.v4i32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13109 3110declare float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13111declare <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #13112 3113define amdgpu_kernel void @image_sample_a16_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s) {3114; CHECK-LABEL: @image_sample_a16_1d(3115; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f16.v8i32.v4i32(i32 15, half [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3116; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163117; CHECK-NEXT: ret void3118;3119 %s32 = fpext half %s to float3120 %res = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32.v8i32.v4i32(i32 15, float %s32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3121 store <4 x float> %res, ptr addrspace(1) %out3122 ret void3123}3124 3125define amdgpu_kernel void @image_sample_a16_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t) {3126; CHECK-LABEL: @image_sample_a16_2d(3127; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f16.v8i32.v4i32(i32 15, half [[S:%.*]], half [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3128; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163129; CHECK-NEXT: ret void3130;3131 %s32 = fpext half %s to float3132 %t32 = fpext half %t to float3133 %res = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32.v8i32.v4i32(i32 15, float %s32, float %t32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3134 store <4 x float> %res, ptr addrspace(1) %out3135 ret void3136}3137 3138define amdgpu_kernel void @image_sample_a16_3d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %r) {3139; CHECK-LABEL: @image_sample_a16_3d(3140; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f16.v8i32.v4i32(i32 15, half [[S:%.*]], half [[T:%.*]], half [[R:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3141; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163142; CHECK-NEXT: ret void3143;3144 %s32 = fpext half %s to float3145 %t32 = fpext half %t to float3146 %r32 = fpext half %r to float3147 %res = call <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32.v8i32.v4i32(i32 15, float %s32, float %t32, float %r32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3148 store <4 x float> %res, ptr addrspace(1) %out3149 ret void3150}3151 3152define amdgpu_kernel void @image_sample_a16_cube(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %face) {3153;3154; CHECK-LABEL: @image_sample_a16_cube(3155; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.cube.v4f32.f16.v8i32.v4i32(i32 15, half [[S:%.*]], half [[T:%.*]], half [[FACE:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3156; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163157; CHECK-NEXT: ret void3158;3159 %s32 = fpext half %s to float3160 %t32 = fpext half %t to float3161 %face32 = fpext half %face to float3162 %res = call <4 x float> @llvm.amdgcn.image.sample.cube.v4f32.f32.v8i32.v4i32(i32 15, float %s32, float %t32, float %face32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3163 store <4 x float> %res, ptr addrspace(1) %out3164 ret void3165}3166 3167define amdgpu_kernel void @image_sample_a16_1darray(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %slice) {3168; CHECK-LABEL: @image_sample_a16_1darray(3169; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.1darray.v4f32.f16.v8i32.v4i32(i32 15, half [[S:%.*]], half [[SLICE:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3170; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163171; CHECK-NEXT: ret void3172;3173 %s32 = fpext half %s to float3174 %slice32 = fpext half %slice to float3175 %res = call <4 x float> @llvm.amdgcn.image.sample.1darray.v4f32.f32.v8i32.v4i32(i32 15, float %s32, float %slice32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3176 store <4 x float> %res, ptr addrspace(1) %out3177 ret void3178}3179 3180define amdgpu_kernel void @image_sample_a16_2darray(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %slice) {3181; CHECK-LABEL: @image_sample_a16_2darray(3182; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.2darray.v4f32.f16.v8i32.v4i32(i32 15, half [[S:%.*]], half [[T:%.*]], half [[SLICE:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3183; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163184; CHECK-NEXT: ret void3185;3186 %s32 = fpext half %s to float3187 %t32 = fpext half %t to float3188 %slice32 = fpext half %slice to float3189 %res = call <4 x float> @llvm.amdgcn.image.sample.2darray.v4f32.f32.v8i32.v4i32(i32 15, float %s32, float %t32, float %slice32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3190 store <4 x float> %res, ptr addrspace(1) %out3191 ret void3192}3193 3194define amdgpu_kernel void @image_sample_a16_c_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s) {3195; CHECK-LABEL: @image_sample_a16_c_1d(3196; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.1d.v4f32.f16.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], half [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3197; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163198; CHECK-NEXT: ret void3199;3200 %s32 = fpext half %s to float3201 %res = call <4 x float> @llvm.amdgcn.image.sample.c.1d.v4f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %s32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3202 store <4 x float> %res, ptr addrspace(1) %out3203 ret void3204}3205 3206define amdgpu_kernel void @image_sample_a16_c_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t) {3207; CHECK-LABEL: @image_sample_a16_c_2d(3208; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.2d.v4f32.f16.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], half [[S:%.*]], half [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3209; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163210; CHECK-NEXT: ret void3211;3212 %s32 = fpext half %s to float3213 %t32 = fpext half %t to float3214 %res = call <4 x float> @llvm.amdgcn.image.sample.c.2d.v4f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %s32, float %t32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3215 store <4 x float> %res, ptr addrspace(1) %out3216 ret void3217}3218 3219define amdgpu_kernel void @image_sample_a16_cl_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %clamp) {3220; CHECK-LABEL: @image_sample_a16_cl_1d(3221; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.cl.1d.v4f32.f16.v8i32.v4i32(i32 15, half [[S:%.*]], half [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3222; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163223; CHECK-NEXT: ret void3224;3225 %s32 = fpext half %s to float3226 %clamp32 = fpext half %clamp to float3227 %res = call <4 x float> @llvm.amdgcn.image.sample.cl.1d.v4f32.f32.v8i32.v4i32(i32 15, float %s32, float %clamp32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3228 store <4 x float> %res, ptr addrspace(1) %out3229 ret void3230}3231 3232define amdgpu_kernel void @image_sample_a16_cl_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %clamp) {3233; CHECK-LABEL: @image_sample_a16_cl_2d(3234; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.cl.2d.v4f32.f16.v8i32.v4i32(i32 15, half [[S:%.*]], half [[T:%.*]], half [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3235; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163236; CHECK-NEXT: ret void3237;3238 %s32 = fpext half %s to float3239 %t32 = fpext half %t to float3240 %clamp32 = fpext half %clamp to float3241 %res = call <4 x float> @llvm.amdgcn.image.sample.cl.2d.v4f32.f32.v8i32.v4i32(i32 15, float %s32, float %t32, float %clamp32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3242 store <4 x float> %res, ptr addrspace(1) %out3243 ret void3244}3245 3246define amdgpu_kernel void @image_sample_a16_c_cl_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %clamp) {3247; CHECK-LABEL: @image_sample_a16_c_cl_1d(3248; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.cl.1d.v4f32.f16.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], half [[S:%.*]], half [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3249; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163250; CHECK-NEXT: ret void3251;3252 %s32 = fpext half %s to float3253 %clamp32 = fpext half %clamp to float3254 %res = call <4 x float> @llvm.amdgcn.image.sample.c.cl.1d.v4f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %s32, float %clamp32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3255 store <4 x float> %res, ptr addrspace(1) %out3256 ret void3257}3258 3259define amdgpu_kernel void @image_sample_a16_c_cl_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t, half %clamp) {3260; CHECK-LABEL: @image_sample_a16_c_cl_2d(3261; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.cl.2d.v4f32.f16.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], half [[S:%.*]], half [[T:%.*]], half [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3262; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163263; CHECK-NEXT: ret void3264;3265 %s32 = fpext half %s to float3266 %t32 = fpext half %t to float3267 %clamp32 = fpext half %clamp to float3268 %res = call <4 x float> @llvm.amdgcn.image.sample.c.cl.2d.v4f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %s32, float %t32, float %clamp32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3269 store <4 x float> %res, ptr addrspace(1) %out3270 ret void3271}3272 3273define amdgpu_kernel void @image_sample_a16_b16_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %bias, half %s) {3274; CHECK-LABEL: @image_sample_a16_b16_1d(3275; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f16.f16.v8i32.v4i32(i32 15, half [[BIAS:%.*]], half [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3276; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163277; CHECK-NEXT: ret void3278;3279 %bias32 = fpext half %bias to float3280 %s32 = fpext half %s to float3281 %res = call <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %bias32, float %s32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3282 store <4 x float> %res, ptr addrspace(1) %out3283 ret void3284}3285 3286define amdgpu_kernel void @image_sample_a16_b32_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, half %s) {3287; CHECK-LABEL: @image_sample_a16_b32_1d(3288; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float3289; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[BIAS:%.*]], float [[S32]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3290; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163291; CHECK-NEXT: ret void3292;3293 %s32 = fpext half %s to float3294 %res = call <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %bias, float %s32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3295 store <4 x float> %res, ptr addrspace(1) %out3296 ret void3297}3298 3299define amdgpu_kernel void @image_sample_a16_b16_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %bias, half %s, half %t) {3300; CHECK-LABEL: @image_sample_a16_b16_2d(3301; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.b.2d.v4f32.f16.f16.v8i32.v4i32(i32 15, half [[BIAS:%.*]], half [[S:%.*]], half [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3302; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163303; CHECK-NEXT: ret void3304;3305 %bias32 = fpext half %bias to float3306 %s32 = fpext half %s to float3307 %t32 = fpext half %t to float3308 %res = call <4 x float> @llvm.amdgcn.image.sample.b.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %bias32, float %s32, float %t32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3309 store <4 x float> %res, ptr addrspace(1) %out3310 ret void3311}3312 3313define amdgpu_kernel void @image_sample_a16_b32_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, half %s, half %t) {3314; CHECK-LABEL: @image_sample_a16_b32_2d(3315; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float3316; CHECK-NEXT: [[T32:%.*]] = fpext half [[T:%.*]] to float3317; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.b.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[BIAS:%.*]], float [[S32]], float [[T32]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3318; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163319; CHECK-NEXT: ret void3320;3321 %s32 = fpext half %s to float3322 %t32 = fpext half %t to float3323 %res = call <4 x float> @llvm.amdgcn.image.sample.b.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %bias, float %s32, float %t32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3324 store <4 x float> %res, ptr addrspace(1) %out3325 ret void3326}3327 3328define amdgpu_kernel void @image_sample_a16_c_b16_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %bias, float %zcompare, half %s) {3329; CHECK-LABEL: @image_sample_a16_c_b16_1d(3330; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.b.1d.v4f32.f16.f16.v8i32.v4i32(i32 15, half [[BIAS:%.*]], float [[ZCOMPARE:%.*]], half [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3331; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163332; CHECK-NEXT: ret void3333;3334 %bias32 = fpext half %bias to float3335 %s32 = fpext half %s to float3336 %res = call <4 x float> @llvm.amdgcn.image.sample.c.b.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %bias32, float %zcompare, float %s32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3337 store <4 x float> %res, ptr addrspace(1) %out3338 ret void3339}3340 3341define amdgpu_kernel void @image_sample_a16_c_b32_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, half %s) {3342; CHECK-LABEL: @image_sample_a16_c_b32_1d(3343; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float3344; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.b.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[BIAS:%.*]], float [[ZCOMPARE:%.*]], float [[S32]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3345; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163346; CHECK-NEXT: ret void3347;3348 %s32 = fpext half %s to float3349 %res = call <4 x float> @llvm.amdgcn.image.sample.c.b.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %bias, float %zcompare, float %s32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3350 store <4 x float> %res, ptr addrspace(1) %out3351 ret void3352}3353 3354define amdgpu_kernel void @image_sample_a16_c_b16_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %bias, float %zcompare, half %s, half %t) {3355; CHECK-LABEL: @image_sample_a16_c_b16_2d(3356; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.b.2d.v4f32.f16.f16.v8i32.v4i32(i32 15, half [[BIAS:%.*]], float [[ZCOMPARE:%.*]], half [[S:%.*]], half [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3357; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163358; CHECK-NEXT: ret void3359;3360 %bias32 = fpext half %bias to float3361 %s32 = fpext half %s to float3362 %t32 = fpext half %t to float3363 %res = call <4 x float> @llvm.amdgcn.image.sample.c.b.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %bias32, float %zcompare, float %s32, float %t32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3364 store <4 x float> %res, ptr addrspace(1) %out3365 ret void3366}3367 3368define amdgpu_kernel void @image_sample_a16_c_b32_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, half %s, half %t) {3369; CHECK-LABEL: @image_sample_a16_c_b32_2d(3370; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float3371; CHECK-NEXT: [[T32:%.*]] = fpext half [[T:%.*]] to float3372; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.b.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[BIAS:%.*]], float [[ZCOMPARE:%.*]], float [[S32]], float [[T32]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3373; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163374; CHECK-NEXT: ret void3375;3376 %s32 = fpext half %s to float3377 %t32 = fpext half %t to float3378 %res = call <4 x float> @llvm.amdgcn.image.sample.c.b.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %bias, float %zcompare, float %s32, float %t32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3379 store <4 x float> %res, ptr addrspace(1) %out3380 ret void3381}3382 3383define amdgpu_kernel void @image_sample_a16_b16_cl_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %bias, half %s, half %clamp) {3384; CHECK-LABEL: @image_sample_a16_b16_cl_1d(3385; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.b.cl.1d.v4f32.f16.f16.v8i32.v4i32(i32 15, half [[BIAS:%.*]], half [[S:%.*]], half [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3386; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163387; CHECK-NEXT: ret void3388;3389 %bias32 = fpext half %bias to float3390 %s32 = fpext half %s to float3391 %clamp32 = fpext half %clamp to float3392 %res = call <4 x float> @llvm.amdgcn.image.sample.b.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %bias32, float %s32, float %clamp32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3393 store <4 x float> %res, ptr addrspace(1) %out3394 ret void3395}3396 3397define amdgpu_kernel void @image_sample_a16_b32_cl_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, half %s, half %clamp) {3398; CHECK-LABEL: @image_sample_a16_b32_cl_1d(3399; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float3400; CHECK-NEXT: [[CLAMP32:%.*]] = fpext half [[CLAMP:%.*]] to float3401; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.b.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[BIAS:%.*]], float [[S32]], float [[CLAMP32]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3402; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163403; CHECK-NEXT: ret void3404;3405 %s32 = fpext half %s to float3406 %clamp32 = fpext half %clamp to float3407 %res = call <4 x float> @llvm.amdgcn.image.sample.b.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %bias, float %s32, float %clamp32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3408 store <4 x float> %res, ptr addrspace(1) %out3409 ret void3410}3411 3412define amdgpu_kernel void @image_sample_a16_b16_cl_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %bias, half %s, half %t, half %clamp) {3413; CHECK-LABEL: @image_sample_a16_b16_cl_2d(3414; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.b.cl.2d.v4f32.f16.f16.v8i32.v4i32(i32 15, half [[BIAS:%.*]], half [[S:%.*]], half [[T:%.*]], half [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3415; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163416; CHECK-NEXT: ret void3417;3418 %bias32 = fpext half %bias to float3419 %s32 = fpext half %s to float3420 %t32 = fpext half %t to float3421 %clamp32 = fpext half %clamp to float3422 %res = call <4 x float> @llvm.amdgcn.image.sample.b.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %bias32, float %s32, float %t32, float %clamp32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3423 store <4 x float> %res, ptr addrspace(1) %out3424 ret void3425}3426 3427define amdgpu_kernel void @image_sample_a16_b32_cl_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, half %s, half %t, half %clamp) {3428; CHECK-LABEL: @image_sample_a16_b32_cl_2d(3429; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float3430; CHECK-NEXT: [[T32:%.*]] = fpext half [[T:%.*]] to float3431; CHECK-NEXT: [[CLAMP32:%.*]] = fpext half [[CLAMP:%.*]] to float3432; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.b.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[BIAS:%.*]], float [[S32]], float [[T32]], float [[CLAMP32]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3433; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163434; CHECK-NEXT: ret void3435;3436 %s32 = fpext half %s to float3437 %t32 = fpext half %t to float3438 %clamp32 = fpext half %clamp to float3439 %res = call <4 x float> @llvm.amdgcn.image.sample.b.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %bias, float %s32, float %t32, float %clamp32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3440 store <4 x float> %res, ptr addrspace(1) %out3441 ret void3442}3443 3444define amdgpu_kernel void @image_sample_a16_c_b16_cl_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %bias, float %zcompare, half %s, half %clamp) {3445; CHECK-LABEL: @image_sample_a16_c_b16_cl_1d(3446; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.1d.v4f32.f16.f16.v8i32.v4i32(i32 15, half [[BIAS:%.*]], float [[ZCOMPARE:%.*]], half [[S:%.*]], half [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3447; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163448; CHECK-NEXT: ret void3449;3450 %bias32 = fpext half %bias to float3451 %s32 = fpext half %s to float3452 %clamp32 = fpext half %clamp to float3453 %res = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %bias32, float %zcompare, float %s32, float %clamp32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3454 store <4 x float> %res, ptr addrspace(1) %out3455 ret void3456}3457 3458define amdgpu_kernel void @image_sample_a16_c_b32_cl_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, half %s, half %clamp) {3459; CHECK-LABEL: @image_sample_a16_c_b32_cl_1d(3460; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float3461; CHECK-NEXT: [[CLAMP32:%.*]] = fpext half [[CLAMP:%.*]] to float3462; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[BIAS:%.*]], float [[ZCOMPARE:%.*]], float [[S32]], float [[CLAMP32]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3463; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163464; CHECK-NEXT: ret void3465;3466 %s32 = fpext half %s to float3467 %clamp32 = fpext half %clamp to float3468 %res = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %bias, float %zcompare, float %s32, float %clamp32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3469 store <4 x float> %res, ptr addrspace(1) %out3470 ret void3471}3472 3473define amdgpu_kernel void @image_sample_a16_c_b16_cl_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %bias, float %zcompare, half %s, half %t, half %clamp) {3474; CHECK-LABEL: @image_sample_a16_c_b16_cl_2d(3475; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.2d.v4f32.f16.f16.v8i32.v4i32(i32 15, half [[BIAS:%.*]], float [[ZCOMPARE:%.*]], half [[S:%.*]], half [[T:%.*]], half [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3476; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163477; CHECK-NEXT: ret void3478;3479 %bias32 = fpext half %bias to float3480 %s32 = fpext half %s to float3481 %t32 = fpext half %t to float3482 %clamp32 = fpext half %clamp to float3483 %res = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %bias32, float %zcompare, float %s32, float %t32, float %clamp32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3484 store <4 x float> %res, ptr addrspace(1) %out3485 ret void3486}3487 3488define amdgpu_kernel void @image_sample_a16_c_b32_cl_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, half %s, half %t, half %clamp) {3489; CHECK-LABEL: @image_sample_a16_c_b32_cl_2d(3490; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float3491; CHECK-NEXT: [[T32:%.*]] = fpext half [[T:%.*]] to float3492; CHECK-NEXT: [[CLAMP32:%.*]] = fpext half [[CLAMP:%.*]] to float3493; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[BIAS:%.*]], float [[ZCOMPARE:%.*]], float [[S32]], float [[T32]], float [[CLAMP32]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3494; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163495; CHECK-NEXT: ret void3496;3497 %s32 = fpext half %s to float3498 %t32 = fpext half %t to float3499 %clamp32 = fpext half %clamp to float3500 %res = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %bias, float %zcompare, float %s32, float %t32, float %clamp32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3501 store <4 x float> %res, ptr addrspace(1) %out3502 ret void3503}3504 3505define amdgpu_kernel void @image_sample_a16_d_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, half %s) {3506; CHECK-LABEL: @image_sample_a16_d_1d(3507; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f16.f16.v8i32.v4i32(i32 15, half [[DSDH:%.*]], half [[DSDV:%.*]], half [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3508; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163509; CHECK-NEXT: ret void3510;3511 %dsdh32 = fpext half %dsdh to float3512 %dsdv32 = fpext half %dsdv to float3513 %s32 = fpext half %s to float3514 %res = call <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %dsdh32, float %dsdv32, float %s32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3515 store <4 x float> %res, ptr addrspace(1) %out3516 ret void3517}3518 3519define amdgpu_kernel void @image_sample_a16_d_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {3520; CHECK-LABEL: @image_sample_a16_d_2d(3521; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f16.f16.v8i32.v4i32(i32 15, half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], half [[S:%.*]], half [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3522; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163523; CHECK-NEXT: ret void3524;3525 %dsdh32 = fpext half %dsdh to float3526 %dtdh32 = fpext half %dtdh to float3527 %dsdv32 = fpext half %dsdv to float3528 %dtdv32 = fpext half %dtdv to float3529 %s32 = fpext half %s to float3530 %t32 = fpext half %t to float3531 %res = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %dsdh32, float %dtdh32, float %dsdv32, float %dtdv32, float %s32, float %t32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3532 store <4 x float> %res, ptr addrspace(1) %out3533 ret void3534}3535 3536define amdgpu_kernel void @image_sample_a16_d_3d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, half %s, half %t, half %r) {3537; CHECK-LABEL: @image_sample_a16_d_3d(3538; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f16.v8i32.v4i32(i32 15, half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DRDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], half [[DRDV:%.*]], half [[S:%.*]], half [[T:%.*]], half [[R:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3539; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163540; CHECK-NEXT: ret void3541;3542 %dsdh32 = fpext half %dsdh to float3543 %dtdh32 = fpext half %dtdh to float3544 %drdh32 = fpext half %drdh to float3545 %dsdv32 = fpext half %dsdv to float3546 %dtdv32 = fpext half %dtdv to float3547 %drdv32 = fpext half %drdv to float3548 %s32 = fpext half %s to float3549 %t32 = fpext half %t to float3550 %r32 = fpext half %r to float3551 %res = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %dsdh32, float %dtdh32, float %drdh32, float %dsdv32, float %dtdv32, float %drdv32, float %s32, float %t32, float %r32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3552 store <4 x float> %res, ptr addrspace(1) %out3553 ret void3554}3555 3556define amdgpu_kernel void @image_sample_a16_c_d_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, half %s) {3557; CHECK-LABEL: @image_sample_a16_c_d_1d(3558; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f16.f16.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DSDV:%.*]], half [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3559; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163560; CHECK-NEXT: ret void3561;3562 %dsdh32 = fpext half %dsdh to float3563 %dsdv32 = fpext half %dsdv to float3564 %s32 = fpext half %s to float3565 %res = call <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %dsdh32, float %dsdv32, float %s32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3566 store <4 x float> %res, ptr addrspace(1) %out3567 ret void3568}3569 3570define amdgpu_kernel void @image_sample_a16_c_d_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {3571; CHECK-LABEL: @image_sample_a16_c_d_2d(3572; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f16.f16.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], half [[S:%.*]], half [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3573; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163574; CHECK-NEXT: ret void3575;3576 %dsdh32 = fpext half %dsdh to float3577 %dtdh32 = fpext half %dtdh to float3578 %dsdv32 = fpext half %dsdv to float3579 %dtdv32 = fpext half %dtdv to float3580 %s32 = fpext half %s to float3581 %t32 = fpext half %t to float3582 %res = call <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %dsdh32, float %dtdh32, float %dsdv32, float %dtdv32, float %s32, float %t32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3583 store <4 x float> %res, ptr addrspace(1) %out3584 ret void3585}3586 3587define amdgpu_kernel void @image_sample_a16_d_cl_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, half %s, half %clamp) {3588; CHECK-LABEL: @image_sample_a16_d_cl_1d(3589; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f16.f16.v8i32.v4i32(i32 15, half [[DSDH:%.*]], half [[DSDV:%.*]], half [[S:%.*]], half [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3590; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163591; CHECK-NEXT: ret void3592;3593 %dsdh32 = fpext half %dsdh to float3594 %dsdv32 = fpext half %dsdv to float3595 %s32 = fpext half %s to float3596 %clamp32 = fpext half %clamp to float3597 %res = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %dsdh32, float %dsdv32, float %s32, float %clamp32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3598 store <4 x float> %res, ptr addrspace(1) %out3599 ret void3600}3601 3602define amdgpu_kernel void @image_sample_a16_d_cl_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp) {3603; CHECK-LABEL: @image_sample_a16_d_cl_2d(3604; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f16.f16.v8i32.v4i32(i32 15, half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], half [[S:%.*]], half [[T:%.*]], half [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3605; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163606; CHECK-NEXT: ret void3607;3608 %dsdh32 = fpext half %dsdh to float3609 %dtdh32 = fpext half %dtdh to float3610 %dsdv32 = fpext half %dsdv to float3611 %dtdv32 = fpext half %dtdv to float3612 %s32 = fpext half %s to float3613 %t32 = fpext half %t to float3614 %clamp32 = fpext half %clamp to float3615 %res = call <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %dsdh32, float %dtdh32, float %dsdv32, float %dtdv32, float %s32, float %t32, float %clamp32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3616 store <4 x float> %res, ptr addrspace(1) %out3617 ret void3618}3619 3620define amdgpu_kernel void @image_sample_a16_c_d_cl_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, half %s, half %clamp) {3621; CHECK-LABEL: @image_sample_a16_c_d_cl_1d(3622; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f16.f16.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DSDV:%.*]], half [[S:%.*]], half [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3623; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163624; CHECK-NEXT: ret void3625;3626 %dsdh32 = fpext half %dsdh to float3627 %dsdv32 = fpext half %dsdv to float3628 %s32 = fpext half %s to float3629 %clamp32 = fpext half %clamp to float3630 %res = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %dsdh32, float %dsdv32, float %s32, float %clamp32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3631 store <4 x float> %res, ptr addrspace(1) %out3632 ret void3633}3634 3635define amdgpu_kernel void @image_sample_a16_c_d_cl_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp) {3636; CHECK-LABEL: @image_sample_a16_c_d_cl_2d(3637; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f16.f16.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], half [[S:%.*]], half [[T:%.*]], half [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3638; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163639; CHECK-NEXT: ret void3640;3641 %dsdh32 = fpext half %dsdh to float3642 %dtdh32 = fpext half %dtdh to float3643 %dsdv32 = fpext half %dsdv to float3644 %dtdv32 = fpext half %dtdv to float3645 %s32 = fpext half %s to float3646 %t32 = fpext half %t to float3647 %clamp32 = fpext half %clamp to float3648 %res = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %dsdh32, float %dtdh32, float %dsdv32, float %dtdv32, float %s32, float %t32, float %clamp32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3649 store <4 x float> %res, ptr addrspace(1) %out3650 ret void3651}3652 3653define amdgpu_kernel void @image_sample_a16_cd_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, half %s) {3654; CHECK-LABEL: @image_sample_a16_cd_1d(3655; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f16.f16.v8i32.v4i32(i32 15, half [[DSDH:%.*]], half [[DSDV:%.*]], half [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3656; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163657; CHECK-NEXT: ret void3658;3659 %dsdh32 = fpext half %dsdh to float3660 %dsdv32 = fpext half %dsdv to float3661 %s32 = fpext half %s to float3662 %res = call <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %dsdh32, float %dsdv32, float %s32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3663 store <4 x float> %res, ptr addrspace(1) %out3664 ret void3665}3666 3667define amdgpu_kernel void @image_sample_a16_cd_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {3668; CHECK-LABEL: @image_sample_a16_cd_2d(3669; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f16.f16.v8i32.v4i32(i32 15, half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], half [[S:%.*]], half [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3670; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163671; CHECK-NEXT: ret void3672;3673 %dsdh32 = fpext half %dsdh to float3674 %dtdh32 = fpext half %dtdh to float3675 %dsdv32 = fpext half %dsdv to float3676 %dtdv32 = fpext half %dtdv to float3677 %s32 = fpext half %s to float3678 %t32 = fpext half %t to float3679 %res = call <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %dsdh32, float %dtdh32, float %dsdv32, float %dtdv32, float %s32, float %t32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3680 store <4 x float> %res, ptr addrspace(1) %out3681 ret void3682}3683 3684define amdgpu_kernel void @image_sample_a16_c_cd_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, half %s) {3685; CHECK-LABEL: @image_sample_a16_c_cd_1d(3686; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f16.f16.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DSDV:%.*]], half [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3687; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163688; CHECK-NEXT: ret void3689;3690 %dsdh32 = fpext half %dsdh to float3691 %dsdv32 = fpext half %dsdv to float3692 %s32 = fpext half %s to float3693 %res = call <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %dsdh32, float %dsdv32, float %s32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3694 store <4 x float> %res, ptr addrspace(1) %out3695 ret void3696}3697 3698define amdgpu_kernel void @image_sample_a16_c_cd_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t) {3699; CHECK-LABEL: @image_sample_a16_c_cd_2d(3700; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f16.f16.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], half [[S:%.*]], half [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3701; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163702; CHECK-NEXT: ret void3703;3704 %dsdh32 = fpext half %dsdh to float3705 %dtdh32 = fpext half %dtdh to float3706 %dsdv32 = fpext half %dsdv to float3707 %dtdv32 = fpext half %dtdv to float3708 %s32 = fpext half %s to float3709 %t32 = fpext half %t to float3710 %res = call <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %dsdh32, float %dtdh32, float %dsdv32, float %dtdv32, float %s32, float %t32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3711 store <4 x float> %res, ptr addrspace(1) %out3712 ret void3713}3714 3715define amdgpu_kernel void @image_sample_a16_cd_cl_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, half %s, half %clamp) {3716; CHECK-LABEL: @image_sample_a16_cd_cl_1d(3717; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f16.f16.v8i32.v4i32(i32 15, half [[DSDH:%.*]], half [[DSDV:%.*]], half [[S:%.*]], half [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3718; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163719; CHECK-NEXT: ret void3720;3721 %dsdh32 = fpext half %dsdh to float3722 %dsdv32 = fpext half %dsdv to float3723 %s32 = fpext half %s to float3724 %clamp32 = fpext half %clamp to float3725 %res = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %dsdh32, float %dsdv32, float %s32, float %clamp32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3726 store <4 x float> %res, ptr addrspace(1) %out3727 ret void3728}3729 3730define amdgpu_kernel void @image_sample_a16_cd_cl_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp) {3731; CHECK-LABEL: @image_sample_a16_cd_cl_2d(3732; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f16.f16.v8i32.v4i32(i32 15, half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], half [[S:%.*]], half [[T:%.*]], half [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3733; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163734; CHECK-NEXT: ret void3735;3736 %dsdh32 = fpext half %dsdh to float3737 %dtdh32 = fpext half %dtdh to float3738 %dsdv32 = fpext half %dsdv to float3739 %dtdv32 = fpext half %dtdv to float3740 %s32 = fpext half %s to float3741 %t32 = fpext half %t to float3742 %clamp32 = fpext half %clamp to float3743 %res = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %dsdh32, float %dtdh32, float %dsdv32, float %dtdv32, float %s32, float %t32, float %clamp32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3744 store <4 x float> %res, ptr addrspace(1) %out3745 ret void3746}3747 3748define amdgpu_kernel void @image_sample_a16_c_cd_cl_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, half %s, half %clamp) {3749; CHECK-LABEL: @image_sample_a16_c_cd_cl_1d(3750; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f16.f16.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DSDV:%.*]], half [[S:%.*]], half [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3751; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163752; CHECK-NEXT: ret void3753;3754 %dsdh32 = fpext half %dsdh to float3755 %dsdv32 = fpext half %dsdv to float3756 %s32 = fpext half %s to float3757 %clamp32 = fpext half %clamp to float3758 %res = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %dsdh32, float %dsdv32, float %s32, float %clamp32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3759 store <4 x float> %res, ptr addrspace(1) %out3760 ret void3761}3762 3763define amdgpu_kernel void @image_sample_a16_c_cd_cl_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %clamp) {3764; CHECK-LABEL: @image_sample_a16_c_cd_cl_2d(3765; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f16.f16.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], half [[S:%.*]], half [[T:%.*]], half [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3766; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163767; CHECK-NEXT: ret void3768;3769 %dsdh32 = fpext half %dsdh to float3770 %dtdh32 = fpext half %dtdh to float3771 %dsdv32 = fpext half %dsdv to float3772 %dtdv32 = fpext half %dtdv to float3773 %s32 = fpext half %s to float3774 %t32 = fpext half %t to float3775 %clamp32 = fpext half %clamp to float3776 %res = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %dsdh32, float %dtdh32, float %dsdv32, float %dtdv32, float %s32, float %t32, float %clamp32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3777 store <4 x float> %res, ptr addrspace(1) %out3778 ret void3779}3780 3781define amdgpu_kernel void @image_sample_a16_l_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %lod) {3782; CHECK-LABEL: @image_sample_a16_l_1d(3783; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.l.1d.v4f32.f16.v8i32.v4i32(i32 15, half [[S:%.*]], half [[LOD:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3784; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163785; CHECK-NEXT: ret void3786;3787 %s32 = fpext half %s to float3788 %lod32 = fpext half %lod to float3789 %res = call <4 x float> @llvm.amdgcn.image.sample.l.1d.v4f32.f32.v8i32.v4i32(i32 15, float %s32, float %lod32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3790 store <4 x float> %res, ptr addrspace(1) %out3791 ret void3792}3793 3794define amdgpu_kernel void @image_sample_a16_l_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %lod) {3795; CHECK-LABEL: @image_sample_a16_l_2d(3796; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.l.2d.v4f32.f16.v8i32.v4i32(i32 15, half [[S:%.*]], half [[T:%.*]], half [[LOD:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3797; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163798; CHECK-NEXT: ret void3799;3800 %s32 = fpext half %s to float3801 %t32 = fpext half %t to float3802 %lod32 = fpext half %lod to float3803 %res = call <4 x float> @llvm.amdgcn.image.sample.l.2d.v4f32.f32.v8i32.v4i32(i32 15, float %s32, float %t32, float %lod32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3804 store <4 x float> %res, ptr addrspace(1) %out3805 ret void3806}3807 3808define amdgpu_kernel void @image_sample_a16_c_l_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %lod) {3809; CHECK-LABEL: @image_sample_a16_c_l_1d(3810; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.l.1d.v4f32.f16.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], half [[S:%.*]], half [[LOD:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3811; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163812; CHECK-NEXT: ret void3813;3814 %s32 = fpext half %s to float3815 %lod32 = fpext half %lod to float3816 %res = call <4 x float> @llvm.amdgcn.image.sample.c.l.1d.v4f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %s32, float %lod32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3817 store <4 x float> %res, ptr addrspace(1) %out3818 ret void3819}3820 3821define amdgpu_kernel void @image_sample_a16_c_l_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t, half %lod) {3822; CHECK-LABEL: @image_sample_a16_c_l_2d(3823; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.l.2d.v4f32.f16.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], half [[S:%.*]], half [[T:%.*]], half [[LOD:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3824; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163825; CHECK-NEXT: ret void3826;3827 %s32 = fpext half %s to float3828 %t32 = fpext half %t to float3829 %lod32 = fpext half %lod to float3830 %res = call <4 x float> @llvm.amdgcn.image.sample.c.l.2d.v4f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %s32, float %t32, float %lod32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3831 store <4 x float> %res, ptr addrspace(1) %out3832 ret void3833}3834 3835define amdgpu_kernel void @image_sample_a16_lz_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s) {3836; CHECK-LABEL: @image_sample_a16_lz_1d(3837; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.lz.1d.v4f32.f16.v8i32.v4i32(i32 15, half [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3838; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163839; CHECK-NEXT: ret void3840;3841 %s32 = fpext half %s to float3842 %res = call <4 x float> @llvm.amdgcn.image.sample.lz.1d.v4f32.f32.v8i32.v4i32(i32 15, float %s32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3843 store <4 x float> %res, ptr addrspace(1) %out3844 ret void3845}3846 3847define amdgpu_kernel void @image_sample_a16_lz_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t) {3848; CHECK-LABEL: @image_sample_a16_lz_2d(3849; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f16.v8i32.v4i32(i32 15, half [[S:%.*]], half [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3850; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163851; CHECK-NEXT: ret void3852;3853 %s32 = fpext half %s to float3854 %t32 = fpext half %t to float3855 %res = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32.v8i32.v4i32(i32 15, float %s32, float %t32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3856 store <4 x float> %res, ptr addrspace(1) %out3857 ret void3858}3859 3860define amdgpu_kernel void @image_sample_a16_c_lz_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s) {3861; CHECK-LABEL: @image_sample_a16_c_lz_1d(3862; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.lz.1d.v4f32.f16.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], half [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3863; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163864; CHECK-NEXT: ret void3865;3866 %s32 = fpext half %s to float3867 %res = call <4 x float> @llvm.amdgcn.image.sample.c.lz.1d.v4f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %s32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3868 store <4 x float> %res, ptr addrspace(1) %out3869 ret void3870}3871 3872define amdgpu_kernel void @image_sample_a16_c_lz_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %s, half %t) {3873; CHECK-LABEL: @image_sample_a16_c_lz_2d(3874; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.lz.2d.v4f32.f16.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], half [[S:%.*]], half [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3875; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163876; CHECK-NEXT: ret void3877;3878 %s32 = fpext half %s to float3879 %t32 = fpext half %t to float3880 %res = call <4 x float> @llvm.amdgcn.image.sample.c.lz.2d.v4f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %s32, float %t32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3881 store <4 x float> %res, ptr addrspace(1) %out3882 ret void3883}3884 3885define amdgpu_kernel void @image_sample_a16_c_d_o_2darray_V1(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %slice) {3886; CHECK-LABEL: @image_sample_a16_c_d_o_2darray_V1(3887; CHECK-NEXT: [[RES:%.*]] = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f16.f16.v8i32.v4i32(i32 4, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], half [[S:%.*]], half [[T:%.*]], half [[SLICE:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3888; CHECK-NEXT: store float [[RES]], ptr addrspace(1) [[OUT:%.*]], align 43889; CHECK-NEXT: ret void3890;3891 %dsdh32 = fpext half %dsdh to float3892 %dtdh32 = fpext half %dtdh to float3893 %dsdv32 = fpext half %dsdv to float3894 %dtdv32 = fpext half %dtdv to float3895 %s32 = fpext half %s to float3896 %t32 = fpext half %t to float3897 %slice32 = fpext half %slice to float3898 %res = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f32.f32.v8i32.v4i32(i32 4, i32 %offset, float %zcompare, float %dsdh32, float %dtdh32, float %dsdv32, float %dtdv32, float %s32, float %t32, float %slice32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3899 store float %res, ptr addrspace(1) %out3900 ret void3901}3902 3903define amdgpu_kernel void @image_sample_a16_c_d_o_2darray_V2(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %t, half %slice) {3904; CHECK-LABEL: @image_sample_a16_c_d_o_2darray_V2(3905; CHECK-NEXT: [[RES:%.*]] = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f16.v8i32.v4i32(i32 6, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], half [[S:%.*]], half [[T:%.*]], half [[SLICE:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3906; CHECK-NEXT: store <2 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 83907; CHECK-NEXT: ret void3908;3909 %dsdh32 = fpext half %dsdh to float3910 %dtdh32 = fpext half %dtdh to float3911 %dsdv32 = fpext half %dsdv to float3912 %dtdv32 = fpext half %dtdv to float3913 %s32 = fpext half %s to float3914 %t32 = fpext half %t to float3915 %slice32 = fpext half %slice to float3916 %res = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f32.f32.v8i32.v4i32(i32 6, i32 %offset, float %zcompare, float %dsdh32, float %dtdh32, float %dsdv32, float %dtdv32, float %s32, float %t32, float %slice32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3917 store <2 x float> %res, ptr addrspace(1) %out3918 ret void3919}3920 3921define amdgpu_kernel void @image_sample_a16_c_d_o_2darray_const(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %slice) {3922; CHECK-LABEL: @image_sample_a16_c_d_o_2darray_const(3923; CHECK-NEXT: [[RES:%.*]] = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f16.v8i32.v4i32(i32 6, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], half [[S:%.*]], half 0xH3400, half [[SLICE:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3924; CHECK-NEXT: store <2 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 83925; CHECK-NEXT: ret void3926;3927 %dsdh32 = fpext half %dsdh to float3928 %dtdh32 = fpext half %dtdh to float3929 %dsdv32 = fpext half %dsdv to float3930 %dtdv32 = fpext half %dtdv to float3931 %s32 = fpext half %s to float3932 %slice32 = fpext half %slice to float3933 %res = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f32.f32.v8i32.v4i32(i32 6, i32 %offset, float %zcompare, float %dsdh32, float %dtdh32, float %dsdv32, float %dtdv32, float %s32, float 0.25, float %slice32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3934 store <2 x float> %res, ptr addrspace(1) %out3935 ret void3936}3937 3938define amdgpu_kernel void @image_sample_a16_c_d_o_2darray_const_noopt(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %slice) {3939; CHECK-LABEL: @image_sample_a16_c_d_o_2darray_const_noopt(3940; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float3941; CHECK-NEXT: [[SLICE32:%.*]] = fpext half [[SLICE:%.*]] to float3942; CHECK-NEXT: [[RES:%.*]] = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32.v8i32.v4i32(i32 6, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], float [[S32]], float 1.000000e+10, float [[SLICE32]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)3943; CHECK-NEXT: store <2 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 83944; CHECK-NEXT: ret void3945;3946 %dsdh32 = fpext half %dsdh to float3947 %dtdh32 = fpext half %dtdh to float3948 %dsdv32 = fpext half %dsdv to float3949 %dtdv32 = fpext half %dtdv to float3950 %s32 = fpext half %s to float3951 %slice32 = fpext half %slice to float3952 %res = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f32.f32.v8i32.v4i32(i32 6, i32 %offset, float %zcompare, float %dsdh32, float %dtdh32, float %dsdv32, float %dtdv32, float %s32, float 1.0e+10, float %slice32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)3953 store <2 x float> %res, ptr addrspace(1) %out3954 ret void3955}3956 3957define amdgpu_kernel void @image_load_a16_mip_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, i16 %s) {3958; CHECK-LABEL: @image_load_a16_mip_1d(3959; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16.v8i32(i32 15, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)3960; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163961; CHECK-NEXT: ret void3962;3963 %s32 = zext i16 %s to i323964 %res = call <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i32.v8i32(i32 15, i32 %s32, i32 0, <8 x i32> %rsrc, i32 0, i32 0)3965 store <4 x float> %res, ptr addrspace(1) %out3966 ret void3967}3968 3969define amdgpu_kernel void @image_load_a16_mip_1d_noopt(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, i16 %s) {3970; CHECK-LABEL: @image_load_a16_mip_1d_noopt(3971; CHECK-NEXT: [[S32:%.*]] = sext i16 [[S:%.*]] to i323972; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32.v8i32(i32 15, i32 [[S32]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)3973; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163974; CHECK-NEXT: ret void3975;3976 %s32 = sext i16 %s to i323977 %res = call <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i32.v8i32(i32 15, i32 %s32, i32 0, <8 x i32> %rsrc, i32 0, i32 0)3978 store <4 x float> %res, ptr addrspace(1) %out3979 ret void3980}3981 3982define amdgpu_kernel void @image_load_a16_mip_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, i16 %s, i16 %t) {3983; CHECK-LABEL: @image_load_a16_mip_2d(3984; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16.v8i32(i32 15, i16 [[S:%.*]], i16 [[T:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)3985; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163986; CHECK-NEXT: ret void3987;3988 %s32 = zext i16 %s to i323989 %t32 = zext i16 %t to i323990 %res = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32.v8i32(i32 15, i32 %s32, i32 %t32, i32 0, <8 x i32> %rsrc, i32 0, i32 0)3991 store <4 x float> %res, ptr addrspace(1) %out3992 ret void3993}3994 3995define amdgpu_kernel void @image_load_a16_mip_2d_const(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, i16 %s) {3996; CHECK-LABEL: @image_load_a16_mip_2d_const(3997; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16.v8i32(i32 15, i16 [[S:%.*]], i16 -1, <8 x i32> [[RSRC:%.*]], i32 0, i32 0)3998; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 163999; CHECK-NEXT: ret void4000;4001 %s32 = zext i16 %s to i324002 %res = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32.v8i32(i32 15, i32 %s32, i32 65535, i32 0, <8 x i32> %rsrc, i32 0, i32 0)4003 store <4 x float> %res, ptr addrspace(1) %out4004 ret void4005}4006 4007define amdgpu_kernel void @image_load_a16_mip_2d_const_noopt(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, i16 %s) {4008; CHECK-LABEL: @image_load_a16_mip_2d_const_noopt(4009; CHECK-NEXT: [[S32:%.*]] = zext i16 [[S:%.*]] to i324010; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32.v8i32(i32 15, i32 [[S32]], i32 65536, <8 x i32> [[RSRC:%.*]], i32 0, i32 0)4011; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164012; CHECK-NEXT: ret void4013;4014 %s32 = zext i16 %s to i324015 %res = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32.v8i32(i32 15, i32 %s32, i32 65536, i32 0, <8 x i32> %rsrc, i32 0, i32 0)4016 store <4 x float> %res, ptr addrspace(1) %out4017 ret void4018}4019 4020; --------------------------------------------------------------------4021; llvm.amdgcn.image.sample g164022; --------------------------------------------------------------------4023 4024define amdgpu_kernel void @image_sample_g16_d_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {4025; CHECK-LABEL: @image_sample_g16_d_1d(4026; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f16.f32.v8i32.v4i32(i32 15, half [[DSDH:%.*]], half [[DSDV:%.*]], float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4027; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164028; CHECK-NEXT: ret void4029;4030 %dsdh32 = fpext half %dsdh to float4031 %dsdv32 = fpext half %dsdv to float4032 %res = call <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %dsdh32, float %dsdv32, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4033 store <4 x float> %res, ptr addrspace(1) %out4034 ret void4035}4036 4037define amdgpu_kernel void @image_sample_g16_d_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {4038; CHECK-LABEL: @image_sample_g16_d_2d(4039; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f16.f32.v8i32.v4i32(i32 15, half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4040; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164041; CHECK-NEXT: ret void4042;4043 %dsdh32 = fpext half %dsdh to float4044 %dtdh32 = fpext half %dtdh to float4045 %dsdv32 = fpext half %dsdv to float4046 %dtdv32 = fpext half %dtdv to float4047 %res = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %dsdh32, float %dtdh32, float %dsdv32, float %dtdv32, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4048 store <4 x float> %res, ptr addrspace(1) %out4049 ret void4050}4051 4052define amdgpu_kernel void @image_sample_g16_d_3d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %drdh, half %dsdv, half %dtdv, half %drdv, float %s, float %t, float %r) {4053; CHECK-LABEL: @image_sample_g16_d_3d(4054; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f16.f32.v8i32.v4i32(i32 15, half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DRDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], half [[DRDV:%.*]], float [[S:%.*]], float [[T:%.*]], float [[R:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4055; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164056; CHECK-NEXT: ret void4057;4058 %dsdh32 = fpext half %dsdh to float4059 %dtdh32 = fpext half %dtdh to float4060 %drdh32 = fpext half %drdh to float4061 %dsdv32 = fpext half %dsdv to float4062 %dtdv32 = fpext half %dtdv to float4063 %drdv32 = fpext half %drdv to float4064 %res = call <4 x float> @llvm.amdgcn.image.sample.d.3d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %dsdh32, float %dtdh32, float %drdh32, float %dsdv32, float %dtdv32, float %drdv32, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4065 store <4 x float> %res, ptr addrspace(1) %out4066 ret void4067}4068 4069define amdgpu_kernel void @image_sample_g16_c_d_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s) {4070; CHECK-LABEL: @image_sample_g16_c_d_1d(4071; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f16.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DSDV:%.*]], float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4072; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164073; CHECK-NEXT: ret void4074;4075 %dsdh32 = fpext half %dsdh to float4076 %dsdv32 = fpext half %dsdv to float4077 %res = call <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %dsdh32, float %dsdv32, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4078 store <4 x float> %res, ptr addrspace(1) %out4079 ret void4080}4081 4082define amdgpu_kernel void @image_sample_g16_c_d_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {4083; CHECK-LABEL: @image_sample_g16_c_d_2d(4084; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f16.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4085; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164086; CHECK-NEXT: ret void4087;4088 %dsdh32 = fpext half %dsdh to float4089 %dtdh32 = fpext half %dtdh to float4090 %dsdv32 = fpext half %dsdv to float4091 %dtdv32 = fpext half %dtdv to float4092 %res = call <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %dsdh32, float %dtdh32, float %dsdv32, float %dtdv32, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4093 store <4 x float> %res, ptr addrspace(1) %out4094 ret void4095}4096 4097define amdgpu_kernel void @image_sample_g16_d_cl_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s, float %clamp) {4098; CHECK-LABEL: @image_sample_g16_d_cl_1d(4099; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f16.f32.v8i32.v4i32(i32 15, half [[DSDH:%.*]], half [[DSDV:%.*]], float [[S:%.*]], float [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4100; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164101; CHECK-NEXT: ret void4102;4103 %dsdh32 = fpext half %dsdh to float4104 %dsdv32 = fpext half %dsdv to float4105 %res = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %dsdh32, float %dsdv32, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4106 store <4 x float> %res, ptr addrspace(1) %out4107 ret void4108}4109 4110define amdgpu_kernel void @image_sample_g16_d_cl_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {4111; CHECK-LABEL: @image_sample_g16_d_cl_2d(4112; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f16.f32.v8i32.v4i32(i32 15, half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], float [[S:%.*]], float [[T:%.*]], float [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4113; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164114; CHECK-NEXT: ret void4115;4116 %dsdh32 = fpext half %dsdh to float4117 %dtdh32 = fpext half %dtdh to float4118 %dsdv32 = fpext half %dsdv to float4119 %dtdv32 = fpext half %dtdv to float4120 %res = call <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %dsdh32, float %dtdh32, float %dsdv32, float %dtdv32, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4121 store <4 x float> %res, ptr addrspace(1) %out4122 ret void4123}4124 4125define amdgpu_kernel void @image_sample_g16_c_d_cl_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) {4126; CHECK-LABEL: @image_sample_g16_c_d_cl_1d(4127; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f16.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DSDV:%.*]], float [[S:%.*]], float [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4128; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164129; CHECK-NEXT: ret void4130;4131 %dsdh32 = fpext half %dsdh to float4132 %dsdv32 = fpext half %dsdv to float4133 %res = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %dsdh32, float %dsdv32, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4134 store <4 x float> %res, ptr addrspace(1) %out4135 ret void4136}4137 4138define amdgpu_kernel void @image_sample_g16_c_d_cl_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {4139; CHECK-LABEL: @image_sample_g16_c_d_cl_2d(4140; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f16.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], float [[S:%.*]], float [[T:%.*]], float [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4141; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164142; CHECK-NEXT: ret void4143;4144 %dsdh32 = fpext half %dsdh to float4145 %dtdh32 = fpext half %dtdh to float4146 %dsdv32 = fpext half %dsdv to float4147 %dtdv32 = fpext half %dtdv to float4148 %res = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %dsdh32, float %dtdh32, float %dsdv32, float %dtdv32, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4149 store <4 x float> %res, ptr addrspace(1) %out4150 ret void4151}4152 4153define amdgpu_kernel void @image_sample_g16_cd_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {4154; CHECK-LABEL: @image_sample_g16_cd_1d(4155; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f16.f32.v8i32.v4i32(i32 15, half [[DSDH:%.*]], half [[DSDV:%.*]], float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4156; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164157; CHECK-NEXT: ret void4158;4159 %dsdh32 = fpext half %dsdh to float4160 %dsdv32 = fpext half %dsdv to float4161 %res = call <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %dsdh32, float %dsdv32, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4162 store <4 x float> %res, ptr addrspace(1) %out4163 ret void4164}4165 4166define amdgpu_kernel void @image_sample_g16_cd_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {4167; CHECK-LABEL: @image_sample_g16_cd_2d(4168; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f16.f32.v8i32.v4i32(i32 15, half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4169; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164170; CHECK-NEXT: ret void4171;4172 %dsdh32 = fpext half %dsdh to float4173 %dtdh32 = fpext half %dtdh to float4174 %dsdv32 = fpext half %dsdv to float4175 %dtdv32 = fpext half %dtdv to float4176 %res = call <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %dsdh32, float %dtdh32, float %dsdv32, float %dtdv32, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4177 store <4 x float> %res, ptr addrspace(1) %out4178 ret void4179}4180 4181define amdgpu_kernel void @image_sample_g16_c_cd_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s) {4182; CHECK-LABEL: @image_sample_g16_c_cd_1d(4183; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f16.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DSDV:%.*]], float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4184; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164185; CHECK-NEXT: ret void4186;4187 %dsdh32 = fpext half %dsdh to float4188 %dsdv32 = fpext half %dsdv to float4189 %res = call <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %dsdh32, float %dsdv32, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4190 store <4 x float> %res, ptr addrspace(1) %out4191 ret void4192}4193 4194define amdgpu_kernel void @image_sample_g16_c_cd_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t) {4195; CHECK-LABEL: @image_sample_g16_c_cd_2d(4196; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f16.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4197; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164198; CHECK-NEXT: ret void4199;4200 %dsdh32 = fpext half %dsdh to float4201 %dtdh32 = fpext half %dtdh to float4202 %dsdv32 = fpext half %dsdv to float4203 %dtdv32 = fpext half %dtdv to float4204 %res = call <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %dsdh32, float %dtdh32, float %dsdv32, float %dtdv32, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4205 store <4 x float> %res, ptr addrspace(1) %out4206 ret void4207}4208 4209define amdgpu_kernel void @image_sample_g16_cd_cl_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s, float %clamp) {4210; CHECK-LABEL: @image_sample_g16_cd_cl_1d(4211; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f16.f32.v8i32.v4i32(i32 15, half [[DSDH:%.*]], half [[DSDV:%.*]], float [[S:%.*]], float [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4212; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164213; CHECK-NEXT: ret void4214;4215 %dsdh32 = fpext half %dsdh to float4216 %dsdv32 = fpext half %dsdv to float4217 %res = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %dsdh32, float %dsdv32, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4218 store <4 x float> %res, ptr addrspace(1) %out4219 ret void4220}4221 4222define amdgpu_kernel void @image_sample_g16_cd_cl_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {4223; CHECK-LABEL: @image_sample_g16_cd_cl_2d(4224; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f16.f32.v8i32.v4i32(i32 15, half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], float [[S:%.*]], float [[T:%.*]], float [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4225; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164226; CHECK-NEXT: ret void4227;4228 %dsdh32 = fpext half %dsdh to float4229 %dtdh32 = fpext half %dtdh to float4230 %dsdv32 = fpext half %dsdv to float4231 %dtdv32 = fpext half %dtdv to float4232 %res = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %dsdh32, float %dtdh32, float %dsdv32, float %dtdv32, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4233 store <4 x float> %res, ptr addrspace(1) %out4234 ret void4235}4236 4237define amdgpu_kernel void @image_sample_g16_c_cd_cl_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dsdv, float %s, float %clamp) {4238; CHECK-LABEL: @image_sample_g16_c_cd_cl_1d(4239; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f16.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DSDV:%.*]], float [[S:%.*]], float [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4240; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164241; CHECK-NEXT: ret void4242;4243 %dsdh32 = fpext half %dsdh to float4244 %dsdv32 = fpext half %dsdv to float4245 %res = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %dsdh32, float %dsdv32, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4246 store <4 x float> %res, ptr addrspace(1) %out4247 ret void4248}4249 4250define amdgpu_kernel void @image_sample_g16_c_cd_cl_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %clamp) {4251; CHECK-LABEL: @image_sample_g16_c_cd_cl_2d(4252; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f16.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], float [[S:%.*]], float [[T:%.*]], float [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4253; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164254; CHECK-NEXT: ret void4255;4256 %dsdh32 = fpext half %dsdh to float4257 %dtdh32 = fpext half %dtdh to float4258 %dsdv32 = fpext half %dsdv to float4259 %dtdv32 = fpext half %dtdv to float4260 %res = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %dsdh32, float %dtdh32, float %dsdv32, float %dtdv32, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4261 store <4 x float> %res, ptr addrspace(1) %out4262 ret void4263}4264 4265define amdgpu_kernel void @image_sample_g16_c_d_o_2darray_V1(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice) {4266; CHECK-LABEL: @image_sample_g16_c_d_o_2darray_V1(4267; CHECK-NEXT: [[RES:%.*]] = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f16.f32.v8i32.v4i32(i32 4, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], float [[S:%.*]], float [[T:%.*]], float [[SLICE:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4268; CHECK-NEXT: store float [[RES]], ptr addrspace(1) [[OUT:%.*]], align 44269; CHECK-NEXT: ret void4270;4271 %dsdh32 = fpext half %dsdh to float4272 %dtdh32 = fpext half %dtdh to float4273 %dsdv32 = fpext half %dsdv to float4274 %dtdv32 = fpext half %dtdv to float4275 %res = call float @llvm.amdgcn.image.sample.c.d.o.2darray.f32.f32.f32.v8i32.v4i32(i32 4, i32 %offset, float %zcompare, float %dsdh32, float %dtdh32, float %dsdv32, float %dtdv32, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4276 store float %res, ptr addrspace(1) %out4277 ret void4278}4279 4280define amdgpu_kernel void @image_sample_g16_c_d_o_2darray_V2(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, float %s, float %t, float %slice) {4281; CHECK-LABEL: @image_sample_g16_c_d_o_2darray_V2(4282; CHECK-NEXT: [[RES:%.*]] = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32.v8i32.v4i32(i32 6, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], float [[S:%.*]], float [[T:%.*]], float [[SLICE:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4283; CHECK-NEXT: store <2 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 84284; CHECK-NEXT: ret void4285;4286 %dsdh32 = fpext half %dsdh to float4287 %dtdh32 = fpext half %dtdh to float4288 %dsdv32 = fpext half %dsdv to float4289 %dtdv32 = fpext half %dtdv to float4290 %res = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f32.f32.v8i32.v4i32(i32 6, i32 %offset, float %zcompare, float %dsdh32, float %dtdh32, float %dsdv32, float %dtdv32, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4291 store <2 x float> %res, ptr addrspace(1) %out4292 ret void4293}4294 4295; --------------------------------------------------------------------4296; llvm.amdgcn.image.sample a16 preserve fast-math flags4297; --------------------------------------------------------------------4298 4299define amdgpu_kernel void @image_sample_a16_1d_nnan(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s) {4300; CHECK-LABEL: @image_sample_a16_1d_nnan(4301; CHECK-NEXT: [[RES:%.*]] = call nnan <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f16.v8i32.v4i32(i32 15, half [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4302; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164303; CHECK-NEXT: ret void4304;4305 %s32 = fpext half %s to float4306 %res = call nnan <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32.v8i32.v4i32(i32 15, float %s32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4307 store <4 x float> %res, ptr addrspace(1) %out4308 ret void4309}4310 4311define amdgpu_kernel void @image_sample_a16_1d_nnan_ninf_nsz(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s) {4312; CHECK-LABEL: @image_sample_a16_1d_nnan_ninf_nsz(4313; CHECK-NEXT: [[RES:%.*]] = call nnan ninf nsz <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f16.v8i32.v4i32(i32 15, half [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4314; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164315; CHECK-NEXT: ret void4316;4317 %s32 = fpext half %s to float4318 %res = call nnan ninf nsz <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32.v8i32.v4i32(i32 15, float %s32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4319 store <4 x float> %res, ptr addrspace(1) %out4320 ret void4321}4322 4323define amdgpu_kernel void @image_sample_a16_1d_fast(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s) {4324; CHECK-LABEL: @image_sample_a16_1d_fast(4325; CHECK-NEXT: [[RES:%.*]] = call fast <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f16.v8i32.v4i32(i32 15, half [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4326; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164327; CHECK-NEXT: ret void4328;4329 %s32 = fpext half %s to float4330 %res = call fast <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32.v8i32.v4i32(i32 15, float %s32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4331 store <4 x float> %res, ptr addrspace(1) %out4332 ret void4333}4334 4335define amdgpu_kernel void @image_sample_a16_2d_nnan(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t) {4336; CHECK-LABEL: @image_sample_a16_2d_nnan(4337; CHECK-NEXT: [[RES:%.*]] = call nnan <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f16.v8i32.v4i32(i32 15, half [[S:%.*]], half [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4338; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164339; CHECK-NEXT: ret void4340;4341 %s32 = fpext half %s to float4342 %t32 = fpext half %t to float4343 %res = call nnan <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32.v8i32.v4i32(i32 15, float %s32, float %t32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4344 store <4 x float> %res, ptr addrspace(1) %out4345 ret void4346}4347 4348define amdgpu_kernel void @image_sample_a16_3d_nnan(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %r) {4349; CHECK-LABEL: @image_sample_a16_3d_nnan(4350; CHECK-NEXT: [[RES:%.*]] = call nnan <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f16.v8i32.v4i32(i32 15, half [[S:%.*]], half [[T:%.*]], half [[R:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4351; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164352; CHECK-NEXT: ret void4353;4354 %s32 = fpext half %s to float4355 %t32 = fpext half %t to float4356 %r32 = fpext half %r to float4357 %res = call nnan <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32.v8i32.v4i32(i32 15, float %s32, float %t32, float %r32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4358 store <4 x float> %res, ptr addrspace(1) %out4359 ret void4360}4361 4362define amdgpu_kernel void @image_sample_a16_cube_nnan(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %face) {4363;4364; CHECK-LABEL: @image_sample_a16_cube_nnan(4365; CHECK-NEXT: [[RES:%.*]] = call nnan <4 x float> @llvm.amdgcn.image.sample.cube.v4f32.f16.v8i32.v4i32(i32 15, half [[S:%.*]], half [[T:%.*]], half [[FACE:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4366; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164367; CHECK-NEXT: ret void4368;4369 %s32 = fpext half %s to float4370 %t32 = fpext half %t to float4371 %face32 = fpext half %face to float4372 %res = call nnan <4 x float> @llvm.amdgcn.image.sample.cube.v4f32.f32.v8i32.v4i32(i32 15, float %s32, float %t32, float %face32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4373 store <4 x float> %res, ptr addrspace(1) %out4374 ret void4375}4376 4377define amdgpu_kernel void @image_sample_a16_1darray_nnan(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %slice) {4378; CHECK-LABEL: @image_sample_a16_1darray_nnan(4379; CHECK-NEXT: [[RES:%.*]] = call nnan <4 x float> @llvm.amdgcn.image.sample.1darray.v4f32.f16.v8i32.v4i32(i32 15, half [[S:%.*]], half [[SLICE:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4380; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164381; CHECK-NEXT: ret void4382;4383 %s32 = fpext half %s to float4384 %slice32 = fpext half %slice to float4385 %res = call nnan <4 x float> @llvm.amdgcn.image.sample.1darray.v4f32.f32.v8i32.v4i32(i32 15, float %s32, float %slice32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4386 store <4 x float> %res, ptr addrspace(1) %out4387 ret void4388}4389 4390define amdgpu_kernel void @image_sample_a16_2darray_nnan(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t, half %slice) {4391; CHECK-LABEL: @image_sample_a16_2darray_nnan(4392; CHECK-NEXT: [[RES:%.*]] = call nnan <4 x float> @llvm.amdgcn.image.sample.2darray.v4f32.f16.v8i32.v4i32(i32 15, half [[S:%.*]], half [[T:%.*]], half [[SLICE:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4393; CHECK-NEXT: store <4 x float> [[RES]], ptr addrspace(1) [[OUT:%.*]], align 164394; CHECK-NEXT: ret void4395;4396 %s32 = fpext half %s to float4397 %t32 = fpext half %t to float4398 %slice32 = fpext half %slice to float4399 %res = call nnan <4 x float> @llvm.amdgcn.image.sample.2darray.v4f32.f32.v8i32.v4i32(i32 15, float %s32, float %t32, float %slice32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4400 store <4 x float> %res, ptr addrspace(1) %out4401 ret void4402}4403 4404; --------------------------------------------------------------------4405; llvm.amdgcn.image.sample l to lz4406; --------------------------------------------------------------------4407 4408declare <4 x float> @llvm.amdgcn.image.sample.l.o.1d.v4f32.f32.v8i32.v4i32(i32, i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #14409declare <4 x float> @llvm.amdgcn.image.sample.l.o.2d.v4f32.f32.v8i32.v4i32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #14410declare <4 x float> @llvm.amdgcn.image.sample.c.l.o.1d.v4f32.f32.v8i32.v4i32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #14411declare <4 x float> @llvm.amdgcn.image.sample.c.l.o.2d.v4f32.f32.v8i32.v4i32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #14412 4413declare <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f32.v8i32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #14414declare <4 x float> @llvm.amdgcn.image.gather4.c.l.2d.v4f32.f32.v8i32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #14415declare <4 x float> @llvm.amdgcn.image.gather4.l.o.2d.v4f32.f32.v8i32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #14416declare <4 x float> @llvm.amdgcn.image.gather4.c.l.o.2d.v4f32.f32.v8i32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #14417declare <4 x float> @llvm.amdgcn.image.gather4.c.l.o.2darray.v4f32.f32.v8i32(i32, i32, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #14418 4419define amdgpu_kernel void @sample_l_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %lod) {4420; CHECK-LABEL: @sample_l_1d(4421; CHECK-NEXT: main_body:4422; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.lz.1d.v4f32.f32.v8i32.v4i32(i32 15, float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4423; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164424; CHECK-NEXT: ret void4425;4426main_body:4427 %v = call <4 x float> @llvm.amdgcn.image.sample.l.1d.v4f32.f32.v8i32.v4i32(i32 15, float %s, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4428 store <4 x float> %v, ptr addrspace(1) %out4429 ret void4430}4431 4432define amdgpu_kernel void @sample_l_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %lod) {4433; CHECK-LABEL: @sample_l_2d(4434; CHECK-NEXT: main_body:4435; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32.v8i32.v4i32(i32 15, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4436; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164437; CHECK-NEXT: ret void4438;4439main_body:4440 %v = call <4 x float> @llvm.amdgcn.image.sample.l.2d.v4f32.f32.v8i32.v4i32(i32 15, float %s, float %t, float -0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4441 store <4 x float> %v, ptr addrspace(1) %out4442 ret void4443}4444 4445define amdgpu_kernel void @sample_c_l_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %lod) {4446; CHECK-LABEL: @sample_c_l_1d(4447; CHECK-NEXT: main_body:4448; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.lz.1d.v4f32.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4449; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164450; CHECK-NEXT: ret void4451;4452main_body:4453 %v = call <4 x float> @llvm.amdgcn.image.sample.c.l.1d.v4f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %s, float -2.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4454 store <4 x float> %v, ptr addrspace(1) %out4455 ret void4456}4457 4458define amdgpu_kernel void @sample_c_l_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t, float %lod) {4459; CHECK-LABEL: @sample_c_l_2d(4460; CHECK-NEXT: main_body:4461; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.lz.2d.v4f32.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4462; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164463; CHECK-NEXT: ret void4464;4465main_body:4466 %v = call <4 x float> @llvm.amdgcn.image.sample.c.l.2d.v4f32.f32.v8i32.v4i32(i32 15, float %zcompare, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4467 store <4 x float> %v, ptr addrspace(1) %out4468 ret void4469}4470 4471define amdgpu_kernel void @sample_l_o_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %lod) {4472; CHECK-LABEL: @sample_l_o_1d(4473; CHECK-NEXT: main_body:4474; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.lz.o.1d.v4f32.f32.v8i32.v4i32(i32 15, i32 [[OFFSET:%.*]], float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4475; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164476; CHECK-NEXT: ret void4477;4478main_body:4479 %v = call <4 x float> @llvm.amdgcn.image.sample.l.o.1d.v4f32.f32.v8i32.v4i32(i32 15, i32 %offset, float %s, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4480 store <4 x float> %v, ptr addrspace(1) %out4481 ret void4482}4483 4484define amdgpu_kernel void @sample_l_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %t, float %lod) {4485; CHECK-LABEL: @sample_l_o_2d(4486; CHECK-NEXT: main_body:4487; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.lz.o.2d.v4f32.f32.v8i32.v4i32(i32 15, i32 [[OFFSET:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4488; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164489; CHECK-NEXT: ret void4490;4491main_body:4492 %v = call <4 x float> @llvm.amdgcn.image.sample.l.o.2d.v4f32.f32.v8i32.v4i32(i32 15, i32 %offset, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4493 store <4 x float> %v, ptr addrspace(1) %out4494 ret void4495}4496 4497define amdgpu_kernel void @sample_c_l_o_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %lod) {4498; CHECK-LABEL: @sample_c_l_o_1d(4499; CHECK-NEXT: main_body:4500; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.lz.o.1d.v4f32.f32.v8i32.v4i32(i32 15, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4501; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164502; CHECK-NEXT: ret void4503;4504main_body:4505 %v = call <4 x float> @llvm.amdgcn.image.sample.c.l.o.1d.v4f32.f32.v8i32.v4i32(i32 15, i32 %offset, float %zcompare, float %s, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4506 store <4 x float> %v, ptr addrspace(1) %out4507 ret void4508}4509 4510define amdgpu_kernel void @sample_c_l_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %t, float %lod) {4511; CHECK-LABEL: @sample_c_l_o_2d(4512; CHECK-NEXT: main_body:4513; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.lz.o.2d.v4f32.f32.v8i32.v4i32(i32 15, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4514; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164515; CHECK-NEXT: ret void4516;4517main_body:4518 %v = call <4 x float> @llvm.amdgcn.image.sample.c.l.o.2d.v4f32.f32.v8i32.v4i32(i32 15, i32 %offset, float %zcompare, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4519 store <4 x float> %v, ptr addrspace(1) %out4520 ret void4521}4522 4523define amdgpu_kernel void @gather4_l_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %lod) {4524; CHECK-LABEL: @gather4_l_2d(4525; CHECK-NEXT: main_body:4526; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32.v8i32.v4i32(i32 15, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4527; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164528; CHECK-NEXT: ret void4529;4530main_body:4531 %v = call <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f32.v8i32(i32 15, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4532 store <4 x float> %v, ptr addrspace(1) %out4533 ret void4534}4535 4536define amdgpu_kernel void @gather4_c_l_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t, float %lod) {4537; CHECK-LABEL: @gather4_c_l_2d(4538; CHECK-NEXT: main_body:4539; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.2d.v4f32.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4540; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164541; CHECK-NEXT: ret void4542;4543main_body:4544 %v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.2d.v4f32.f32.v8i32(i32 15, float %zcompare, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4545 store <4 x float> %v, ptr addrspace(1) %out4546 ret void4547}4548 4549define amdgpu_kernel void @gather4_l_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %t, float %lod) {4550; CHECK-LABEL: @gather4_l_o_2d(4551; CHECK-NEXT: main_body:4552; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.gather4.lz.o.2d.v4f32.f32.v8i32.v4i32(i32 15, i32 [[OFFSET:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4553; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164554; CHECK-NEXT: ret void4555;4556main_body:4557 %v = call <4 x float> @llvm.amdgcn.image.gather4.l.o.2d.v4f32.f32.v8i32(i32 15, i32 %offset, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4558 store <4 x float> %v, ptr addrspace(1) %out4559 ret void4560}4561 4562define amdgpu_kernel void @gather4_c_l_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %t, float %lod) {4563; CHECK-LABEL: @gather4_c_l_o_2d(4564; CHECK-NEXT: main_body:4565; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.o.2d.v4f32.f32.v8i32.v4i32(i32 15, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4566; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164567; CHECK-NEXT: ret void4568;4569main_body:4570 %v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.o.2d.v4f32.f32.v8i32(i32 15, i32 %offset, float %zcompare, float %s, float %t, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4571 store <4 x float> %v, ptr addrspace(1) %out4572 ret void4573}4574 4575define amdgpu_kernel void @gather4_c_l_o_2darray(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %t, float %slice, float %lod) {4576; CHECK-LABEL: @gather4_c_l_o_2darray(4577; CHECK-NEXT: main_body:4578; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.o.2darray.v4f32.f32.v8i32.v4i32(i32 15, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[T:%.*]], float [[SLICE:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4579; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164580; CHECK-NEXT: ret void4581;4582main_body:4583 %v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.o.2darray.v4f32.f32.v8i32(i32 15, i32 %offset, float %zcompare, float %s, float %t, float %slice, float 0.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4584 store <4 x float> %v, ptr addrspace(1) %out4585 ret void4586}4587 4588; --------------------------------------------------------------------4589; llvm.amdgcn.image.sample mipmap zero4590; --------------------------------------------------------------------4591 4592define amdgpu_kernel void @load_mip_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, i32 %s) {4593; CHECK-LABEL: @load_mip_1d(4594; CHECK-NEXT: main_body:4595; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32.v8i32(i32 15, i32 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)4596; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164597; CHECK-NEXT: ret void4598;4599main_body:4600 %v = call <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i32.v8i32(i32 15, i32 %s, i32 0, <8 x i32> %rsrc, i32 0, i32 0)4601 store <4 x float> %v, ptr addrspace(1) %out4602 ret void4603}4604 4605define amdgpu_kernel void @load_mip_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, i32 %s, i32 %t) {4606; CHECK-LABEL: @load_mip_2d(4607; CHECK-NEXT: main_body:4608; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32.v8i32(i32 15, i32 [[S:%.*]], i32 [[T:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)4609; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164610; CHECK-NEXT: ret void4611;4612main_body:4613 %v = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32.v8i32(i32 15, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)4614 store <4 x float> %v, ptr addrspace(1) %out4615 ret void4616}4617 4618define amdgpu_kernel void @load_mip_3d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %u) {4619; CHECK-LABEL: @load_mip_3d(4620; CHECK-NEXT: main_body:4621; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i32.v8i32(i32 15, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[U:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)4622; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164623; CHECK-NEXT: ret void4624;4625main_body:4626 %v = call <4 x float> @llvm.amdgcn.image.load.mip.3d.v4f32.i32.v8i32(i32 15, i32 %s, i32 %t, i32 %u, i32 0, <8 x i32> %rsrc, i32 0, i32 0)4627 store <4 x float> %v, ptr addrspace(1) %out4628 ret void4629}4630 4631define amdgpu_kernel void @load_mip_1darray(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, i32 %s, i32 %t) {4632; CHECK-LABEL: @load_mip_1darray(4633; CHECK-NEXT: main_body:4634; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.load.1darray.v4f32.i32.v8i32(i32 15, i32 [[S:%.*]], i32 [[T:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)4635; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164636; CHECK-NEXT: ret void4637;4638main_body:4639 %v = call <4 x float> @llvm.amdgcn.image.load.mip.1darray.v4f32.i32.v8i32(i32 15, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)4640 store <4 x float> %v, ptr addrspace(1) %out4641 ret void4642}4643 4644define amdgpu_kernel void @load_mip_2darray(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %u) {4645; CHECK-LABEL: @load_mip_2darray(4646; CHECK-NEXT: main_body:4647; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.load.2darray.v4f32.i32.v8i32(i32 15, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[U:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)4648; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164649; CHECK-NEXT: ret void4650;4651main_body:4652 %v = call <4 x float> @llvm.amdgcn.image.load.mip.2darray.v4f32.i32.v8i32(i32 15, i32 %s, i32 %t, i32 %u, i32 0, <8 x i32> %rsrc, i32 0, i32 0)4653 store <4 x float> %v, ptr addrspace(1) %out4654 ret void4655}4656 4657define amdgpu_kernel void @load_mip_cube(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %u) {4658; CHECK-LABEL: @load_mip_cube(4659; CHECK-NEXT: main_body:4660; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.load.cube.v4f32.i32.v8i32(i32 15, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[U:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)4661; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164662; CHECK-NEXT: ret void4663;4664main_body:4665 %v = call <4 x float> @llvm.amdgcn.image.load.mip.cube.v4f32.i32.v8i32(i32 15, i32 %s, i32 %t, i32 %u, i32 0, <8 x i32> %rsrc, i32 0, i32 0)4666 store <4 x float> %v, ptr addrspace(1) %out4667 ret void4668}4669 4670 4671define amdgpu_kernel void @store_mip_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s) {4672; CHECK-LABEL: @store_mip_1d(4673; CHECK-NEXT: main_body:4674; CHECK-NEXT: call void @llvm.amdgcn.image.store.1d.v4f32.i32.v8i32(<4 x float> [[VDATA:%.*]], i32 15, i32 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)4675; CHECK-NEXT: ret void4676;4677main_body:4678 call void @llvm.amdgcn.image.store.mip.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 0, <8 x i32> %rsrc, i32 0, i32 0)4679 ret void4680}4681 4682define amdgpu_kernel void @store_mip_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t) {4683; CHECK-LABEL: @store_mip_2d(4684; CHECK-NEXT: main_body:4685; CHECK-NEXT: call void @llvm.amdgcn.image.store.2d.v4f32.i32.v8i32(<4 x float> [[VDATA:%.*]], i32 15, i32 [[S:%.*]], i32 [[T:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)4686; CHECK-NEXT: ret void4687;4688main_body:4689 call void @llvm.amdgcn.image.store.mip.2d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)4690 ret void4691}4692 4693define amdgpu_kernel void @store_mip_3d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %u) {4694; CHECK-LABEL: @store_mip_3d(4695; CHECK-NEXT: main_body:4696; CHECK-NEXT: call void @llvm.amdgcn.image.store.3d.v4f32.i32.v8i32(<4 x float> [[VDATA:%.*]], i32 15, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[U:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)4697; CHECK-NEXT: ret void4698;4699main_body:4700 call void @llvm.amdgcn.image.store.mip.3d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %u, i32 0, <8 x i32> %rsrc, i32 0, i32 0)4701 ret void4702}4703 4704define amdgpu_kernel void @store_mip_1darray(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t) {4705; CHECK-LABEL: @store_mip_1darray(4706; CHECK-NEXT: main_body:4707; CHECK-NEXT: call void @llvm.amdgcn.image.store.1darray.v4f32.i32.v8i32(<4 x float> [[VDATA:%.*]], i32 15, i32 [[S:%.*]], i32 [[T:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)4708; CHECK-NEXT: ret void4709;4710main_body:4711 call void @llvm.amdgcn.image.store.mip.1darray.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)4712 ret void4713}4714 4715define amdgpu_kernel void @store_mip_2darray(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %u) {4716; CHECK-LABEL: @store_mip_2darray(4717; CHECK-NEXT: main_body:4718; CHECK-NEXT: call void @llvm.amdgcn.image.store.2darray.v4f32.i32.v8i32(<4 x float> [[VDATA:%.*]], i32 15, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[U:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)4719; CHECK-NEXT: ret void4720;4721main_body:4722 call void @llvm.amdgcn.image.store.mip.2darray.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %u, i32 0, <8 x i32> %rsrc, i32 0, i32 0)4723 ret void4724}4725 4726define amdgpu_kernel void @store_mip_cube(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %u) {4727; CHECK-LABEL: @store_mip_cube(4728; CHECK-NEXT: main_body:4729; CHECK-NEXT: call void @llvm.amdgcn.image.store.cube.v4f32.i32.v8i32(<4 x float> [[VDATA:%.*]], i32 15, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[U:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)4730; CHECK-NEXT: ret void4731;4732main_body:4733 call void @llvm.amdgcn.image.store.mip.cube.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %u, i32 0, <8 x i32> %rsrc, i32 0, i32 0)4734 ret void4735}4736 4737declare <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i32.v8i32(i32, i32, i32, <8 x i32>, i32, i32) #14738declare <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32.v8i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #14739declare <4 x float> @llvm.amdgcn.image.load.mip.3d.v4f32.i32.v8i32(i32, i32, i32, i32, i32, <8 x i32>, i32, i32) #14740declare <4 x float> @llvm.amdgcn.image.load.mip.1darray.v4f32.i32.v8i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #14741declare <4 x float> @llvm.amdgcn.image.load.mip.2darray.v4f32.i32.v8i32(i32, i32, i32, i32, i32, <8 x i32>, i32, i32) #14742declare <4 x float> @llvm.amdgcn.image.load.mip.cube.v4f32.i32.v8i32(i32, i32, i32, i32, i32, <8 x i32>, i32, i32) #14743 4744 4745declare void @llvm.amdgcn.image.store.mip.1d.v4f32.i32.v8i32(<4 x float>, i32, i32, i32, <8 x i32>, i32, i32) #04746declare void @llvm.amdgcn.image.store.mip.2d.v4f32.i32.v8i32(<4 x float>, i32, i32, i32, i32, <8 x i32>, i32, i32) #04747declare void @llvm.amdgcn.image.store.mip.3d.v4f32.i32.v8i32(<4 x float>, i32, i32, i32, i32, i32, <8 x i32>, i32, i32) #04748declare void @llvm.amdgcn.image.store.mip.cube.v4f32.i32.v8i32(<4 x float>, i32, i32, i32, i32, i32, <8 x i32>, i32, i32) #04749declare void @llvm.amdgcn.image.store.mip.1darray.v4f32.i32.v8i32(<4 x float>, i32, i32, i32, i32, <8 x i32>, i32, i32) #04750declare void @llvm.amdgcn.image.store.mip.2darray.v4f32.i32.v8i32(<4 x float>, i32, i32, i32, i32, i32, <8 x i32>, i32, i32) #04751 4752; --------------------------------------------------------------------4753; llvm.amdgcn.image.sample bias zero4754; --------------------------------------------------------------------4755 4756declare <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f32.v8i32.v4i32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #14757declare <4 x float> @llvm.amdgcn.image.sample.b.2d.v4f32.f32.v8i32.v4i32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #14758declare <4 x float> @llvm.amdgcn.image.sample.c.b.1d.v4f32.f32.v8i32.v4i32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #14759declare <4 x float> @llvm.amdgcn.image.sample.c.b.2d.v4f32.f32.v8i32.v4i32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #14760declare <4 x float> @llvm.amdgcn.image.sample.b.o.1d.v4f32.f32.v8i32.v4i32(i32, i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #14761declare <4 x float> @llvm.amdgcn.image.sample.b.o.2d.v4f32.f32.v8i32.v4i32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #14762declare <4 x float> @llvm.amdgcn.image.sample.c.b.o.1d.v4f32.f32.v8i32.v4i32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #14763declare <4 x float> @llvm.amdgcn.image.sample.c.b.o.2d.v4f32.f32.v8i32.v4i32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #14764declare <4 x float> @llvm.amdgcn.image.sample.c.b.o.2d.v4f32.f16.v8i32.v4i32(i32, i32, half, float, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #14765 4766declare <4 x float> @llvm.amdgcn.image.gather4.b.2d.v4f32.f32.v8i32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #14767declare <4 x float> @llvm.amdgcn.image.gather4.c.b.2d.v4f32.f32.v8i32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #14768declare <4 x float> @llvm.amdgcn.image.gather4.b.o.2d.v4f32.f32.v8i32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #14769declare <4 x float> @llvm.amdgcn.image.gather4.c.b.o.2d.v4f32.f32.v8i32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #14770 4771define amdgpu_kernel void @sample_b_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {4772; CHECK-LABEL: @sample_b_1d(4773; CHECK-NEXT: main_body:4774; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32.v8i32.v4i32(i32 15, float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4775; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164776; CHECK-NEXT: ret void4777;4778main_body:4779 %v = call <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f32.v8i32.v4i32(i32 15, float 0.0, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4780 store <4 x float> %v, ptr addrspace(1) %out4781 ret void4782}4783 4784define amdgpu_kernel void @sample_b_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {4785; CHECK-LABEL: @sample_b_2d(4786; CHECK-NEXT: main_body:4787; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32.v8i32.v4i32(i32 15, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4788; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164789; CHECK-NEXT: ret void4790;4791main_body:4792 %v = call <4 x float> @llvm.amdgcn.image.sample.b.2d.v4f32.f32.v8i32.v4i32(i32 15, float -0.0, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4793 store <4 x float> %v, ptr addrspace(1) %out4794 ret void4795}4796 4797define amdgpu_kernel void @sample_c_b_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s) {4798; CHECK-LABEL: @sample_c_b_1d(4799; CHECK-NEXT: main_body:4800; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.1d.v4f32.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4801; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164802; CHECK-NEXT: ret void4803;4804main_body:4805 %v = call <4 x float> @llvm.amdgcn.image.sample.c.b.1d.v4f32.f32.v8i32.v4i32(i32 15, float -0.0, float %zcompare, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4806 store <4 x float> %v, ptr addrspace(1) %out4807 ret void4808}4809 4810define amdgpu_kernel void @sample_c_b_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t) {4811; CHECK-LABEL: @sample_c_b_2d(4812; CHECK-NEXT: main_body:4813; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.2d.v4f32.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4814; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164815; CHECK-NEXT: ret void4816;4817main_body:4818 %v = call <4 x float> @llvm.amdgcn.image.sample.c.b.2d.v4f32.f32.v8i32.v4i32(i32 15, float 0.0, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4819 store <4 x float> %v, ptr addrspace(1) %out4820 ret void4821}4822 4823define amdgpu_kernel void @sample_b_o_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s) {4824; CHECK-LABEL: @sample_b_o_1d(4825; CHECK-NEXT: main_body:4826; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.o.1d.v4f32.f32.v8i32.v4i32(i32 15, i32 [[OFFSET:%.*]], float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4827; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164828; CHECK-NEXT: ret void4829;4830main_body:4831 %v = call <4 x float> @llvm.amdgcn.image.sample.b.o.1d.v4f32.f32.v8i32.v4i32(i32 15, i32 %offset, float 0.0, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4832 store <4 x float> %v, ptr addrspace(1) %out4833 ret void4834}4835 4836define amdgpu_kernel void @sample_b_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %t) {4837; CHECK-LABEL: @sample_b_o_2d(4838; CHECK-NEXT: main_body:4839; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.o.2d.v4f32.f32.v8i32.v4i32(i32 15, i32 [[OFFSET:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4840; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164841; CHECK-NEXT: ret void4842;4843main_body:4844 %v = call <4 x float> @llvm.amdgcn.image.sample.b.o.2d.v4f32.f32.v8i32.v4i32(i32 15, i32 %offset, float 0.0, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4845 store <4 x float> %v, ptr addrspace(1) %out4846 ret void4847}4848 4849define amdgpu_kernel void @sample_c_b_o_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s) {4850; CHECK-LABEL: @sample_c_b_o_1d(4851; CHECK-NEXT: main_body:4852; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.o.1d.v4f32.f32.v8i32.v4i32(i32 15, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4853; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164854; CHECK-NEXT: ret void4855;4856main_body:4857 %v = call <4 x float> @llvm.amdgcn.image.sample.c.b.o.1d.v4f32.f32.v8i32.v4i32(i32 15, i32 %offset, float 0.0, float %zcompare, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4858 store <4 x float> %v, ptr addrspace(1) %out4859 ret void4860}4861 4862define amdgpu_kernel void @sample_c_b_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %t) {4863; CHECK-LABEL: @sample_c_b_o_2d(4864; CHECK-NEXT: main_body:4865; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.o.2d.v4f32.f32.v8i32.v4i32(i32 15, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4866; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164867; CHECK-NEXT: ret void4868;4869main_body:4870 %v = call <4 x float> @llvm.amdgcn.image.sample.c.b.o.2d.v4f32.f32.v8i32.v4i32(i32 15, i32 %offset, float 0.0, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4871 store <4 x float> %v, ptr addrspace(1) %out4872 ret void4873}4874 4875define amdgpu_kernel void @gather4_b_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {4876; CHECK-LABEL: @gather4_b_2d(4877; CHECK-NEXT: main_body:4878; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32.v8i32.v4i32(i32 15, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4879; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164880; CHECK-NEXT: ret void4881;4882main_body:4883 %v = call <4 x float> @llvm.amdgcn.image.gather4.b.2d.v4f32.f32.v8i32(i32 15, float 0.0, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4884 store <4 x float> %v, ptr addrspace(1) %out4885 ret void4886}4887 4888define amdgpu_kernel void @gather4_c_b_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t) {4889; CHECK-LABEL: @gather4_c_b_2d(4890; CHECK-NEXT: main_body:4891; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.gather4.c.2d.v4f32.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4892; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164893; CHECK-NEXT: ret void4894;4895main_body:4896 %v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.2d.v4f32.f32.v8i32(i32 15, float 0.0, float %zcompare,float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4897 store <4 x float> %v, ptr addrspace(1) %out4898 ret void4899}4900 4901define amdgpu_kernel void @gather4_b_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %t) {4902; CHECK-LABEL: @gather4_b_o_2d(4903; CHECK-NEXT: main_body:4904; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.gather4.o.2d.v4f32.f32.v8i32.v4i32(i32 15, i32 [[OFFSET:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4905; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164906; CHECK-NEXT: ret void4907;4908main_body:4909 %v = call <4 x float> @llvm.amdgcn.image.gather4.b.o.2d.v4f32.f32.v8i32(i32 15, i32 %offset, float 0.0, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4910 store <4 x float> %v, ptr addrspace(1) %out4911 ret void4912}4913 4914define amdgpu_kernel void @gather4_c_b_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %t) {4915; CHECK-LABEL: @gather4_c_b_o_2d(4916; CHECK-NEXT: main_body:4917; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.gather4.c.o.2d.v4f32.f32.v8i32.v4i32(i32 15, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4918; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164919; CHECK-NEXT: ret void4920;4921main_body:4922 %v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.o.2d.v4f32.f32.v8i32(i32 15, i32 %offset, float 0.0, float %zcompare,float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4923 store <4 x float> %v, ptr addrspace(1) %out4924 ret void4925}4926 4927define amdgpu_kernel void @sample_c_b_o_a16_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %s, half %t) {4928; CHECK-LABEL: @sample_c_b_o_a16_2d(4929; CHECK-NEXT: main_body:4930; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.o.2d.v4f32.f16.v8i32.v4i32(i32 15, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], half [[S:%.*]], half [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4931; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164932; CHECK-NEXT: ret void4933;4934main_body:4935 %v = call <4 x float> @llvm.amdgcn.image.sample.c.b.o.2d.v4f32.f16.v8i32.v4i32(i32 15, i32 %offset, half 0.0, float %zcompare, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4936 store <4 x float> %v, ptr addrspace(1) %out4937 ret void4938}4939 4940; Check that bias is not optimized away if > 04941define amdgpu_kernel void @sample_b_1d_pos(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {4942; CHECK-LABEL: @sample_b_1d_pos(4943; CHECK-NEXT: main_body:4944; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float 1.000000e+00, float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4945; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164946; CHECK-NEXT: ret void4947;4948main_body:4949 %v = call <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f32.v8i32.v4i32(i32 15, float 1.0, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4950 store <4 x float> %v, ptr addrspace(1) %out4951 ret void4952}4953 4954; Check that bias is not optimized away if < 04955define amdgpu_kernel void @sample_b_1d_neg(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {4956; CHECK-LABEL: @sample_b_1d_neg(4957; CHECK-NEXT: main_body:4958; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float -1.000000e+00, float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4959; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164960; CHECK-NEXT: ret void4961;4962main_body:4963 %v = call <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f32.v8i32.v4i32(i32 15, float -1.0, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4964 store <4 x float> %v, ptr addrspace(1) %out4965 ret void4966}4967 4968; Zero bias + A164969define amdgpu_kernel void @sample_b_1d_a16(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s) {4970; CHECK-LABEL: @sample_b_1d_a16(4971; CHECK-NEXT: main_body:4972; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f16.v8i32.v4i32(i32 15, half [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4973; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164974; CHECK-NEXT: ret void4975;4976main_body:4977 %s32 = fpext half %s to float4978 %v = call <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f32.v8i32.v4i32(i32 15, float -0.0, float %s32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4979 store <4 x float> %v, ptr addrspace(1) %out4980 ret void4981}4982 4983; --------------------------------------------------------------------4984; llvm.amdgcn.image.sample offset zero4985; --------------------------------------------------------------------4986 4987define amdgpu_kernel void @offset_sample_o_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {4988; CHECK-LABEL: @offset_sample_o_1d(4989; CHECK-NEXT: main_body:4990; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32.v8i32.v4i32(i32 15, float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)4991; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 164992; CHECK-NEXT: ret void4993;4994main_body:4995 %v = call <4 x float> @llvm.amdgcn.image.sample.o.1d.v4f32.f32.v8i32.v4i32(i32 15, i32 0, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)4996 store <4 x float> %v, ptr addrspace(1) %out4997 ret void4998}4999 5000define amdgpu_kernel void @offset_sample_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {5001; CHECK-LABEL: @offset_sample_o_2d(5002; CHECK-NEXT: main_body:5003; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32.v8i32.v4i32(i32 15, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5004; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165005; CHECK-NEXT: ret void5006;5007main_body:5008 %v = call <4 x float> @llvm.amdgcn.image.sample.o.2d.v4f32.f32.v8i32.v4i32(i32 15, i32 0, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5009 store <4 x float> %v, ptr addrspace(1) %out5010 ret void5011}5012 5013define amdgpu_kernel void @offset_sample_c_o_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s) {5014; CHECK-LABEL: @offset_sample_c_o_1d(5015; CHECK-NEXT: main_body:5016; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.1d.v4f32.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5017; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165018; CHECK-NEXT: ret void5019;5020main_body:5021 %v = call <4 x float> @llvm.amdgcn.image.sample.c.o.1d.v4f32.f32.v8i32.v4i32(i32 15, i32 0, float %zcompare, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5022 store <4 x float> %v, ptr addrspace(1) %out5023 ret void5024}5025 5026define amdgpu_kernel void @offset_sample_c_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t) {5027; CHECK-LABEL: @offset_sample_c_o_2d(5028; CHECK-NEXT: main_body:5029; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.2d.v4f32.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5030; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165031; CHECK-NEXT: ret void5032;5033main_body:5034 %v = call <4 x float> @llvm.amdgcn.image.sample.c.o.2d.v4f32.f32.v8i32.v4i32(i32 15, i32 0, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5035 store <4 x float> %v, ptr addrspace(1) %out5036 ret void5037}5038 5039define amdgpu_kernel void @offset_sample_cl_o_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %clamp) {5040; CHECK-LABEL: @offset_sample_cl_o_1d(5041; CHECK-NEXT: main_body:5042; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.cl.1d.v4f32.f32.v8i32.v4i32(i32 15, float [[S:%.*]], float [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5043; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165044; CHECK-NEXT: ret void5045;5046main_body:5047 %v = call <4 x float> @llvm.amdgcn.image.sample.cl.o.1d.v4f32.f32.v8i32.v4i32(i32 15, i32 0, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5048 store <4 x float> %v, ptr addrspace(1) %out5049 ret void5050}5051 5052define amdgpu_kernel void @offset_sample_cl_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %clamp) {5053; CHECK-LABEL: @offset_sample_cl_o_2d(5054; CHECK-NEXT: main_body:5055; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.cl.2d.v4f32.f32.v8i32.v4i32(i32 15, float [[S:%.*]], float [[T:%.*]], float [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5056; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165057; CHECK-NEXT: ret void5058;5059main_body:5060 %v = call <4 x float> @llvm.amdgcn.image.sample.cl.o.2d.v4f32.f32.v8i32.v4i32(i32 15, i32 0, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5061 store <4 x float> %v, ptr addrspace(1) %out5062 ret void5063}5064 5065define amdgpu_kernel void @offset_sample_c_cl_o_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %clamp) {5066; CHECK-LABEL: @offset_sample_c_cl_o_1d(5067; CHECK-NEXT: main_body:5068; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.cl.1d.v4f32.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5069; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165070; CHECK-NEXT: ret void5071;5072main_body:5073 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cl.o.1d.v4f32.f32.v8i32.v4i32(i32 15, i32 0, float %zcompare, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5074 store <4 x float> %v, ptr addrspace(1) %out5075 ret void5076}5077 5078define amdgpu_kernel void @offset_sample_c_cl_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t, float %clamp) {5079; CHECK-LABEL: @offset_sample_c_cl_o_2d(5080; CHECK-NEXT: main_body:5081; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.cl.2d.v4f32.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[T:%.*]], float [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5082; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165083; CHECK-NEXT: ret void5084;5085main_body:5086 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cl.o.2d.v4f32.f32.v8i32.v4i32(i32 15, i32 0, float %zcompare, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5087 store <4 x float> %v, ptr addrspace(1) %out5088 ret void5089}5090 5091define amdgpu_kernel void @offset_sample_b_o_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %s) {5092; CHECK-LABEL: @offset_sample_b_o_1d(5093; CHECK-NEXT: main_body:5094; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[BIAS:%.*]], float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5095; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165096; CHECK-NEXT: ret void5097;5098main_body:5099 %v = call <4 x float> @llvm.amdgcn.image.sample.b.o.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, i32 0, float %bias, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5100 store <4 x float> %v, ptr addrspace(1) %out5101 ret void5102}5103 5104define amdgpu_kernel void @offset_sample_b_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %s, float %t) {5105; CHECK-LABEL: @offset_sample_b_o_2d(5106; CHECK-NEXT: main_body:5107; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.b.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[BIAS:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5108; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165109; CHECK-NEXT: ret void5110;5111main_body:5112 %v = call <4 x float> @llvm.amdgcn.image.sample.b.o.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, i32 0, float %bias, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5113 store <4 x float> %v, ptr addrspace(1) %out5114 ret void5115}5116 5117define amdgpu_kernel void @offset_sample_c_b_o_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, float %s) {5118; CHECK-LABEL: @offset_sample_c_b_o_1d(5119; CHECK-NEXT: main_body:5120; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.b.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[BIAS:%.*]], float [[ZCOMPARE:%.*]], float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5121; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165122; CHECK-NEXT: ret void5123;5124main_body:5125 %v = call <4 x float> @llvm.amdgcn.image.sample.c.b.o.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, i32 0, float %bias, float %zcompare, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5126 store <4 x float> %v, ptr addrspace(1) %out5127 ret void5128}5129 5130define amdgpu_kernel void @offset_sample_c_b_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, float %s, float %t) {5131; CHECK-LABEL: @offset_sample_c_b_o_2d(5132; CHECK-NEXT: main_body:5133; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.b.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[BIAS:%.*]], float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5134; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165135; CHECK-NEXT: ret void5136;5137main_body:5138 %v = call <4 x float> @llvm.amdgcn.image.sample.c.b.o.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, i32 0, float %bias, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5139 store <4 x float> %v, ptr addrspace(1) %out5140 ret void5141}5142 5143define amdgpu_kernel void @offset_sample_b_cl_o_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %s, float %clamp) {5144; CHECK-LABEL: @offset_sample_b_cl_o_1d(5145; CHECK-NEXT: main_body:5146; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.b.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[BIAS:%.*]], float [[S:%.*]], float [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5147; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165148; CHECK-NEXT: ret void5149;5150main_body:5151 %v = call <4 x float> @llvm.amdgcn.image.sample.b.cl.o.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, i32 0, float %bias, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5152 store <4 x float> %v, ptr addrspace(1) %out5153 ret void5154}5155 5156define amdgpu_kernel void @offset_sample_b_cl_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %s, float %t, float %clamp) {5157; CHECK-LABEL: @offset_sample_b_cl_o_2d(5158; CHECK-NEXT: main_body:5159; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.b.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[BIAS:%.*]], float [[S:%.*]], float [[T:%.*]], float [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5160; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165161; CHECK-NEXT: ret void5162;5163main_body:5164 %v = call <4 x float> @llvm.amdgcn.image.sample.b.cl.o.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, i32 0, float %bias, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5165 store <4 x float> %v, ptr addrspace(1) %out5166 ret void5167}5168 5169define amdgpu_kernel void @offset_sample_c_b_cl_o_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, float %s, float %clamp) {5170; CHECK-LABEL: @offset_sample_c_b_cl_o_1d(5171; CHECK-NEXT: main_body:5172; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[BIAS:%.*]], float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5173; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165174; CHECK-NEXT: ret void5175;5176main_body:5177 %v = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.o.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, i32 0, float %bias, float %zcompare, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5178 store <4 x float> %v, ptr addrspace(1) %out5179 ret void5180}5181 5182define amdgpu_kernel void @offset_sample_c_b_cl_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %bias, float %zcompare, float %s, float %t, float %clamp) {5183; CHECK-LABEL: @offset_sample_c_b_cl_o_2d(5184; CHECK-NEXT: main_body:5185; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[BIAS:%.*]], float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[T:%.*]], float [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5186; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165187; CHECK-NEXT: ret void5188;5189main_body:5190 %v = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.o.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, i32 0, float %bias, float %zcompare, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5191 store <4 x float> %v, ptr addrspace(1) %out5192 ret void5193}5194 5195define amdgpu_kernel void @offset_sample_d_o_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dsdv, float %s) {5196; CHECK-LABEL: @offset_sample_d_o_1d(5197; CHECK-NEXT: main_body:5198; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.d.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[DSDH:%.*]], float [[DSDV:%.*]], float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5199; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165200; CHECK-NEXT: ret void5201;5202main_body:5203 %v = call <4 x float> @llvm.amdgcn.image.sample.d.o.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, i32 0, float %dsdh, float %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5204 store <4 x float> %v, ptr addrspace(1) %out5205 ret void5206}5207 5208define amdgpu_kernel void @offset_sample_d_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t) {5209; CHECK-LABEL: @offset_sample_d_o_2d(5210; CHECK-NEXT: main_body:5211; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[DSDH:%.*]], float [[DTDH:%.*]], float [[DSDV:%.*]], float [[DTDV:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5212; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165213; CHECK-NEXT: ret void5214;5215main_body:5216 %v = call <4 x float> @llvm.amdgcn.image.sample.d.o.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, i32 0, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5217 store <4 x float> %v, ptr addrspace(1) %out5218 ret void5219}5220 5221define amdgpu_kernel void @offset_sample_c_d_o_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dsdv, float %s) {5222; CHECK-LABEL: @offset_sample_c_d_o_1d(5223; CHECK-NEXT: main_body:5224; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], float [[DSDH:%.*]], float [[DSDV:%.*]], float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5225; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165226; CHECK-NEXT: ret void5227;5228main_body:5229 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.o.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, i32 0, float %zcompare, float %dsdh, float %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5230 store <4 x float> %v, ptr addrspace(1) %out5231 ret void5232}5233 5234define amdgpu_kernel void @offset_sample_c_d_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t) {5235; CHECK-LABEL: @offset_sample_c_d_o_2d(5236; CHECK-NEXT: main_body:5237; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.d.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], float [[DSDH:%.*]], float [[DTDH:%.*]], float [[DSDV:%.*]], float [[DTDV:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5238; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165239; CHECK-NEXT: ret void5240;5241main_body:5242 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.o.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, i32 0, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5243 store <4 x float> %v, ptr addrspace(1) %out5244 ret void5245}5246 5247define amdgpu_kernel void @offset_sample_d_cl_o_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dsdv, float %s, float %clamp) {5248; CHECK-LABEL: @offset_sample_d_cl_o_1d(5249; CHECK-NEXT: main_body:5250; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[DSDH:%.*]], float [[DSDV:%.*]], float [[S:%.*]], float [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5251; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165252; CHECK-NEXT: ret void5253;5254main_body:5255 %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.o.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, i32 0, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5256 store <4 x float> %v, ptr addrspace(1) %out5257 ret void5258}5259 5260define amdgpu_kernel void @offset_sample_d_cl_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, float %clamp) {5261; CHECK-LABEL: @offset_sample_d_cl_o_2d(5262; CHECK-NEXT: main_body:5263; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.d.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[DSDH:%.*]], float [[DTDH:%.*]], float [[DSDV:%.*]], float [[DTDV:%.*]], float [[S:%.*]], float [[T:%.*]], float [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5264; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165265; CHECK-NEXT: ret void5266;5267main_body:5268 %v = call <4 x float> @llvm.amdgcn.image.sample.d.cl.o.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, i32 0, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5269 store <4 x float> %v, ptr addrspace(1) %out5270 ret void5271}5272 5273define amdgpu_kernel void @offset_sample_c_d_cl_o_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dsdv, float %s, float %clamp) {5274; CHECK-LABEL: @offset_sample_c_d_cl_o_1d(5275; CHECK-NEXT: main_body:5276; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], float [[DSDH:%.*]], float [[DSDV:%.*]], float [[S:%.*]], float [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5277; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165278; CHECK-NEXT: ret void5279;5280main_body:5281 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.o.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, i32 0, float %zcompare, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5282 store <4 x float> %v, ptr addrspace(1) %out5283 ret void5284}5285 5286define amdgpu_kernel void @offset_sample_c_d_cl_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, float %clamp) {5287; CHECK-LABEL: @offset_sample_c_d_cl_o_2d(5288; CHECK-NEXT: main_body:5289; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], float [[DSDH:%.*]], float [[DTDH:%.*]], float [[DSDV:%.*]], float [[DTDV:%.*]], float [[S:%.*]], float [[T:%.*]], float [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5290; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165291; CHECK-NEXT: ret void5292;5293main_body:5294 %v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.o.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, i32 0, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5295 store <4 x float> %v, ptr addrspace(1) %out5296 ret void5297}5298 5299define amdgpu_kernel void @offset_sample_cd_o_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dsdv, float %s) {5300; CHECK-LABEL: @offset_sample_cd_o_1d(5301; CHECK-NEXT: main_body:5302; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[DSDH:%.*]], float [[DSDV:%.*]], float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5303; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165304; CHECK-NEXT: ret void5305;5306main_body:5307 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.o.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, i32 0, float %dsdh, float %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5308 store <4 x float> %v, ptr addrspace(1) %out5309 ret void5310}5311 5312define amdgpu_kernel void @offset_sample_cd_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t) {5313; CHECK-LABEL: @offset_sample_cd_o_2d(5314; CHECK-NEXT: main_body:5315; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.cd.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[DSDH:%.*]], float [[DTDH:%.*]], float [[DSDV:%.*]], float [[DTDV:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5316; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165317; CHECK-NEXT: ret void5318;5319main_body:5320 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.o.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, i32 0, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5321 store <4 x float> %v, ptr addrspace(1) %out5322 ret void5323}5324 5325define amdgpu_kernel void @offset_sample_c_cd_o_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dsdv, float %s) {5326; CHECK-LABEL: @offset_sample_c_cd_o_1d(5327; CHECK-NEXT: main_body:5328; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], float [[DSDH:%.*]], float [[DSDV:%.*]], float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5329; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165330; CHECK-NEXT: ret void5331;5332main_body:5333 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.o.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, i32 0, float %zcompare, float %dsdh, float %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5334 store <4 x float> %v, ptr addrspace(1) %out5335 ret void5336}5337 5338define amdgpu_kernel void @offset_sample_c_cd_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t) {5339; CHECK-LABEL: @offset_sample_c_cd_o_2d(5340; CHECK-NEXT: main_body:5341; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.cd.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], float [[DSDH:%.*]], float [[DTDH:%.*]], float [[DSDV:%.*]], float [[DTDV:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5342; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165343; CHECK-NEXT: ret void5344;5345main_body:5346 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.o.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, i32 0, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5347 store <4 x float> %v, ptr addrspace(1) %out5348 ret void5349}5350 5351define amdgpu_kernel void @offset_sample_cd_cl_o_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dsdv, float %s, float %clamp) {5352; CHECK-LABEL: @offset_sample_cd_cl_o_1d(5353; CHECK-NEXT: main_body:5354; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[DSDH:%.*]], float [[DSDV:%.*]], float [[S:%.*]], float [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5355; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165356; CHECK-NEXT: ret void5357;5358main_body:5359 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.o.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, i32 0, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5360 store <4 x float> %v, ptr addrspace(1) %out5361 ret void5362}5363 5364define amdgpu_kernel void @offset_sample_cd_cl_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, float %clamp) {5365; CHECK-LABEL: @offset_sample_cd_cl_o_2d(5366; CHECK-NEXT: main_body:5367; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[DSDH:%.*]], float [[DTDH:%.*]], float [[DSDV:%.*]], float [[DTDV:%.*]], float [[S:%.*]], float [[T:%.*]], float [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5368; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165369; CHECK-NEXT: ret void5370;5371main_body:5372 %v = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.o.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, i32 0, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5373 store <4 x float> %v, ptr addrspace(1) %out5374 ret void5375}5376 5377define amdgpu_kernel void @offset_sample_c_cd_cl_o_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dsdv, float %s, float %clamp) {5378; CHECK-LABEL: @offset_sample_c_cd_cl_o_1d(5379; CHECK-NEXT: main_body:5380; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], float [[DSDH:%.*]], float [[DSDV:%.*]], float [[S:%.*]], float [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5381; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165382; CHECK-NEXT: ret void5383;5384main_body:5385 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.o.1d.v4f32.f32.f32.v8i32.v4i32(i32 15, i32 0, float %zcompare, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5386 store <4 x float> %v, ptr addrspace(1) %out5387 ret void5388}5389 5390define amdgpu_kernel void @offset_sample_c_cd_cl_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, float %clamp) {5391; CHECK-LABEL: @offset_sample_c_cd_cl_o_2d(5392; CHECK-NEXT: main_body:5393; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], float [[DSDH:%.*]], float [[DTDH:%.*]], float [[DSDV:%.*]], float [[DTDV:%.*]], float [[S:%.*]], float [[T:%.*]], float [[CLAMP:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5394; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165395; CHECK-NEXT: ret void5396;5397main_body:5398 %v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.o.2d.v4f32.f32.f32.v8i32.v4i32(i32 15, i32 0, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5399 store <4 x float> %v, ptr addrspace(1) %out5400 ret void5401}5402 5403define amdgpu_kernel void @offset_sample_l_o_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %lod) {5404; CHECK-LABEL: @offset_sample_l_o_1d(5405; CHECK-NEXT: main_body:5406; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.l.1d.v4f32.f32.v8i32.v4i32(i32 15, float [[S:%.*]], float [[LOD:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5407; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165408; CHECK-NEXT: ret void5409;5410main_body:5411 %v = call <4 x float> @llvm.amdgcn.image.sample.l.o.1d.v4f32.f32.v8i32.v4i32(i32 15, i32 0, float %s, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5412 store <4 x float> %v, ptr addrspace(1) %out5413 ret void5414}5415 5416define amdgpu_kernel void @offset_sample_l_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %lod) {5417; CHECK-LABEL: @offset_sample_l_o_2d(5418; CHECK-NEXT: main_body:5419; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.l.2d.v4f32.f32.v8i32.v4i32(i32 15, float [[S:%.*]], float [[T:%.*]], float [[LOD:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5420; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165421; CHECK-NEXT: ret void5422;5423main_body:5424 %v = call <4 x float> @llvm.amdgcn.image.sample.l.o.2d.v4f32.f32.v8i32.v4i32(i32 15, i32 0, float %s, float %t, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5425 store <4 x float> %v, ptr addrspace(1) %out5426 ret void5427}5428 5429define amdgpu_kernel void @offset_sample_c_l_o_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %lod) {5430; CHECK-LABEL: @offset_sample_c_l_o_1d(5431; CHECK-NEXT: main_body:5432; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.l.1d.v4f32.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[LOD:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5433; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165434; CHECK-NEXT: ret void5435;5436main_body:5437 %v = call <4 x float> @llvm.amdgcn.image.sample.c.l.o.1d.v4f32.f32.v8i32.v4i32(i32 15, i32 0, float %zcompare, float %s, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5438 store <4 x float> %v, ptr addrspace(1) %out5439 ret void5440}5441 5442define amdgpu_kernel void @offset_sample_c_l_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t, float %lod) {5443; CHECK-LABEL: @offset_sample_c_l_o_2d(5444; CHECK-NEXT: main_body:5445; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.l.2d.v4f32.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[T:%.*]], float [[LOD:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5446; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165447; CHECK-NEXT: ret void5448;5449main_body:5450 %v = call <4 x float> @llvm.amdgcn.image.sample.c.l.o.2d.v4f32.f32.v8i32.v4i32(i32 15, i32 0, float %zcompare, float %s, float %t, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5451 store <4 x float> %v, ptr addrspace(1) %out5452 ret void5453}5454 5455define amdgpu_kernel void @offset_sample_lz_o_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {5456; CHECK-LABEL: @offset_sample_lz_o_1d(5457; CHECK-NEXT: main_body:5458; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.lz.1d.v4f32.f32.v8i32.v4i32(i32 15, float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5459; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165460; CHECK-NEXT: ret void5461;5462main_body:5463 %v = call <4 x float> @llvm.amdgcn.image.sample.lz.o.1d.v4f32.f32.v8i32.v4i32(i32 15, i32 0, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5464 store <4 x float> %v, ptr addrspace(1) %out5465 ret void5466}5467 5468define amdgpu_kernel void @offset_sample_lz_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {5469; CHECK-LABEL: @offset_sample_lz_o_2d(5470; CHECK-NEXT: main_body:5471; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32.v8i32.v4i32(i32 15, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5472; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165473; CHECK-NEXT: ret void5474;5475main_body:5476 %v = call <4 x float> @llvm.amdgcn.image.sample.lz.o.2d.v4f32.f32.v8i32.v4i32(i32 15, i32 0, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5477 store <4 x float> %v, ptr addrspace(1) %out5478 ret void5479}5480 5481define amdgpu_kernel void @offset_sample_c_lz_o_1d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s) {5482; CHECK-LABEL: @offset_sample_c_lz_o_1d(5483; CHECK-NEXT: main_body:5484; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.lz.1d.v4f32.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], float [[S:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5485; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165486; CHECK-NEXT: ret void5487;5488main_body:5489 %v = call <4 x float> @llvm.amdgcn.image.sample.c.lz.o.1d.v4f32.f32.v8i32.v4i32(i32 15, i32 0, float %zcompare, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5490 store <4 x float> %v, ptr addrspace(1) %out5491 ret void5492}5493 5494define amdgpu_kernel void @offset_sample_c_lz_o_2d(ptr addrspace(1) %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t) {5495; CHECK-LABEL: @offset_sample_c_lz_o_2d(5496; CHECK-NEXT: main_body:5497; CHECK-NEXT: [[V:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.c.lz.2d.v4f32.f32.v8i32.v4i32(i32 15, float [[ZCOMPARE:%.*]], float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)5498; CHECK-NEXT: store <4 x float> [[V]], ptr addrspace(1) [[OUT:%.*]], align 165499; CHECK-NEXT: ret void5500;5501main_body:5502 %v = call <4 x float> @llvm.amdgcn.image.sample.c.lz.o.2d.v4f32.f32.v8i32.v4i32(i32 15, i32 0, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)5503 store <4 x float> %v, ptr addrspace(1) %out5504 ret void5505}5506 5507declare <4 x float> @llvm.amdgcn.image.sample.o.1d.v4f32.f32.v8i32.v4i32(i32, i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15508declare <4 x float> @llvm.amdgcn.image.sample.o.2d.v4f32.f32.v8i32.v4i32(i32, i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15509declare <4 x float> @llvm.amdgcn.image.sample.c.o.1d.v4f32.f32.v8i32.v4i32(i32, i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15510declare <4 x float> @llvm.amdgcn.image.sample.c.o.2d.v4f32.f32.v8i32.v4i32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15511declare <4 x float> @llvm.amdgcn.image.sample.cl.o.1d.v4f32.f32.v8i32.v4i32(i32, i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15512declare <4 x float> @llvm.amdgcn.image.sample.cl.o.2d.v4f32.f32.v8i32.v4i32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15513declare <4 x float> @llvm.amdgcn.image.sample.c.cl.o.1d.v4f32.f32.v8i32.v4i32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15514declare <4 x float> @llvm.amdgcn.image.sample.c.cl.o.2d.v4f32.f32.v8i32.v4i32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15515 5516declare <4 x float> @llvm.amdgcn.image.sample.b.o.1d.v4f32.f32.f32.v8i32.v4i32(i32, i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15517declare <4 x float> @llvm.amdgcn.image.sample.b.o.2d.v4f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15518declare <4 x float> @llvm.amdgcn.image.sample.c.b.o.1d.v4f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15519declare <4 x float> @llvm.amdgcn.image.sample.c.b.o.2d.v4f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15520declare <4 x float> @llvm.amdgcn.image.sample.b.cl.o.1d.v4f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15521declare <4 x float> @llvm.amdgcn.image.sample.b.cl.o.2d.v4f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15522declare <4 x float> @llvm.amdgcn.image.sample.c.b.cl.o.1d.v4f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15523declare <4 x float> @llvm.amdgcn.image.sample.c.b.cl.o.2d.v4f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15524 5525declare <4 x float> @llvm.amdgcn.image.sample.d.o.1d.v4f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15526declare <4 x float> @llvm.amdgcn.image.sample.d.o.2d.v4f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15527declare <4 x float> @llvm.amdgcn.image.sample.c.d.o.1d.v4f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15528declare <4 x float> @llvm.amdgcn.image.sample.c.d.o.2d.v4f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15529declare <4 x float> @llvm.amdgcn.image.sample.d.cl.o.1d.v4f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15530declare <4 x float> @llvm.amdgcn.image.sample.d.cl.o.2d.v4f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15531declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.o.1d.v4f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15532declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.o.2d.v4f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15533 5534declare <4 x float> @llvm.amdgcn.image.sample.cd.o.1d.v4f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15535declare <4 x float> @llvm.amdgcn.image.sample.cd.o.2d.v4f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15536declare <4 x float> @llvm.amdgcn.image.sample.c.cd.o.1d.v4f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15537declare <4 x float> @llvm.amdgcn.image.sample.c.cd.o.2d.v4f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15538declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.o.1d.v4f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15539declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.o.2d.v4f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15540declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.o.1d.v4f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15541declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.o.2d.v4f32.f32.f32.v8i32.v4i32(i32, i32, float, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15542 5543declare <4 x float> @llvm.amdgcn.image.sample.lz.o.1d.v4f32.f32.v8i32.v4i32(i32, i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15544declare <4 x float> @llvm.amdgcn.image.sample.lz.o.2d.v4f32.f32.v8i32.v4i32(i32, i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15545declare <4 x float> @llvm.amdgcn.image.sample.c.lz.o.1d.v4f32.f32.v8i32.v4i32(i32, i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15546declare <4 x float> @llvm.amdgcn.image.sample.c.lz.o.2d.v4f32.f32.v8i32.v4i32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #15547 5548; --------------------------------------------------------------------5549; llvm.amdgcn.is.shared5550; --------------------------------------------------------------------5551 5552declare i1 @llvm.amdgcn.is.shared(ptr) nounwind readnone5553 5554define i1 @test_is_shared_null() nounwind {5555; CHECK-LABEL: @test_is_shared_null(5556; CHECK-NEXT: ret i1 false5557;5558 %val = call i1 @llvm.amdgcn.is.shared(ptr null)5559 ret i1 %val5560}5561 5562define i1 @test_is_shared_undef() nounwind {5563; CHECK-LABEL: @test_is_shared_undef(5564; CHECK-NEXT: ret i1 undef5565;5566 %val = call i1 @llvm.amdgcn.is.shared(ptr undef)5567 ret i1 %val5568}5569 5570define i1 @test_is_shared_poison() nounwind {5571; CHECK-LABEL: @test_is_shared_poison(5572; CHECK-NEXT: ret i1 poison5573;5574 %val = call i1 @llvm.amdgcn.is.shared(ptr poison)5575 ret i1 %val5576}5577 5578; --------------------------------------------------------------------5579; llvm.amdgcn.is.private5580; --------------------------------------------------------------------5581 5582declare i1 @llvm.amdgcn.is.private(ptr) nounwind readnone5583 5584define i1 @test_is_private_null() nounwind {5585; CHECK-LABEL: @test_is_private_null(5586; CHECK-NEXT: ret i1 false5587;5588 %val = call i1 @llvm.amdgcn.is.private(ptr null)5589 ret i1 %val5590}5591 5592define i1 @test_is_private_undef() nounwind {5593; CHECK-LABEL: @test_is_private_undef(5594; CHECK-NEXT: ret i1 undef5595;5596 %val = call i1 @llvm.amdgcn.is.private(ptr undef)5597 ret i1 %val5598}5599 5600define i1 @test_is_private_poison() nounwind {5601; CHECK-LABEL: @test_is_private_poison(5602; CHECK-NEXT: ret i1 poison5603;5604 %val = call i1 @llvm.amdgcn.is.private(ptr poison)5605 ret i1 %val5606}5607 5608; --------------------------------------------------------------------5609; llvm.amdgcn.trig.preop5610; --------------------------------------------------------------------5611 5612declare double @llvm.amdgcn.trig.preop.f64(double, i32)5613declare float @llvm.amdgcn.trig.preop.f32(float, i32)5614 5615define double @trig_preop_constfold_variable_undef_arg(i32 %arg) {5616; CHECK-LABEL: @trig_preop_constfold_variable_undef_arg(5617; CHECK-NEXT: ret double 0x7FF80000000000005618;5619 %val = call double @llvm.amdgcn.trig.preop.f64(double undef, i32 %arg)5620 ret double %val5621}5622 5623define double @trig_preop_constfold_variable_poison_arg(i32 %arg) {5624; CHECK-LABEL: @trig_preop_constfold_variable_poison_arg(5625; CHECK-NEXT: ret double poison5626;5627 %val = call double @llvm.amdgcn.trig.preop.f64(double poison, i32 %arg)5628 ret double %val5629}5630 5631define double @trig_preop_constfold_variable_arg_undef(double %arg) {5632; CHECK-LABEL: @trig_preop_constfold_variable_arg_undef(5633; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double [[ARG:%.*]], i32 undef)5634; CHECK-NEXT: ret double [[VAL]]5635;5636 %val = call double @llvm.amdgcn.trig.preop.f64(double %arg, i32 undef)5637 ret double %val5638}5639 5640define double @trig_preop_constfold_variable_arg_poison(double %arg) {5641; CHECK-LABEL: @trig_preop_constfold_variable_arg_poison(5642; CHECK-NEXT: ret double poison5643;5644 %val = call double @llvm.amdgcn.trig.preop.f64(double %arg, i32 poison)5645 ret double %val5646}5647 5648define double @trig_preop_constfold_variable_int(i32 %arg) {5649; CHECK-LABEL: @trig_preop_constfold_variable_int(5650; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 3.454350e+02, i32 [[ARG:%.*]])5651; CHECK-NEXT: ret double [[VAL]]5652;5653 %val = call double @llvm.amdgcn.trig.preop.f64(double 3.454350e+02, i32 %arg)5654 ret double %val5655}5656 5657define double @trig_preop_qnan(i32 %arg) {5658; CHECK-LABEL: @trig_preop_qnan(5659; CHECK-NEXT: ret double 0x7FF80000000000005660;5661 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x7FF8000000000000, i32 %arg)5662 ret double %val5663}5664 5665define double @trig_preop_snan(i32 %arg) {5666; CHECK-LABEL: @trig_preop_snan(5667; CHECK-NEXT: ret double 0x7FF80000000000015668;5669 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x7FF0000000000001, i32 %arg)5670 ret double %val5671}5672 5673define double @trig_preop_inf_0() {5674; CHECK-LABEL: @trig_preop_inf_0(5675; CHECK-NEXT: ret double 0xB43DD63F5F2F8BD5676;5677 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x7FF0000000000000, i32 0)5678 ret double %val5679}5680 5681define double @trig_preop_ninf_0() {5682; CHECK-LABEL: @trig_preop_ninf_0(5683; CHECK-NEXT: ret double 0xB43DD63F5F2F8BD5684;5685 %val = call double @llvm.amdgcn.trig.preop.f64(double 0xFFF0000000000000, i32 0)5686 ret double %val5687}5688 5689define double @trig_preop_variable_fp(double %arg) {5690; CHECK-LABEL: @trig_preop_variable_fp(5691; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double [[ARG:%.*]], i32 5)5692; CHECK-NEXT: ret double [[VAL]]5693;5694 %val = call double @llvm.amdgcn.trig.preop.f64(double %arg, i32 5)5695 ret double %val5696}5697 5698define double @trig_preop_variable_args(double %arg0, i32 %arg1) {5699; CHECK-LABEL: @trig_preop_variable_args(5700; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double [[ARG0:%.*]], i32 [[ARG1:%.*]])5701; CHECK-NEXT: ret double [[VAL]]5702;5703 %val = call double @llvm.amdgcn.trig.preop.f64(double %arg0, i32 %arg1)5704 ret double %val5705}5706 5707define double @trig_preop_constfold() {5708; CHECK-LABEL: @trig_preop_constfold(5709; CHECK-NEXT: ret double 0x394A6EE06DB14ACC5710;5711 %val = call double @llvm.amdgcn.trig.preop.f64(double 3.454350e+02, i32 2)5712 ret double %val5713}5714 5715; src1[4:0] <= 21 for segment to be inbound with this exponent of src0.5716define double @trig_preop_constfold_outbound_segment() {5717; CHECK-LABEL: @trig_preop_constfold_outbound_segment(5718; CHECK-NEXT: ret double 0.000000e+005719;5720 %val = call double @llvm.amdgcn.trig.preop.f64(double 3.454350e+02, i32 22)5721 ret double %val5722}5723 5724; Only use src1[4:0], so segment is actually 31 for -1.5725define double @trig_preop_constfold_neg1_segment() {5726; CHECK-LABEL: @trig_preop_constfold_neg1_segment(5727; CHECK-NEXT: ret double 0.000000e+005728;5729 %val = call double @llvm.amdgcn.trig.preop.f64(double 3.454350e+02, i32 -1)5730 ret double %val5731}5732 5733; Only use src1[4:0], so segment is actually 0 for -32.5734define double @trig_preop_constfold_neg32_segment() {5735; CHECK-LABEL: @trig_preop_constfold_neg32_segment(5736; CHECK-NEXT: ret double 0x3FE45F306DC9C8825737;5738 %val = call double @llvm.amdgcn.trig.preop.f64(double 3.454350e+02, i32 -32)5739 ret double %val5740}5741 5742define double @trig_preop_constfold_strictfp() strictfp {5743; CHECK-LABEL: @trig_preop_constfold_strictfp(5744; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 3.454350e+02, i32 5) #[[ATTR19]]5745; CHECK-NEXT: ret double [[VAL]]5746;5747 %val = call double @llvm.amdgcn.trig.preop.f64(double 3.454350e+02, i32 5) strictfp5748 ret double %val5749}5750 5751define double @trig_preop_constfold_exponent0_mantissa0__segment0() {5752; CHECK-LABEL: @trig_preop_constfold_exponent0_mantissa0__segment0(5753; CHECK-NEXT: ret double 0x3FE45F306DC9C8825754;5755 %val = call double @llvm.amdgcn.trig.preop.f64(double 0.0, i32 0)5756 ret double %val5757}5758 5759define double @trig_preop_constfold_exponent0_mantissa1__segment0() {5760; CHECK-LABEL: @trig_preop_constfold_exponent0_mantissa1__segment0(5761; CHECK-NEXT: ret double 0x3FE45F306DC9C8825762;5763 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x000FFFFFFFFFFFFF, i32 0)5764 ret double %val5765}5766 5767define double @trig_preop_constfold_exponent0_mantissaX__segment0() {5768; CHECK-LABEL: @trig_preop_constfold_exponent0_mantissaX__segment0(5769; CHECK-NEXT: ret double 0x3FE45F306DC9C8825770;5771 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x0004A7F09D5F47D4, i32 0)5772 ret double %val5773}5774 5775define double @trig_preop_constfold_exponent0_mantissa0__segment2() {5776; CHECK-LABEL: @trig_preop_constfold_exponent0_mantissa0__segment2(5777; CHECK-NEXT: ret double 0x394A6EE06DB14ACC5778;5779 %val = call double @llvm.amdgcn.trig.preop.f64(double 0.0, i32 2)5780 ret double %val5781}5782 5783define double @trig_preop_constfold_exponent0_mantissa1__segment2() {5784; CHECK-LABEL: @trig_preop_constfold_exponent0_mantissa1__segment2(5785; CHECK-NEXT: ret double 0x394A6EE06DB14ACC5786;5787 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x000FFFFFFFFFFFFF, i32 2)5788 ret double %val5789}5790 5791define double @trig_preop_constfold_exponent0_mantissaX__segment2() {5792; CHECK-LABEL: @trig_preop_constfold_exponent0_mantissaX__segment2(5793; CHECK-NEXT: ret double 0x394A6EE06DB14ACC5794;5795 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x00094A6EE06DB14A, i32 2)5796 ret double %val5797}5798 5799; src1[4:0] <= 21 for segment to be inbound with this exponent of src0.5800define double @trig_preop_constfold_exponent0_mantissa0__outbound_segment() {5801; CHECK-LABEL: @trig_preop_constfold_exponent0_mantissa0__outbound_segment(5802; CHECK-NEXT: ret double 0.000000e+005803;5804 %val = call double @llvm.amdgcn.trig.preop.f64(double 0.0, i32 22)5805 ret double %val5806}5807 5808; src1[4:0] <= 21 for segment to be inbound with this exponent of src0.5809define double @trig_preop_constfold_exponent0_mantissa1__outbound_segment() {5810; CHECK-LABEL: @trig_preop_constfold_exponent0_mantissa1__outbound_segment(5811; CHECK-NEXT: ret double 0.000000e+005812;5813 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x000FFFFFFFFFFFFF, i32 22)5814 ret double %val5815}5816 5817; src1[4:0] <= 21 for segment to be inbound with this exponent of src0.5818define double @trig_preop_constfold_exponent0_mantissaX__outbound_segment() {5819; CHECK-LABEL: @trig_preop_constfold_exponent0_mantissaX__outbound_segment(5820; CHECK-NEXT: ret double 0.000000e+005821;5822 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x000A6EE06DB14ACC, i32 22)5823 ret double %val5824}5825 5826; 1607 = 1077 + 10 * 535827define double @trig_preop_constfold_exponent1607_mantissa0__segment0() {5828; CHECK-LABEL: @trig_preop_constfold_exponent1607_mantissa0__segment0(5829; CHECK-NEXT: ret double 0x1EC8135A2FBF209C5830;5831 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x6470000000000000, i32 0)5832 ret double %val5833}5834 5835; 1607 = 1077 + 10 * 535836define double @trig_preop_constfold_exponent1607_mantissa1__segment1() {5837; CHECK-LABEL: @trig_preop_constfold_exponent1607_mantissa1__segment1(5838; CHECK-NEXT: ret double 0x1EC8135A2FBF209C5839;5840 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x647FFFFFFFFFFFFF, i32 0)5841 ret double %val5842}5843 5844; 1607 = 1077 + 10 * 535845define double @trig_preop_constfold_exponent1607_mantissaX__segment1() {5846; CHECK-LABEL: @trig_preop_constfold_exponent1607_mantissaX__segment1(5847; CHECK-NEXT: ret double 0x1EC8135A2FBF209C5848;5849 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x6471B791D6398353, i32 0)5850 ret double %val5851}5852 5853; 1607 = 1077 + 10 * 535854define double @trig_preop_constfold_exponent1607_mantissa0__segment2() {5855; CHECK-LABEL: @trig_preop_constfold_exponent1607_mantissa0__segment2(5856; CHECK-NEXT: ret double 0x181272117E2EF7E45857;5858 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x6470000000000000, i32 2)5859 ret double %val5860}5861 5862; 1607 = 1077 + 10 * 535863define double @trig_preop_constfold_exponent1607_mantissa1__segment2() {5864; CHECK-LABEL: @trig_preop_constfold_exponent1607_mantissa1__segment2(5865; CHECK-NEXT: ret double 0x181272117E2EF7E45866;5867 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x647FFFFFFFFFFFFF, i32 2)5868 ret double %val5869}5870 5871; 1607 = 1077 + 10 * 535872define double @trig_preop_constfold_exponent1607_mantissaX__segment2() {5873; CHECK-LABEL: @trig_preop_constfold_exponent1607_mantissaX__segment2(5874; CHECK-NEXT: ret double 0x181272117E2EF7E45875;5876 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x647272117E2EF7E4, i32 2)5877 ret double %val5878}5879 5880; src1[4:0] <= 11 for segment to be inbound with this exponent of src0.5881define double @trig_preop_constfold_exponent1607_mantissa0__outbound_segment() {5882; CHECK-LABEL: @trig_preop_constfold_exponent1607_mantissa0__outbound_segment(5883; CHECK-NEXT: ret double 0.000000e+005884;5885 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x6470000000000000, i32 12)5886 ret double %val5887}5888 5889; src1[4:0] <= 11 for segment to be inbound with this exponent of src0.5890define double @trig_preop_constfold_exponent1607_mantissa1__outbound_segment() {5891; CHECK-LABEL: @trig_preop_constfold_exponent1607_mantissa1__outbound_segment(5892; CHECK-NEXT: ret double 0.000000e+005893;5894 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x647FFFFFFFFFFFFF, i32 12)5895 ret double %val5896}5897 5898; src1[4:0] <= 11 for segment to be inbound with this exponent of src0.5899define double @trig_preop_constfold_exponent1607_mantissaX__outbound_segment() {5900; CHECK-LABEL: @trig_preop_constfold_exponent1607_mantissaX__outbound_segment(5901; CHECK-NEXT: ret double 0.000000e+005902;5903 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x647181272117E2EF, i32 12)5904 ret double %val5905}5906 5907define double @trig_preop_constfold_exponent1968_mantissa0__segment0() {5908; CHECK-LABEL: @trig_preop_constfold_exponent1968_mantissa0__segment0(5909; CHECK-NEXT: ret double 0x10374F463F669E5F5910;5911 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x7B00000000000000, i32 0)5912 ret double %val5913}5914 5915define double @trig_preop_constfold_exponent1968_mantissa1__segment0() {5916; CHECK-LABEL: @trig_preop_constfold_exponent1968_mantissa1__segment0(5917; CHECK-NEXT: ret double 0x10374F463F669E5F5918;5919 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x7B0FFFFFFFFFFFFF, i32 0)5920 ret double %val5921}5922 5923define double @trig_preop_constfold_exponent1968_mantissax__segment0() {5924; CHECK-LABEL: @trig_preop_constfold_exponent1968_mantissax__segment0(5925; CHECK-NEXT: ret double 0x10374F463F669E5F5926;5927 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x7B074F463F669E5F, i32 0)5928 ret double %val5929}5930 5931define double @trig_preop_constfold_exponent1968_mantissa0__segment2() {5932; CHECK-LABEL: @trig_preop_constfold_exponent1968_mantissa0__segment2(5933; CHECK-NEXT: ret double 0x98F2F8BD9E839CE5934;5935 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x7B00000000000000, i32 2)5936 ret double %val5937}5938 5939define double @trig_preop_constfold_exponent1968_mantissa1__segment2() {5940; CHECK-LABEL: @trig_preop_constfold_exponent1968_mantissa1__segment2(5941; CHECK-NEXT: ret double 0x98F2F8BD9E839CE5942;5943 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x7B0FFFFFFFFFFFFF, i32 2)5944 ret double %val5945}5946 5947define double @trig_preop_constfold_exponent1968_mantissaX__segment2() {5948; CHECK-LABEL: @trig_preop_constfold_exponent1968_mantissaX__segment2(5949; CHECK-NEXT: ret double 0x98F2F8BD9E839CE5950;5951 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x7B0A2F8BD9E839CE, i32 2)5952 ret double %val5953}5954 5955; src1[4:0] <= 4 for segment to be inbound with this exponent of src0.5956define double @trig_preop_constfold_exponent1968_mantissa0__outbound_segment() {5957; CHECK-LABEL: @trig_preop_constfold_exponent1968_mantissa0__outbound_segment(5958; CHECK-NEXT: ret double 0.000000e+005959;5960 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x7B00000000000000, i32 5)5961 ret double %val5962}5963 5964; src1[4:0] <= 4 for segment to be inbound with this exponent of src0.5965define double @trig_preop_constfold_exponent1968_mantissa1__outbound_segment() {5966; CHECK-LABEL: @trig_preop_constfold_exponent1968_mantissa1__outbound_segment(5967; CHECK-NEXT: ret double 0.000000e+005968;5969 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x7B0FFFFFFFFFFFFF, i32 5)5970 ret double %val5971}5972 5973; src1[4:0] <= 4 for segment to be inbound with this exponent of src0.5974define double @trig_preop_constfold_exponent1968_mantissaX__outbound_segment() {5975; CHECK-LABEL: @trig_preop_constfold_exponent1968_mantissaX__outbound_segment(5976; CHECK-NEXT: ret double 0.000000e+005977;5978 %val = call double @llvm.amdgcn.trig.preop.f64(double 0x7B0A98F2F8BD9E83, i32 5)5979 ret double %val5980}5981 5982; --------------------------------------------------------------------5983; llvm.amdgcn.log5984; --------------------------------------------------------------------5985 5986declare float @llvm.amdgcn.log.f32(float) nounwind readnone5987declare half @llvm.amdgcn.log.f16(half) nounwind readnone5988 5989define float @test_constant_fold_log_f32_undef() {5990; CHECK-LABEL: @test_constant_fold_log_f32_undef(5991; CHECK-NEXT: ret float 0x7FF80000000000005992;5993 %val = call float @llvm.amdgcn.log.f32(float undef)5994 ret float %val5995}5996 5997define float @test_constant_fold_log_f32_poison() {5998; CHECK-LABEL: @test_constant_fold_log_f32_poison(5999; CHECK-NEXT: ret float poison6000;6001 %val = call float @llvm.amdgcn.log.f32(float poison)6002 ret float %val6003}6004 6005define float @test_constant_fold_log_f32_p0() {6006; CHECK-LABEL: @test_constant_fold_log_f32_p0(6007; CHECK-NEXT: ret float 0xFFF00000000000006008;6009 %val = call float @llvm.amdgcn.log.f32(float 0.0)6010 ret float %val6011}6012 6013define float @test_constant_fold_log_f32_n0() {6014; CHECK-LABEL: @test_constant_fold_log_f32_n0(6015; CHECK-NEXT: ret float 0xFFF00000000000006016;6017 %val = call float @llvm.amdgcn.log.f32(float -0.0)6018 ret float %val6019}6020 6021define float @test_constant_fold_log_f32_subnormal() {6022; CHECK-LABEL: @test_constant_fold_log_f32_subnormal(6023; CHECK-NEXT: ret float 0xFFF00000000000006024;6025 %val = call float @llvm.amdgcn.log.f32(float 0x380FFFFFC0000000)6026 ret float %val6027}6028 6029define float @test_constant_fold_log_f32_negsubnormal() {6030; CHECK-LABEL: @test_constant_fold_log_f32_negsubnormal(6031; CHECK-NEXT: ret float 0xFFF00000000000006032;6033 %val = call float @llvm.amdgcn.log.f32(float 0xB80FFFFFC0000000)6034 ret float %val6035}6036 6037define float @test_constant_fold_log_f32_pinf() {6038; CHECK-LABEL: @test_constant_fold_log_f32_pinf(6039; CHECK-NEXT: ret float 0x7FF00000000000006040;6041 %val = call float @llvm.amdgcn.log.f32(float 0x7FF0000000000000)6042 ret float %val6043}6044 6045define float @test_constant_fold_log_f32_ninf() {6046; CHECK-LABEL: @test_constant_fold_log_f32_ninf(6047; CHECK-NEXT: ret float 0x7FF80000000000006048;6049 %val = call float @llvm.amdgcn.log.f32(float 0xFFF0000000000000)6050 ret float %val6051}6052 6053define float @test_constant_fold_log_f32_p1() {6054; CHECK-LABEL: @test_constant_fold_log_f32_p1(6055; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.log.f32(float 1.000000e+00)6056; CHECK-NEXT: ret float [[VAL]]6057;6058 %val = call float @llvm.amdgcn.log.f32(float 1.0)6059 ret float %val6060}6061 6062define float @test_constant_fold_log_f32_p10() {6063; CHECK-LABEL: @test_constant_fold_log_f32_p10(6064; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.log.f32(float 1.000000e+01)6065; CHECK-NEXT: ret float [[VAL]]6066;6067 %val = call float @llvm.amdgcn.log.f32(float 10.0)6068 ret float %val6069}6070 6071define float @test_constant_fold_log_f32_neg10() {6072; CHECK-LABEL: @test_constant_fold_log_f32_neg10(6073; CHECK-NEXT: ret float 0x7FF80000000000006074;6075 %val = call float @llvm.amdgcn.log.f32(float -10.0)6076 ret float %val6077}6078 6079define float @test_constant_fold_log_f32_qnan() {6080; CHECK-LABEL: @test_constant_fold_log_f32_qnan(6081; CHECK-NEXT: ret float 0x7FF80000000000006082;6083 %val = call float @llvm.amdgcn.log.f32(float 0x7FF8000000000000)6084 ret float %val6085}6086 6087define float @test_constant_fold_log_f32_snan() {6088; CHECK-LABEL: @test_constant_fold_log_f32_snan(6089; CHECK-NEXT: ret float 0x7FF80000200000006090;6091 %val = call float @llvm.amdgcn.log.f32(float 0x7FF0000020000000)6092 ret float %val6093}6094 6095define half @test_constant_fold_log_f16_p0() {6096; CHECK-LABEL: @test_constant_fold_log_f16_p0(6097; CHECK-NEXT: ret half 0xHFC006098;6099 %val = call half @llvm.amdgcn.log.f16(half 0.0)6100 ret half %val6101}6102 6103define half @test_constant_fold_log_f16_neg10() {6104; CHECK-LABEL: @test_constant_fold_log_f16_neg10(6105; CHECK-NEXT: ret half 0xH7E006106;6107 %val = call half @llvm.amdgcn.log.f16(half -10.0)6108 ret half %val6109}6110 6111define float @test_constant_fold_log_f32_qnan_strictfp() strictfp {6112; CHECK-LABEL: @test_constant_fold_log_f32_qnan_strictfp(6113; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.log.f32(float 0x7FF8000000000000) #[[ATTR19]]6114; CHECK-NEXT: ret float [[VAL]]6115;6116 %val = call float @llvm.amdgcn.log.f32(float 0x7FF8000000000000) strictfp6117 ret float %val6118}6119 6120define float @test_constant_fold_log_f32_0_strictfp() strictfp {6121; CHECK-LABEL: @test_constant_fold_log_f32_0_strictfp(6122; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.log.f32(float 0.000000e+00) #[[ATTR19]]6123; CHECK-NEXT: ret float [[VAL]]6124;6125 %val = call float @llvm.amdgcn.log.f32(float 0.0) strictfp6126 ret float %val6127}6128 6129define float @test_constant_fold_log_f32_neg0_strictfp() strictfp {6130; CHECK-LABEL: @test_constant_fold_log_f32_neg0_strictfp(6131; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.log.f32(float -0.000000e+00) #[[ATTR19]]6132; CHECK-NEXT: ret float [[VAL]]6133;6134 %val = call float @llvm.amdgcn.log.f32(float -0.0) strictfp6135 ret float %val6136}6137 6138define float @test_constant_fold_log_f32_neg_strictfp() strictfp {6139; CHECK-LABEL: @test_constant_fold_log_f32_neg_strictfp(6140; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.log.f32(float -1.000000e+01) #[[ATTR19]]6141; CHECK-NEXT: ret float [[VAL]]6142;6143 %val = call float @llvm.amdgcn.log.f32(float -10.0) strictfp6144 ret float %val6145}6146 6147define float @test_constant_fold_log_f32_pinf_strictfp() strictfp {6148; CHECK-LABEL: @test_constant_fold_log_f32_pinf_strictfp(6149; CHECK-NEXT: ret float 0x7FF00000000000006150;6151 %val = call float @llvm.amdgcn.log.f32(float 0x7FF0000000000000) strictfp6152 ret float %val6153}6154 6155define float @test_constant_fold_log_f32_ninf_strictfp() strictfp {6156; CHECK-LABEL: @test_constant_fold_log_f32_ninf_strictfp(6157; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.log.f32(float 0xFFF0000000000000) #[[ATTR19]]6158; CHECK-NEXT: ret float [[VAL]]6159;6160 %val = call float @llvm.amdgcn.log.f32(float 0xFFF0000000000000) strictfp6161 ret float %val6162}6163 6164define half @test_constant_fold_log_f16_denorm() {6165; CHECK-LABEL: @test_constant_fold_log_f16_denorm(6166; CHECK-NEXT: [[VAL:%.*]] = call half @llvm.amdgcn.log.f16(half 0xH03FF)6167; CHECK-NEXT: ret half [[VAL]]6168;6169 %val = call half @llvm.amdgcn.log.f16(half 0xH03ff)6170 ret half %val6171}6172 6173define half @test_constant_fold_log_f16_neg_denorm() {6174; CHECK-LABEL: @test_constant_fold_log_f16_neg_denorm(6175; CHECK-NEXT: ret half 0xH7E006176;6177 %val = call half @llvm.amdgcn.log.f16(half 0xH83ff)6178 ret half %val6179}6180 6181; --------------------------------------------------------------------6182; llvm.amdgcn.exp26183; --------------------------------------------------------------------6184 6185declare float @llvm.amdgcn.exp2.f32(float) nounwind readnone6186declare half @llvm.amdgcn.exp2.f16(half) nounwind readnone6187 6188define float @test_constant_fold_exp2_f32_undef() {6189; CHECK-LABEL: @test_constant_fold_exp2_f32_undef(6190; CHECK-NEXT: ret float 0x7FF80000000000006191;6192 %val = call float @llvm.amdgcn.exp2.f32(float undef)6193 ret float %val6194}6195 6196define float @test_constant_fold_exp2_f32_poison() {6197; CHECK-LABEL: @test_constant_fold_exp2_f32_poison(6198; CHECK-NEXT: ret float poison6199;6200 %val = call float @llvm.amdgcn.exp2.f32(float poison)6201 ret float %val6202}6203 6204define float @test_constant_fold_exp2_f32_p0() {6205; CHECK-LABEL: @test_constant_fold_exp2_f32_p0(6206; CHECK-NEXT: ret float 1.000000e+006207;6208 %val = call float @llvm.amdgcn.exp2.f32(float 0.0)6209 ret float %val6210}6211 6212define float @test_constant_fold_exp2_f32_n0() {6213; CHECK-LABEL: @test_constant_fold_exp2_f32_n0(6214; CHECK-NEXT: ret float 1.000000e+006215;6216 %val = call float @llvm.amdgcn.exp2.f32(float -0.0)6217 ret float %val6218}6219 6220define float @test_constant_fold_exp2_f32_p1() {6221; CHECK-LABEL: @test_constant_fold_exp2_f32_p1(6222; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float 1.000000e+00)6223; CHECK-NEXT: ret float [[VAL]]6224;6225 %val = call float @llvm.amdgcn.exp2.f32(float 1.0)6226 ret float %val6227}6228 6229define float @test_constant_fold_exp2_f32_n1() {6230; CHECK-LABEL: @test_constant_fold_exp2_f32_n1(6231; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float -1.000000e+00)6232; CHECK-NEXT: ret float [[VAL]]6233;6234 %val = call float @llvm.amdgcn.exp2.f32(float -1.0)6235 ret float %val6236}6237 6238define float @test_constant_fold_exp2_f32_p2() {6239; CHECK-LABEL: @test_constant_fold_exp2_f32_p2(6240; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float 2.000000e+00)6241; CHECK-NEXT: ret float [[VAL]]6242;6243 %val = call float @llvm.amdgcn.exp2.f32(float 2.0)6244 ret float %val6245}6246 6247define float @test_constant_fold_exp2_f32_n2() {6248; CHECK-LABEL: @test_constant_fold_exp2_f32_n2(6249; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float -2.000000e+00)6250; CHECK-NEXT: ret float [[VAL]]6251;6252 %val = call float @llvm.amdgcn.exp2.f32(float -2.0)6253 ret float %val6254}6255 6256define float @test_constant_fold_exp2_f32_p4() {6257; CHECK-LABEL: @test_constant_fold_exp2_f32_p4(6258; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float 4.000000e+00)6259; CHECK-NEXT: ret float [[VAL]]6260;6261 %val = call float @llvm.amdgcn.exp2.f32(float 4.0)6262 ret float %val6263}6264 6265define float @test_constant_fold_exp2_f32_n4() {6266; CHECK-LABEL: @test_constant_fold_exp2_f32_n4(6267; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float -4.000000e+00)6268; CHECK-NEXT: ret float [[VAL]]6269;6270 %val = call float @llvm.amdgcn.exp2.f32(float -4.0)6271 ret float %val6272}6273 6274define float @test_constant_fold_exp2_f32_subnormal() {6275; CHECK-LABEL: @test_constant_fold_exp2_f32_subnormal(6276; CHECK-NEXT: ret float 1.000000e+006277;6278 %val = call float @llvm.amdgcn.exp2.f32(float 0x380FFFFFC0000000)6279 ret float %val6280}6281 6282define float @test_constant_fold_exp2_f32_negsubnormal() {6283; CHECK-LABEL: @test_constant_fold_exp2_f32_negsubnormal(6284; CHECK-NEXT: ret float 1.000000e+006285;6286 %val = call float @llvm.amdgcn.exp2.f32(float 0xB80FFFFFC0000000)6287 ret float %val6288}6289 6290define float @test_constant_fold_exp2_f32_pinf() {6291; CHECK-LABEL: @test_constant_fold_exp2_f32_pinf(6292; CHECK-NEXT: ret float 0x7FF00000000000006293;6294 %val = call float @llvm.amdgcn.exp2.f32(float 0x7FF0000000000000)6295 ret float %val6296}6297 6298define float @test_constant_fold_exp2_f32_ninf() {6299; CHECK-LABEL: @test_constant_fold_exp2_f32_ninf(6300; CHECK-NEXT: ret float 0.000000e+006301;6302 %val = call float @llvm.amdgcn.exp2.f32(float 0xFFF0000000000000)6303 ret float %val6304}6305 6306define float @test_constant_fold_exp2_f32_p10() {6307; CHECK-LABEL: @test_constant_fold_exp2_f32_p10(6308; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float 1.000000e+01)6309; CHECK-NEXT: ret float [[VAL]]6310;6311 %val = call float @llvm.amdgcn.exp2.f32(float 10.0)6312 ret float %val6313}6314 6315define float @test_constant_fold_exp2_f32_neg10() {6316; CHECK-LABEL: @test_constant_fold_exp2_f32_neg10(6317; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float -1.000000e+01)6318; CHECK-NEXT: ret float [[VAL]]6319;6320 %val = call float @llvm.amdgcn.exp2.f32(float -10.0)6321 ret float %val6322}6323 6324define float @test_constant_fold_exp2_f32_qnan() {6325; CHECK-LABEL: @test_constant_fold_exp2_f32_qnan(6326; CHECK-NEXT: ret float 0x7FF80000000000006327;6328 %val = call float @llvm.amdgcn.exp2.f32(float 0x7FF8000000000000)6329 ret float %val6330}6331 6332define float @test_constant_fold_exp2_f32_snan() {6333; CHECK-LABEL: @test_constant_fold_exp2_f32_snan(6334; CHECK-NEXT: ret float 0x7FF80000200000006335;6336 %val = call float @llvm.amdgcn.exp2.f32(float 0x7FF0000020000000)6337 ret float %val6338}6339 6340define half @test_constant_fold_exp2_f16_p0() {6341; CHECK-LABEL: @test_constant_fold_exp2_f16_p0(6342; CHECK-NEXT: ret half 0xH3C006343;6344 %val = call half @llvm.amdgcn.exp2.f16(half 0.0)6345 ret half %val6346}6347 6348define half @test_constant_fold_exp2_f16_neg10() {6349; CHECK-LABEL: @test_constant_fold_exp2_f16_neg10(6350; CHECK-NEXT: [[VAL:%.*]] = call half @llvm.amdgcn.exp2.f16(half 0xHC900)6351; CHECK-NEXT: ret half [[VAL]]6352;6353 %val = call half @llvm.amdgcn.exp2.f16(half -10.0)6354 ret half %val6355}6356 6357define float @test_constant_fold_exp2_f32_qnan_strictfp() strictfp {6358; CHECK-LABEL: @test_constant_fold_exp2_f32_qnan_strictfp(6359; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float 0x7FF8000000000000) #[[ATTR19]]6360; CHECK-NEXT: ret float [[VAL]]6361;6362 %val = call float @llvm.amdgcn.exp2.f32(float 0x7FF8000000000000) strictfp6363 ret float %val6364}6365 6366define float @test_constant_fold_exp2_f32_0_strictfp() strictfp {6367; CHECK-LABEL: @test_constant_fold_exp2_f32_0_strictfp(6368; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float 0.000000e+00) #[[ATTR19]]6369; CHECK-NEXT: ret float [[VAL]]6370;6371 %val = call float @llvm.amdgcn.exp2.f32(float 0.0) strictfp6372 ret float %val6373}6374 6375define float @test_constant_fold_exp2_f32_neg0_strictfp() strictfp {6376; CHECK-LABEL: @test_constant_fold_exp2_f32_neg0_strictfp(6377; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float -0.000000e+00) #[[ATTR19]]6378; CHECK-NEXT: ret float [[VAL]]6379;6380 %val = call float @llvm.amdgcn.exp2.f32(float -0.0) strictfp6381 ret float %val6382}6383 6384define float @test_constant_fold_exp2_f32_1_strictfp() strictfp {6385; CHECK-LABEL: @test_constant_fold_exp2_f32_1_strictfp(6386; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float 1.000000e+00) #[[ATTR19]]6387; CHECK-NEXT: ret float [[VAL]]6388;6389 %val = call float @llvm.amdgcn.exp2.f32(float 1.0) strictfp6390 ret float %val6391}6392 6393define float @test_constant_fold_exp2_f32_neg1_strictfp() strictfp {6394; CHECK-LABEL: @test_constant_fold_exp2_f32_neg1_strictfp(6395; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float -1.000000e+00) #[[ATTR19]]6396; CHECK-NEXT: ret float [[VAL]]6397;6398 %val = call float @llvm.amdgcn.exp2.f32(float -1.0) strictfp6399 ret float %val6400}6401 6402define float @test_constant_fold_exp2_f32_2_strictfp() strictfp {6403; CHECK-LABEL: @test_constant_fold_exp2_f32_2_strictfp(6404; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float 2.000000e+00) #[[ATTR19]]6405; CHECK-NEXT: ret float [[VAL]]6406;6407 %val = call float @llvm.amdgcn.exp2.f32(float 2.0) strictfp6408 ret float %val6409}6410 6411define float @test_constant_fold_exp2_f32_neg2_strictfp() strictfp {6412; CHECK-LABEL: @test_constant_fold_exp2_f32_neg2_strictfp(6413; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float -2.000000e+00) #[[ATTR19]]6414; CHECK-NEXT: ret float [[VAL]]6415;6416 %val = call float @llvm.amdgcn.exp2.f32(float -2.0) strictfp6417 ret float %val6418}6419 6420define float @test_constant_fold_exp2_f32_neg_strictfp() strictfp {6421; CHECK-LABEL: @test_constant_fold_exp2_f32_neg_strictfp(6422; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float -1.000000e+01) #[[ATTR19]]6423; CHECK-NEXT: ret float [[VAL]]6424;6425 %val = call float @llvm.amdgcn.exp2.f32(float -10.0) strictfp6426 ret float %val6427}6428 6429define float @test_constant_fold_exp2_f32_pinf_strictfp() strictfp {6430; CHECK-LABEL: @test_constant_fold_exp2_f32_pinf_strictfp(6431; CHECK-NEXT: ret float 0x7FF00000000000006432;6433 %val = call float @llvm.amdgcn.exp2.f32(float 0x7FF0000000000000) strictfp6434 ret float %val6435}6436 6437define float @test_constant_fold_exp2_f32_ninf_strictfp() strictfp {6438; CHECK-LABEL: @test_constant_fold_exp2_f32_ninf_strictfp(6439; CHECK-NEXT: ret float 0.000000e+006440;6441 %val = call float @llvm.amdgcn.exp2.f32(float 0xFFF0000000000000) strictfp6442 ret float %val6443}6444 6445define half @test_constant_fold_exp2_f16_denorm() {6446; CHECK-LABEL: @test_constant_fold_exp2_f16_denorm(6447; CHECK-NEXT: [[VAL:%.*]] = call half @llvm.amdgcn.exp2.f16(half 0xH03FF)6448; CHECK-NEXT: ret half [[VAL]]6449;6450 %val = call half @llvm.amdgcn.exp2.f16(half 0xH03ff)6451 ret half %val6452}6453 6454define half @test_constant_fold_exp2_f16_neg_denorm() {6455; CHECK-LABEL: @test_constant_fold_exp2_f16_neg_denorm(6456; CHECK-NEXT: [[VAL:%.*]] = call half @llvm.amdgcn.exp2.f16(half 0xH83FF)6457; CHECK-NEXT: ret half [[VAL]]6458;6459 %val = call half @llvm.amdgcn.exp2.f16(half 0xH83ff)6460 ret half %val6461}6462 6463; --------------------------------------------------------------------6464; llvm.amdgcn.prng6465; --------------------------------------------------------------------6466declare i32 @llvm.amdgcn.prng.b32(i32)6467define i32 @prng_undef_i32() {6468; CHECK-LABEL: @prng_undef_i32(6469; CHECK-NEXT: ret i32 undef6470;6471 %prng = call i32 @llvm.amdgcn.prng.b32(i32 undef)6472 ret i32 %prng6473}6474 6475define i32 @prng_poison_i32() {6476; CHECK-LABEL: @prng_poison_i32(6477; CHECK-NEXT: ret i32 poison6478;6479 %prng = call i32 @llvm.amdgcn.prng.b32(i32 poison)6480 ret i32 %prng6481}6482 6483; --------------------------------------------------------------------6484; llvm.amdgcn.ds.bpermute6485; --------------------------------------------------------------------6486 6487define void @ds_bpermute_uniform_src(ptr addrspace(1) %out, i32 %lane) {6488; CHECK-LABEL: @ds_bpermute_uniform_src(6489; CHECK-NEXT: store i32 7, ptr addrspace(1) [[OUT:%.*]], align 46490; CHECK-NEXT: ret void6491;6492 %v = call i32 @llvm.amdgcn.ds.bpermute(i32 %lane, i32 7)6493 store i32 %v, ptr addrspace(1) %out6494 ret void6495}6496 6497define void @ds_bpermute_constant_lane(ptr addrspace(1) %out, i32 %src) {6498; CHECK-LABEL: @ds_bpermute_constant_lane(6499; CHECK-NEXT: [[V:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[SRC:%.*]], i32 7)6500; CHECK-NEXT: store i32 [[V]], ptr addrspace(1) [[OUT:%.*]], align 46501; CHECK-NEXT: ret void6502;6503 %v = call i32 @llvm.amdgcn.ds.bpermute(i32 28, i32 %src)6504 store i32 %v, ptr addrspace(1) %out6505 ret void6506}6507 6508define void @ds_bpermute_uniform_lane(ptr addrspace(1) %out, i32 %lanearg, i32 %src) {6509; CHECK-LABEL: @ds_bpermute_uniform_lane(6510; CHECK-NEXT: [[LANE:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[LANEARG:%.*]])6511; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[LANE]], 26512; CHECK-NEXT: [[V:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[SRC:%.*]], i32 [[TMP1]])6513; CHECK-NEXT: store i32 [[V]], ptr addrspace(1) [[OUT:%.*]], align 46514; CHECK-NEXT: ret void6515;6516 %lane = call i32 @llvm.amdgcn.readfirstlane(i32 %lanearg)6517 %v = call i32 @llvm.amdgcn.ds.bpermute(i32 %lane, i32 %src)6518 store i32 %v, ptr addrspace(1) %out6519 ret void6520}6521 6522; --------------------------------------------------------------------6523; llvm.amdgcn.make.buffer.rsrc.p86524; --------------------------------------------------------------------6525 6526define ptr addrspace(8) @make_buffer_rsrc_poison() {6527; CHECK-LABEL: @make_buffer_rsrc_poison(6528; CHECK-NEXT: ret ptr addrspace(8) poison6529;6530 %rsrc = call ptr addrspace(8) @llvm.amdgcn.make.buffer.rsrc.p8.p1(ptr addrspace(1) poison, i16 0, i64 1234, i32 5678)6531 ret ptr addrspace(8) %rsrc6532}6533 6534define ptr addrspace(8) @make_buffer_rsrc_undef() {6535; CHECK-LABEL: @make_buffer_rsrc_undef(6536; CHECK-NEXT: [[RSRC:%.*]] = call ptr addrspace(8) @llvm.amdgcn.make.buffer.rsrc.p8.p1(ptr addrspace(1) undef, i16 0, i64 1234, i32 5678)6537; CHECK-NEXT: ret ptr addrspace(8) [[RSRC]]6538;6539 %rsrc = call ptr addrspace(8) @llvm.amdgcn.make.buffer.rsrc.p8.p1(ptr addrspace(1) undef, i16 0, i64 1234, i32 5678)6540 ret ptr addrspace(8) %rsrc6541}6542