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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -passes=instcombine -S < %s | FileCheck %s3 4define i32 @test_bitcast_f32_to_i32_readfirstlane(float %val) {5; CHECK-LABEL: define i32 @test_bitcast_f32_to_i32_readfirstlane(6; CHECK-SAME: float [[VAL:%.*]]) #[[ATTR0:[0-9]+]] {7; CHECK-NEXT: [[RESULT1:%.*]] = call float @llvm.amdgcn.readfirstlane.f32(float [[VAL]])8; CHECK-NEXT: [[RESULT:%.*]] = bitcast float [[RESULT1]] to i329; CHECK-NEXT: ret i32 [[RESULT]]10;11 %bitcast = bitcast float %val to i3212 %result = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %bitcast)13 ret i32 %result14}15 16define i32 @test_bitcast_f32_to_i32_readfirstlane_multi_use_store(float %val, ptr %use.ptr) {17; CHECK-LABEL: define i32 @test_bitcast_f32_to_i32_readfirstlane_multi_use_store(18; CHECK-SAME: float [[VAL:%.*]], ptr [[USE_PTR:%.*]]) #[[ATTR0]] {19; CHECK-NEXT: store float [[VAL]], ptr [[USE_PTR]], align 420; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.amdgcn.readfirstlane.f32(float [[VAL]])21; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[RESULT]] to i3222; CHECK-NEXT: ret i32 [[TMP1]]23;24 %bitcast = bitcast float %val to i3225 store i32 %bitcast, ptr %use.ptr26 %result = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %bitcast)27 ret i32 %result28}29 30declare void @use.i32(i32)31 32define i32 @test_bitcast_f32_to_i32_readfirstlane_multi_use_call(float %val) {33; CHECK-LABEL: define i32 @test_bitcast_f32_to_i32_readfirstlane_multi_use_call(34; CHECK-SAME: float [[VAL:%.*]]) #[[ATTR0]] {35; CHECK-NEXT: [[BITCAST:%.*]] = bitcast float [[VAL]] to i3236; CHECK-NEXT: call void @use.i32(i32 [[BITCAST]])37; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[BITCAST]])38; CHECK-NEXT: ret i32 [[TMP1]]39;40 %bitcast = bitcast float %val to i3241 call void @use.i32(i32 %bitcast)42 %result = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %bitcast)43 ret i32 %result44}45 46define float @test_bitcast_f32_to_i32_readfirstlane_bitcast(float %val) {47; CHECK-LABEL: define float @test_bitcast_f32_to_i32_readfirstlane_bitcast(48; CHECK-SAME: float [[VAL:%.*]]) #[[ATTR0]] {49; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.amdgcn.readfirstlane.f32(float [[VAL]])50; CHECK-NEXT: ret float [[RESULT]]51;52 %bitcast = bitcast float %val to i3253 %call = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %bitcast)54 %result = bitcast i32 %call to float55 ret float %result56}57 58define i32 @test_bitcast_v2f16_to_i32_readfirstlane(<2 x half> %val) {59; CHECK-LABEL: define i32 @test_bitcast_v2f16_to_i32_readfirstlane(60; CHECK-SAME: <2 x half> [[VAL:%.*]]) #[[ATTR0]] {61; CHECK-NEXT: [[RESULT1:%.*]] = call <2 x half> @llvm.amdgcn.readfirstlane.v2f16(<2 x half> [[VAL]])62; CHECK-NEXT: [[RESULT:%.*]] = bitcast <2 x half> [[RESULT1]] to i3263; CHECK-NEXT: ret i32 [[RESULT]]64;65 %bitcast = bitcast <2 x half> %val to i3266 %result = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %bitcast)67 ret i32 %result68}69 70define i32 @test_bitcast_v2bf16_to_i32_readfirstlane(<2 x bfloat> %val) {71; CHECK-LABEL: define i32 @test_bitcast_v2bf16_to_i32_readfirstlane(72; CHECK-SAME: <2 x bfloat> [[VAL:%.*]]) #[[ATTR0]] {73; CHECK-NEXT: [[RESULT1:%.*]] = call <2 x bfloat> @llvm.amdgcn.readfirstlane.v2bf16(<2 x bfloat> [[VAL]])74; CHECK-NEXT: [[RESULT:%.*]] = bitcast <2 x bfloat> [[RESULT1]] to i3275; CHECK-NEXT: ret i32 [[RESULT]]76;77 %bitcast = bitcast <2 x bfloat> %val to i3278 %result = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %bitcast)79 ret i32 %result80}81 82define i64 @test_bitcast_f64_to_i64_readfirstlane(double %val) {83; CHECK-LABEL: define i64 @test_bitcast_f64_to_i64_readfirstlane(84; CHECK-SAME: double [[VAL:%.*]]) #[[ATTR0]] {85; CHECK-NEXT: [[RESULT1:%.*]] = call double @llvm.amdgcn.readfirstlane.f64(double [[VAL]])86; CHECK-NEXT: [[RESULT:%.*]] = bitcast double [[RESULT1]] to i6487; CHECK-NEXT: ret i64 [[RESULT]]88;89 %bitcast = bitcast double %val to i6490 %result = call i64 @llvm.amdgcn.readfirstlane.i64(i64 %bitcast)91 ret i64 %result92}93 94define <2 x i32> @test_bitcast_f64_to_v2i32_readfirstlane(double %val) {95; CHECK-LABEL: define <2 x i32> @test_bitcast_f64_to_v2i32_readfirstlane(96; CHECK-SAME: double [[VAL:%.*]]) #[[ATTR0]] {97; CHECK-NEXT: [[RESULT1:%.*]] = call double @llvm.amdgcn.readfirstlane.f64(double [[VAL]])98; CHECK-NEXT: [[RESULT:%.*]] = bitcast double [[RESULT1]] to <2 x i32>99; CHECK-NEXT: ret <2 x i32> [[RESULT]]100;101 %bitcast = bitcast double %val to <2 x i32>102 %result = call <2 x i32> @llvm.amdgcn.readfirstlane.v2i32(<2 x i32> %bitcast)103 ret <2 x i32> %result104}105 106define i64 @test_bitcast_v4i16_to_i64_readfirstlane(<4 x i16> %val) {107; CHECK-LABEL: define i64 @test_bitcast_v4i16_to_i64_readfirstlane(108; CHECK-SAME: <4 x i16> [[VAL:%.*]]) #[[ATTR0]] {109; CHECK-NEXT: [[RESULT1:%.*]] = call <4 x i16> @llvm.amdgcn.readfirstlane.v4i16(<4 x i16> [[VAL]])110; CHECK-NEXT: [[RESULT:%.*]] = bitcast <4 x i16> [[RESULT1]] to i64111; CHECK-NEXT: ret i64 [[RESULT]]112;113 %bitcast = bitcast <4 x i16> %val to i64114 %result = call i64 @llvm.amdgcn.readfirstlane.i64(i64 %bitcast)115 ret i64 %result116}117 118 119define i32 @test_bitcast_v4i8_to_i32_readfirstlane(<4 x i8> %val) {120; CHECK-LABEL: define i32 @test_bitcast_v4i8_to_i32_readfirstlane(121; CHECK-SAME: <4 x i8> [[VAL:%.*]]) #[[ATTR0]] {122; CHECK-NEXT: [[BITCAST:%.*]] = bitcast <4 x i8> [[VAL]] to i32123; CHECK-NEXT: [[RESULT:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[BITCAST]])124; CHECK-NEXT: ret i32 [[RESULT]]125;126 %bitcast = bitcast <4 x i8> %val to i32127 %result = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %bitcast)128 ret i32 %result129}130 131define i32 @test_bitcast_v8i4_to_i32_readfirstlane(<8 x i4> %val) {132; CHECK-LABEL: define i32 @test_bitcast_v8i4_to_i32_readfirstlane(133; CHECK-SAME: <8 x i4> [[VAL:%.*]]) #[[ATTR0]] {134; CHECK-NEXT: [[BITCAST:%.*]] = bitcast <8 x i4> [[VAL]] to i32135; CHECK-NEXT: [[RESULT:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[BITCAST]])136; CHECK-NEXT: ret i32 [[RESULT]]137;138 %bitcast = bitcast <8 x i4> %val to i32139 %result = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %bitcast)140 ret i32 %result141}142 143define float @test_bitcast_i32_to_f32_readfirstlane(i32 %val) {144; CHECK-LABEL: define float @test_bitcast_i32_to_f32_readfirstlane(145; CHECK-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] {146; CHECK-NEXT: [[RESULT1:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[VAL]])147; CHECK-NEXT: [[RESULT:%.*]] = bitcast i32 [[RESULT1]] to float148; CHECK-NEXT: ret float [[RESULT]]149;150 %bitcast = bitcast i32 %val to float151 %result = call float @llvm.amdgcn.readfirstlane.f32(float %bitcast)152 ret float %result153}154 155define i16 @test_bitcast_f16_to_i16_readfirstlane(half %val) {156; CHECK-LABEL: define i16 @test_bitcast_f16_to_i16_readfirstlane(157; CHECK-SAME: half [[VAL:%.*]]) #[[ATTR0]] {158; CHECK-NEXT: [[RESULT1:%.*]] = call half @llvm.amdgcn.readfirstlane.f16(half [[VAL]])159; CHECK-NEXT: [[RESULT:%.*]] = bitcast half [[RESULT1]] to i16160; CHECK-NEXT: ret i16 [[RESULT]]161;162 %bitcast = bitcast half %val to i16163 %result = call i16 @llvm.amdgcn.readfirstlane.i16(i16 %bitcast)164 ret i16 %result165}166 167define i16 @test_bitcast_v2i8_to_i16_readfirstlane(<2 x i8> %val) {168; CHECK-LABEL: define i16 @test_bitcast_v2i8_to_i16_readfirstlane(169; CHECK-SAME: <2 x i8> [[VAL:%.*]]) #[[ATTR0]] {170; CHECK-NEXT: [[BITCAST:%.*]] = bitcast <2 x i8> [[VAL]] to i16171; CHECK-NEXT: [[RESULT:%.*]] = call i16 @llvm.amdgcn.readfirstlane.i16(i16 [[BITCAST]])172; CHECK-NEXT: ret i16 [[RESULT]]173;174 %bitcast = bitcast <2 x i8> %val to i16175 %result = call i16 @llvm.amdgcn.readfirstlane.i16(i16 %bitcast)176 ret i16 %result177}178 179define <16 x i32> @test_bitcast_v16f32_to_v16i32_readfirstlane(<16 x float> %val) {180; CHECK-LABEL: define <16 x i32> @test_bitcast_v16f32_to_v16i32_readfirstlane(181; CHECK-SAME: <16 x float> [[VAL:%.*]]) #[[ATTR0]] {182; CHECK-NEXT: [[RESULT:%.*]] = call <16 x float> @llvm.amdgcn.readfirstlane.v16f32(<16 x float> [[VAL]])183; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x float> [[RESULT]] to <16 x i32>184; CHECK-NEXT: ret <16 x i32> [[TMP1]]185;186 %bitcast = bitcast <16 x float> %val to <16 x i32>187 %result = call <16 x i32> @llvm.amdgcn.readfirstlane.v16i32(<16 x i32> %bitcast)188 ret <16 x i32> %result189}190 191define <8 x i64> @test_bitcast_v16f32_to_v8i64_readfirstlane(<16 x float> %val) {192; CHECK-LABEL: define <8 x i64> @test_bitcast_v16f32_to_v8i64_readfirstlane(193; CHECK-SAME: <16 x float> [[VAL:%.*]]) #[[ATTR0]] {194; CHECK-NEXT: [[RESULT:%.*]] = call <16 x float> @llvm.amdgcn.readfirstlane.v16f32(<16 x float> [[VAL]])195; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x float> [[RESULT]] to <8 x i64>196; CHECK-NEXT: ret <8 x i64> [[TMP1]]197;198 %bitcast = bitcast <16 x float> %val to <8 x i64>199 %result = call <8 x i64> @llvm.amdgcn.readfirstlane.v8i64(<8 x i64> %bitcast)200 ret <8 x i64> %result201}202 203define i32 @test_bitcast_f32_to_i32_readlane(float %val, i32 inreg %lane.index) {204; CHECK-LABEL: define i32 @test_bitcast_f32_to_i32_readlane(205; CHECK-SAME: float [[VAL:%.*]], i32 inreg [[LANE_INDEX:%.*]]) #[[ATTR0]] {206; CHECK-NEXT: [[RESULT1:%.*]] = call float @llvm.amdgcn.readlane.f32(float [[VAL]], i32 [[LANE_INDEX]])207; CHECK-NEXT: [[RESULT:%.*]] = bitcast float [[RESULT1]] to i32208; CHECK-NEXT: ret i32 [[RESULT]]209;210 %bitcast = bitcast float %val to i32211 %result = call i32 @llvm.amdgcn.readlane.i32(i32 %bitcast, i32 %lane.index)212 ret i32 %result213}214 215define i32 @test_bitcast_f32_to_i32_writelane_samesourcetype(float %val0, i32 inreg %lane.index, float %val1) {216; CHECK-LABEL: define i32 @test_bitcast_f32_to_i32_writelane_samesourcetype(217; CHECK-SAME: float [[VAL0:%.*]], i32 inreg [[LANE_INDEX:%.*]], float [[VAL1:%.*]]) #[[ATTR0]] {218; CHECK-NEXT: [[BITCAST0:%.*]] = bitcast float [[VAL0]] to i32219; CHECK-NEXT: [[BITCAST1:%.*]] = bitcast float [[VAL1]] to i32220; CHECK-NEXT: [[RESULT:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[BITCAST0]], i32 [[LANE_INDEX]], i32 [[BITCAST1]])221; CHECK-NEXT: ret i32 [[RESULT]]222;223 %bitcast0 = bitcast float %val0 to i32224 %bitcast1 = bitcast float %val1 to i32225 %result = call i32 @llvm.amdgcn.writelane.i32(i32 %bitcast0, i32 %lane.index, i32 %bitcast1)226 ret i32 %result227}228 229define i32 @test_bitcast_f32_to_i32_writelane_diffsourcetype(float %val0, i32 inreg %lane.index, <2 x half> %val1) {230; CHECK-LABEL: define i32 @test_bitcast_f32_to_i32_writelane_diffsourcetype(231; CHECK-SAME: float [[VAL0:%.*]], i32 inreg [[LANE_INDEX:%.*]], <2 x half> [[VAL1:%.*]]) #[[ATTR0]] {232; CHECK-NEXT: [[BITCAST0:%.*]] = bitcast float [[VAL0]] to i32233; CHECK-NEXT: [[BITCAST1:%.*]] = bitcast <2 x half> [[VAL1]] to i32234; CHECK-NEXT: [[RESULT:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[BITCAST0]], i32 [[LANE_INDEX]], i32 [[BITCAST1]])235; CHECK-NEXT: ret i32 [[RESULT]]236;237 %bitcast0 = bitcast float %val0 to i32238 %bitcast1 = bitcast <2 x half> %val1 to i32239 %result = call i32 @llvm.amdgcn.writelane.i32(i32 %bitcast0, i32 %lane.index, i32 %bitcast1)240 ret i32 %result241}242 243define i32 @test_bitcast_update_dpp_f32_to_i32(float %val0, float %val1) {244; CHECK-LABEL: define i32 @test_bitcast_update_dpp_f32_to_i32(245; CHECK-SAME: float [[VAL0:%.*]], float [[VAL1:%.*]]) #[[ATTR0]] {246; CHECK-NEXT: [[BITCAST0:%.*]] = bitcast float [[VAL0]] to i32247; CHECK-NEXT: [[BITCAST1:%.*]] = bitcast float [[VAL1]] to i32248; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 [[BITCAST0]], i32 [[BITCAST1]], i32 1, i32 1, i32 1, i1 false)249; CHECK-NEXT: ret i32 [[TMP0]]250;251 %bitcast0 = bitcast float %val0 to i32252 %bitcast1 = bitcast float %val1 to i32253 %dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 %bitcast0, i32 %bitcast1, i32 1, i32 1, i32 1, i1 false)254 ret i32 %dpp255}256 257define i32 @test_bitcast_update_dpp_f32_to_i32_convergencetoken(float %val0, float %val1) convergent {258; CHECK-LABEL: define i32 @test_bitcast_update_dpp_f32_to_i32_convergencetoken(259; CHECK-SAME: float [[VAL0:%.*]], float [[VAL1:%.*]]) #[[ATTR1:[0-9]+]] {260; CHECK-NEXT: [[T:%.*]] = call token @llvm.experimental.convergence.entry()261; CHECK-NEXT: [[BITCAST0:%.*]] = bitcast float [[VAL0]] to i32262; CHECK-NEXT: [[BITCAST1:%.*]] = bitcast float [[VAL1]] to i32263; CHECK-NEXT: [[DPP:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 [[BITCAST0]], i32 [[BITCAST1]], i32 1, i32 1, i32 1, i1 false) [ "convergencectrl"(token [[T]]) ]264; CHECK-NEXT: ret i32 [[DPP]]265;266 %t = call token @llvm.experimental.convergence.entry()267 %bitcast0 = bitcast float %val0 to i32268 %bitcast1 = bitcast float %val1 to i32269 %dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 %bitcast0, i32 %bitcast1, i32 1, i32 1, i32 1, i1 false) [ "convergencectrl"(token %t) ]270 ret i32 %dpp271}272 273define i32 @test_bitcast_update_dpp_sources_different_type(float %val0, <2 x half> %val1) {274; CHECK-LABEL: define i32 @test_bitcast_update_dpp_sources_different_type(275; CHECK-SAME: float [[VAL0:%.*]], <2 x half> [[VAL1:%.*]]) #[[ATTR0]] {276; CHECK-NEXT: [[BITCAST0:%.*]] = bitcast float [[VAL0]] to i32277; CHECK-NEXT: [[BITCAST1:%.*]] = bitcast <2 x half> [[VAL1]] to i32278; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 [[BITCAST0]], i32 [[BITCAST1]], i32 1, i32 1, i32 1, i1 false)279; CHECK-NEXT: ret i32 [[TMP0]]280;281 %bitcast0 = bitcast float %val0 to i32282 %bitcast1 = bitcast <2 x half> %val1 to i32283 %dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 %bitcast0, i32 %bitcast1, i32 1, i32 1, i32 1, i1 false)284 ret i32 %dpp285}286 287define i32 @test_bitcast_f32_to_i32_readfirstlane_convergencetoken(float %val) convergent {288; CHECK-LABEL: define i32 @test_bitcast_f32_to_i32_readfirstlane_convergencetoken(289; CHECK-SAME: float [[VAL:%.*]]) #[[ATTR1]] {290; CHECK-NEXT: [[T:%.*]] = call token @llvm.experimental.convergence.entry()291; CHECK-NEXT: [[RESULT1:%.*]] = call float @llvm.amdgcn.readfirstlane.f32(float [[VAL]]) [ "convergencectrl"(token [[T]]) ]292; CHECK-NEXT: [[RESULT:%.*]] = bitcast float [[RESULT1]] to i32293; CHECK-NEXT: ret i32 [[RESULT]]294;295 %t = call token @llvm.experimental.convergence.entry()296 %bitcast = bitcast float %val to i32297 %result = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %bitcast) [ "convergencectrl"(token %t) ]298 ret i32 %result299}300 301define i32 @test_bitcast_f32_to_i32_readlane_convergencetoken(float %val, i32 inreg %lane.index) convergent {302; CHECK-LABEL: define i32 @test_bitcast_f32_to_i32_readlane_convergencetoken(303; CHECK-SAME: float [[VAL:%.*]], i32 inreg [[LANE_INDEX:%.*]]) #[[ATTR1]] {304; CHECK-NEXT: [[T:%.*]] = call token @llvm.experimental.convergence.entry()305; CHECK-NEXT: [[RESULT1:%.*]] = call float @llvm.amdgcn.readlane.f32(float [[VAL]], i32 [[LANE_INDEX]]) [ "convergencectrl"(token [[T]]) ]306; CHECK-NEXT: [[RESULT:%.*]] = bitcast float [[RESULT1]] to i32307; CHECK-NEXT: ret i32 [[RESULT]]308;309 %t = call token @llvm.experimental.convergence.entry()310 %bitcast = bitcast float %val to i32311 %result = call i32 @llvm.amdgcn.readlane.i32(i32 %bitcast, i32 %lane.index) [ "convergencectrl"(token %t) ]312 ret i32 %result313}314 315define i32 @test_bitcast_f32_to_i32_ds_bpermute(float %val, i32 %addr) {316; CHECK-LABEL: define i32 @test_bitcast_f32_to_i32_ds_bpermute(317; CHECK-SAME: float [[VAL:%.*]], i32 [[ADDR:%.*]]) #[[ATTR0]] {318; CHECK-NEXT: [[BITCAST:%.*]] = bitcast float [[VAL]] to i32319; CHECK-NEXT: [[RESULT:%.*]] = call i32 @llvm.amdgcn.ds.bpermute(i32 [[ADDR]], i32 [[BITCAST]])320; CHECK-NEXT: ret i32 [[RESULT]]321;322 %bitcast = bitcast float %val to i32323 %result = call i32 @llvm.amdgcn.ds.bpermute(i32 %addr, i32 %bitcast)324 ret i32 %result325}326