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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx700 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX7 %s3; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx810 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX81PLUS %s4; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx900 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX81PLUS %s5; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx1010 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX81PLUS %s6; RUN: opt -mtriple=amdgcn--amdpal -mcpu=gfx1100 -S -passes=instcombine %s | FileCheck --check-prefixes=GFX81PLUS %s7 8define amdgpu_ps half @image_sample_2d_fptrunc_to_d16(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {9; GFX7-LABEL: @image_sample_2d_fptrunc_to_d16(10; GFX7-NEXT: main_body:11; GFX7-NEXT: [[TEX:%.*]] = call float @llvm.amdgcn.image.sample.lz.2d.f32.f32.v8i32.v4i32(i32 1, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)12; GFX7-NEXT: [[TEX_HALF:%.*]] = fptrunc float [[TEX]] to half13; GFX7-NEXT: ret half [[TEX_HALF]]14;15; GFX81PLUS-LABEL: @image_sample_2d_fptrunc_to_d16(16; GFX81PLUS-NEXT: main_body:17; GFX81PLUS-NEXT: [[TEX:%.*]] = call half @llvm.amdgcn.image.sample.lz.2d.f16.f32.v8i32.v4i32(i32 1, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)18; GFX81PLUS-NEXT: ret half [[TEX]]19;20main_body:21 %tex = call float @llvm.amdgcn.image.sample.lz.2d.f32.f32.v8i32.v4i32(i32 1, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)22 %tex_half = fptrunc float %tex to half23 ret half %tex_half24}25 26define amdgpu_ps half @image_sample_2d_v2f32(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {27; GFX7-LABEL: @image_sample_2d_v2f32(28; GFX7-NEXT: main_body:29; GFX7-NEXT: [[TEX:%.*]] = call <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32.v8i32.v4i32(i32 3, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)30; GFX7-NEXT: [[TEX_2_HALF:%.*]] = fptrunc <2 x float> [[TEX]] to <2 x half>31; GFX7-NEXT: [[TEX_HALF_0:%.*]] = extractelement <2 x half> [[TEX_2_HALF]], i64 032; GFX7-NEXT: [[TEX_HALF_1:%.*]] = extractelement <2 x half> [[TEX_2_HALF]], i64 133; GFX7-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]34; GFX7-NEXT: ret half [[ADDF_SUM_0]]35;36; GFX81PLUS-LABEL: @image_sample_2d_v2f32(37; GFX81PLUS-NEXT: main_body:38; GFX81PLUS-NEXT: [[TEX:%.*]] = call <2 x half> @llvm.amdgcn.image.sample.lz.2d.v2f16.f32.v8i32.v4i32(i32 3, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)39; GFX81PLUS-NEXT: [[TEX_HALF_0:%.*]] = extractelement <2 x half> [[TEX]], i64 040; GFX81PLUS-NEXT: [[TEX_HALF_1:%.*]] = extractelement <2 x half> [[TEX]], i64 141; GFX81PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]42; GFX81PLUS-NEXT: ret half [[ADDF_SUM_0]]43;44main_body:45 %tex = call <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32.v8i32.v4i32(i32 3, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)46 %tex_2_half = fptrunc <2 x float> %tex to <2 x half>47 %tex_half_0 = extractelement <2 x half> %tex_2_half, i64 048 %tex_half_1 = extractelement <2 x half> %tex_2_half, i64 149 %addf_sum.0 = fadd half %tex_half_0, %tex_half_150 ret half %addf_sum.051}52 53define amdgpu_ps half @image_sample_2d_v3f32(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {54; GFX7-LABEL: @image_sample_2d_v3f32(55; GFX7-NEXT: main_body:56; GFX7-NEXT: [[TEX:%.*]] = call <3 x float> @llvm.amdgcn.image.sample.lz.2d.v3f32.f32.v8i32.v4i32(i32 7, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)57; GFX7-NEXT: [[TEX_3_HALF:%.*]] = fptrunc <3 x float> [[TEX]] to <3 x half>58; GFX7-NEXT: [[TEX_HALF_0:%.*]] = extractelement <3 x half> [[TEX_3_HALF]], i64 059; GFX7-NEXT: [[TEX_HALF_1:%.*]] = extractelement <3 x half> [[TEX_3_HALF]], i64 160; GFX7-NEXT: [[TEX_HALF_2:%.*]] = extractelement <3 x half> [[TEX_3_HALF]], i64 261; GFX7-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]62; GFX7-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[ADDF_SUM_0]], [[TEX_HALF_2]]63; GFX7-NEXT: ret half [[ADDF_SUM_1]]64;65; GFX81PLUS-LABEL: @image_sample_2d_v3f32(66; GFX81PLUS-NEXT: main_body:67; GFX81PLUS-NEXT: [[TEX:%.*]] = call <3 x half> @llvm.amdgcn.image.sample.lz.2d.v3f16.f32.v8i32.v4i32(i32 7, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)68; GFX81PLUS-NEXT: [[TEX_HALF_0:%.*]] = extractelement <3 x half> [[TEX]], i64 069; GFX81PLUS-NEXT: [[TEX_HALF_1:%.*]] = extractelement <3 x half> [[TEX]], i64 170; GFX81PLUS-NEXT: [[TEX_HALF_2:%.*]] = extractelement <3 x half> [[TEX]], i64 271; GFX81PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]72; GFX81PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[ADDF_SUM_0]], [[TEX_HALF_2]]73; GFX81PLUS-NEXT: ret half [[ADDF_SUM_1]]74;75main_body:76 %tex = call <3 x float> @llvm.amdgcn.image.sample.lz.2d.v3f32.f32.v8i32.v4i32(i32 7, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)77 %tex_3_half = fptrunc <3 x float> %tex to <3 x half>78 %tex_half_0 = extractelement <3 x half> %tex_3_half, i64 079 %tex_half_1 = extractelement <3 x half> %tex_3_half, i64 180 %tex_half_2 = extractelement <3 x half> %tex_3_half, i64 281 %addf_sum.0 = fadd half %tex_half_0, %tex_half_182 %addf_sum.1 = fadd half %addf_sum.0, %tex_half_283 ret half %addf_sum.184}85 86define amdgpu_ps half @image_sample_2d_v4f32(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {87; GFX7-LABEL: @image_sample_2d_v4f32(88; GFX7-NEXT: main_body:89; GFX7-NEXT: [[TEX:%.*]] = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32.v8i32.v4i32(i32 15, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)90; GFX7-NEXT: [[TEX_4_HALF:%.*]] = fptrunc <4 x float> [[TEX]] to <4 x half>91; GFX7-NEXT: [[TEX_HALF_0:%.*]] = extractelement <4 x half> [[TEX_4_HALF]], i64 092; GFX7-NEXT: [[TEX_HALF_1:%.*]] = extractelement <4 x half> [[TEX_4_HALF]], i64 193; GFX7-NEXT: [[TEX_HALF_2:%.*]] = extractelement <4 x half> [[TEX_4_HALF]], i64 294; GFX7-NEXT: [[TEX_HALF_3:%.*]] = extractelement <4 x half> [[TEX_4_HALF]], i64 395; GFX7-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]96; GFX7-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[TEX_HALF_2]], [[TEX_HALF_3]]97; GFX7-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]98; GFX7-NEXT: ret half [[ADDF_SUM_2]]99;100; GFX81PLUS-LABEL: @image_sample_2d_v4f32(101; GFX81PLUS-NEXT: main_body:102; GFX81PLUS-NEXT: [[TEX:%.*]] = call <4 x half> @llvm.amdgcn.image.sample.lz.2d.v4f16.f32.v8i32.v4i32(i32 15, float [[S:%.*]], float [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)103; GFX81PLUS-NEXT: [[TEX_HALF_0:%.*]] = extractelement <4 x half> [[TEX]], i64 0104; GFX81PLUS-NEXT: [[TEX_HALF_1:%.*]] = extractelement <4 x half> [[TEX]], i64 1105; GFX81PLUS-NEXT: [[TEX_HALF_2:%.*]] = extractelement <4 x half> [[TEX]], i64 2106; GFX81PLUS-NEXT: [[TEX_HALF_3:%.*]] = extractelement <4 x half> [[TEX]], i64 3107; GFX81PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]108; GFX81PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[TEX_HALF_2]], [[TEX_HALF_3]]109; GFX81PLUS-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]110; GFX81PLUS-NEXT: ret half [[ADDF_SUM_2]]111;112main_body:113 %tex = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32.v8i32.v4i32(i32 15, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)114 %tex_4_half = fptrunc <4 x float> %tex to <4 x half>115 %tex_half_0 = extractelement <4 x half> %tex_4_half, i64 0116 %tex_half_1 = extractelement <4 x half> %tex_4_half, i64 1117 %tex_half_2 = extractelement <4 x half> %tex_4_half, i64 2118 %tex_half_3 = extractelement <4 x half> %tex_4_half, i64 3119 %addf_sum.0 = fadd half %tex_half_0, %tex_half_1120 %addf_sum.1 = fadd half %tex_half_2, %tex_half_3121 %addf_sum.2 = fadd half %addf_sum.0, %addf_sum.1122 ret half %addf_sum.2123}124 125define amdgpu_ps half @image_sample_2d_multi_fptrunc_to_d16(<8 x i32> %surf_desc, <4 x i32> %samp, float %u, float %v) {126; GFX7-LABEL: @image_sample_2d_multi_fptrunc_to_d16(127; GFX7-NEXT: main_body:128; GFX7-NEXT: [[SAMPLE:%.*]] = call <3 x float> @llvm.amdgcn.image.sample.lz.2d.v3f32.f32.v8i32.v4i32(i32 7, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)129; GFX7-NEXT: [[E0:%.*]] = extractelement <3 x float> [[SAMPLE]], i64 0130; GFX7-NEXT: [[H0:%.*]] = fptrunc float [[E0]] to half131; GFX7-NEXT: [[E1:%.*]] = extractelement <3 x float> [[SAMPLE]], i64 1132; GFX7-NEXT: [[H1:%.*]] = fptrunc float [[E1]] to half133; GFX7-NEXT: [[E2:%.*]] = extractelement <3 x float> [[SAMPLE]], i64 2134; GFX7-NEXT: [[H2:%.*]] = fptrunc float [[E2]] to half135; GFX7-NEXT: [[MUL:%.*]] = fmul half [[H0]], [[H1]]136; GFX7-NEXT: [[RES:%.*]] = fadd half [[MUL]], [[H2]]137; GFX7-NEXT: ret half [[RES]]138;139; GFX81PLUS-LABEL: @image_sample_2d_multi_fptrunc_to_d16(140; GFX81PLUS-NEXT: main_body:141; GFX81PLUS-NEXT: [[SAMPLE:%.*]] = call <3 x half> @llvm.amdgcn.image.sample.lz.2d.v3f16.f32.v8i32.v4i32(i32 7, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)142; GFX81PLUS-NEXT: [[H0:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 0143; GFX81PLUS-NEXT: [[H1:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 1144; GFX81PLUS-NEXT: [[H2:%.*]] = extractelement <3 x half> [[SAMPLE]], i64 2145; GFX81PLUS-NEXT: [[MUL:%.*]] = fmul half [[H0]], [[H1]]146; GFX81PLUS-NEXT: [[RES:%.*]] = fadd half [[MUL]], [[H2]]147; GFX81PLUS-NEXT: ret half [[RES]]148;149main_body:150 %sample = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32.v8i32.v4i32(i32 15, float %u, float %v, <8 x i32> %surf_desc, <4 x i32> %samp, i1 false, i32 0, i32 0)151 %e0 = extractelement <4 x float> %sample, i32 0152 %h0 = fptrunc float %e0 to half153 %e1 = extractelement <4 x float> %sample, i32 1154 %h1 = fptrunc float %e1 to half155 %e2 = extractelement <4 x float> %sample, i32 2156 %h2 = fptrunc float %e2 to half157 %mul = fmul half %h0, %h1158 %res = fadd half %mul, %h2159 ret half %res160}161 162define amdgpu_ps half @image_sample_2d_extractelement_multi_use_no_d16(<8 x i32> %surf_desc, <4 x i32> %sampler_desc, float %u, float %v) {163; GFX7-LABEL: @image_sample_2d_extractelement_multi_use_no_d16(164; GFX7-NEXT: main_body:165; GFX7-NEXT: [[SAMPLE:%.*]] = call <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32.v8i32.v4i32(i32 3, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMPLER_DESC:%.*]], i1 false, i32 0, i32 0)166; GFX7-NEXT: [[E0:%.*]] = extractelement <2 x float> [[SAMPLE]], i64 0167; GFX7-NEXT: [[H0:%.*]] = fptrunc float [[E0]] to half168; GFX7-NEXT: [[USER2:%.*]] = fadd float [[E0]], 1.000000e+00169; GFX7-NEXT: [[HALF:%.*]] = fptrunc float [[USER2]] to half170; GFX7-NEXT: [[E1:%.*]] = extractelement <2 x float> [[SAMPLE]], i64 1171; GFX7-NEXT: [[H1:%.*]] = fptrunc float [[E1]] to half172; GFX7-NEXT: [[MUL:%.*]] = fmul half [[H0]], [[H1]]173; GFX7-NEXT: [[RES:%.*]] = fadd half [[MUL]], [[HALF]]174; GFX7-NEXT: ret half [[RES]]175;176; GFX81PLUS-LABEL: @image_sample_2d_extractelement_multi_use_no_d16(177; GFX81PLUS-NEXT: main_body:178; GFX81PLUS-NEXT: [[SAMPLE:%.*]] = call <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32.v8i32.v4i32(i32 3, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMPLER_DESC:%.*]], i1 false, i32 0, i32 0)179; GFX81PLUS-NEXT: [[E0:%.*]] = extractelement <2 x float> [[SAMPLE]], i64 0180; GFX81PLUS-NEXT: [[H0:%.*]] = fptrunc float [[E0]] to half181; GFX81PLUS-NEXT: [[USER2:%.*]] = fadd float [[E0]], 1.000000e+00182; GFX81PLUS-NEXT: [[HALF:%.*]] = fptrunc float [[USER2]] to half183; GFX81PLUS-NEXT: [[E1:%.*]] = extractelement <2 x float> [[SAMPLE]], i64 1184; GFX81PLUS-NEXT: [[H1:%.*]] = fptrunc float [[E1]] to half185; GFX81PLUS-NEXT: [[MUL:%.*]] = fmul half [[H0]], [[H1]]186; GFX81PLUS-NEXT: [[RES:%.*]] = fadd half [[MUL]], [[HALF]]187; GFX81PLUS-NEXT: ret half [[RES]]188;189main_body:190 %sample = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32.v8i32.v4i32(i32 15, float %u, float %v, <8 x i32> %surf_desc, <4 x i32> %sampler_desc, i1 false, i32 0, i32 0)191 %e0 = extractelement <4 x float> %sample, i32 0192 %h0 = fptrunc float %e0 to half193 %user2 = fadd float %e0, 1.0194 %half = fptrunc float %user2 to half195 %e1 = extractelement <4 x float> %sample, i32 1196 %h1 = fptrunc float %e1 to half197 %mul = fmul half %h0, %h1198 %res = fadd half %mul, %half199 ret half %res200}201 202define amdgpu_ps bfloat @image_sample_2d_multi_fptrunc_non_half_no_d16(<8 x i32> %surf_desc, <4 x i32> %sampler_desc, float %u, float %v) {203; GFX7-LABEL: @image_sample_2d_multi_fptrunc_non_half_no_d16(204; GFX7-NEXT: main_body:205; GFX7-NEXT: [[SAMPLE:%.*]] = call <3 x float> @llvm.amdgcn.image.sample.lz.2d.v3f32.f32.v8i32.v4i32(i32 7, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMPLER_DESC:%.*]], i1 false, i32 0, i32 0)206; GFX7-NEXT: [[E0:%.*]] = extractelement <3 x float> [[SAMPLE]], i64 0207; GFX7-NEXT: [[H0:%.*]] = fptrunc float [[E0]] to bfloat208; GFX7-NEXT: [[E1:%.*]] = extractelement <3 x float> [[SAMPLE]], i64 1209; GFX7-NEXT: [[H1:%.*]] = fptrunc float [[E1]] to bfloat210; GFX7-NEXT: [[E2:%.*]] = extractelement <3 x float> [[SAMPLE]], i64 2211; GFX7-NEXT: [[H2:%.*]] = fptrunc float [[E2]] to bfloat212; GFX7-NEXT: [[MUL:%.*]] = fmul bfloat [[H0]], [[H1]]213; GFX7-NEXT: [[RES:%.*]] = fadd bfloat [[MUL]], [[H2]]214; GFX7-NEXT: ret bfloat [[RES]]215;216; GFX81PLUS-LABEL: @image_sample_2d_multi_fptrunc_non_half_no_d16(217; GFX81PLUS-NEXT: main_body:218; GFX81PLUS-NEXT: [[SAMPLE:%.*]] = call <3 x float> @llvm.amdgcn.image.sample.lz.2d.v3f32.f32.v8i32.v4i32(i32 7, float [[U:%.*]], float [[V:%.*]], <8 x i32> [[SURF_DESC:%.*]], <4 x i32> [[SAMPLER_DESC:%.*]], i1 false, i32 0, i32 0)219; GFX81PLUS-NEXT: [[E0:%.*]] = extractelement <3 x float> [[SAMPLE]], i64 0220; GFX81PLUS-NEXT: [[H0:%.*]] = fptrunc float [[E0]] to bfloat221; GFX81PLUS-NEXT: [[E1:%.*]] = extractelement <3 x float> [[SAMPLE]], i64 1222; GFX81PLUS-NEXT: [[H1:%.*]] = fptrunc float [[E1]] to bfloat223; GFX81PLUS-NEXT: [[E2:%.*]] = extractelement <3 x float> [[SAMPLE]], i64 2224; GFX81PLUS-NEXT: [[H2:%.*]] = fptrunc float [[E2]] to bfloat225; GFX81PLUS-NEXT: [[MUL:%.*]] = fmul bfloat [[H0]], [[H1]]226; GFX81PLUS-NEXT: [[RES:%.*]] = fadd bfloat [[MUL]], [[H2]]227; GFX81PLUS-NEXT: ret bfloat [[RES]]228;229main_body:230 %sample = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32.v8i32.v4i32(i32 15, float %u, float %v, <8 x i32> %surf_desc, <4 x i32> %sampler_desc, i1 false, i32 0, i32 0)231 %e0 = extractelement <4 x float> %sample, i32 0232 %h0 = fptrunc float %e0 to bfloat233 %e1 = extractelement <4 x float> %sample, i32 1234 %h1 = fptrunc float %e1 to bfloat235 %e2 = extractelement <4 x float> %sample, i32 2236 %h2 = fptrunc float %e2 to bfloat237 %mul = fmul bfloat %h0, %h1238 %res = fadd bfloat %mul, %h2239 ret bfloat %res240}241 242define amdgpu_ps half @image_gather4_2d_v4f32(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %s, half %t) {243; GFX7-LABEL: @image_gather4_2d_v4f32(244; GFX7-NEXT: main_body:245; GFX7-NEXT: [[TEX:%.*]] = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f16.v8i32.v4i32(i32 1, half [[S:%.*]], half [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)246; GFX7-NEXT: [[TEX_4_HALF:%.*]] = fptrunc <4 x float> [[TEX]] to <4 x half>247; GFX7-NEXT: [[TEX_HALF_0:%.*]] = extractelement <4 x half> [[TEX_4_HALF]], i64 0248; GFX7-NEXT: [[TEX_HALF_1:%.*]] = extractelement <4 x half> [[TEX_4_HALF]], i64 1249; GFX7-NEXT: [[TEX_HALF_2:%.*]] = extractelement <4 x half> [[TEX_4_HALF]], i64 2250; GFX7-NEXT: [[TEX_HALF_3:%.*]] = extractelement <4 x half> [[TEX_4_HALF]], i64 3251; GFX7-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]252; GFX7-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[TEX_HALF_2]], [[TEX_HALF_3]]253; GFX7-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]254; GFX7-NEXT: ret half [[ADDF_SUM_2]]255;256; GFX81PLUS-LABEL: @image_gather4_2d_v4f32(257; GFX81PLUS-NEXT: main_body:258; GFX81PLUS-NEXT: [[TEX:%.*]] = call <4 x half> @llvm.amdgcn.image.gather4.2d.v4f16.f16.v8i32.v4i32(i32 1, half [[S:%.*]], half [[T:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)259; GFX81PLUS-NEXT: [[TEX_HALF_0:%.*]] = extractelement <4 x half> [[TEX]], i64 0260; GFX81PLUS-NEXT: [[TEX_HALF_1:%.*]] = extractelement <4 x half> [[TEX]], i64 1261; GFX81PLUS-NEXT: [[TEX_HALF_2:%.*]] = extractelement <4 x half> [[TEX]], i64 2262; GFX81PLUS-NEXT: [[TEX_HALF_3:%.*]] = extractelement <4 x half> [[TEX]], i64 3263; GFX81PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[TEX_HALF_0]], [[TEX_HALF_1]]264; GFX81PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[TEX_HALF_2]], [[TEX_HALF_3]]265; GFX81PLUS-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]266; GFX81PLUS-NEXT: ret half [[ADDF_SUM_2]]267;268main_body:269 %tex = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f16.v8i32.v4i32(i32 1, half %s, half %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)270 %tex_4_half = fptrunc <4 x float> %tex to <4 x half>271 %tex_half_0 = extractelement <4 x half> %tex_4_half, i64 0272 %tex_half_1 = extractelement <4 x half> %tex_4_half, i64 1273 %tex_half_2 = extractelement <4 x half> %tex_4_half, i64 2274 %tex_half_3 = extractelement <4 x half> %tex_4_half, i64 3275 %addf_sum.0 = fadd half %tex_half_0, %tex_half_1276 %addf_sum.1 = fadd half %tex_half_2, %tex_half_3277 %addf_sum.2 = fadd half %addf_sum.0, %addf_sum.1278 ret half %addf_sum.2279}280 281define amdgpu_ps half @load_1d(i16 %s, <8 x i32> inreg %rsrc) {282; GFX7-LABEL: @load_1d(283; GFX7-NEXT: [[S_FLOAT:%.*]] = call float @llvm.amdgcn.image.load.1d.f32.i16.v8i32(i32 1, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)284; GFX7-NEXT: [[S_HALF:%.*]] = fptrunc float [[S_FLOAT]] to half285; GFX7-NEXT: ret half [[S_HALF]]286;287; GFX81PLUS-LABEL: @load_1d(288; GFX81PLUS-NEXT: [[S_FLOAT:%.*]] = call half @llvm.amdgcn.image.load.1d.f16.i16.v8i32(i32 1, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)289; GFX81PLUS-NEXT: ret half [[S_FLOAT]]290;291 %s_float = call float @llvm.amdgcn.image.load.1d.f32.i16.v8i32(i32 1, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)292 %s_half = fptrunc float %s_float to half293 ret half %s_half294}295 296define amdgpu_ps half @load_1d_v2(i16 %s, <8 x i32> inreg %rsrc) {297; GFX7-LABEL: @load_1d_v2(298; GFX7-NEXT: [[V2_FLOAT:%.*]] = call <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i16.v8i32(i32 3, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)299; GFX7-NEXT: [[V2_HALF:%.*]] = fptrunc <2 x float> [[V2_FLOAT]] to <2 x half>300; GFX7-NEXT: [[S0:%.*]] = extractelement <2 x half> [[V2_HALF]], i64 0301; GFX7-NEXT: [[S1:%.*]] = extractelement <2 x half> [[V2_HALF]], i64 1302; GFX7-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]303; GFX7-NEXT: ret half [[ADDF_SUM_0]]304;305; GFX81PLUS-LABEL: @load_1d_v2(306; GFX81PLUS-NEXT: [[V2_FLOAT:%.*]] = call <2 x half> @llvm.amdgcn.image.load.1d.v2f16.i16.v8i32(i32 3, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)307; GFX81PLUS-NEXT: [[S0:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 0308; GFX81PLUS-NEXT: [[S1:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 1309; GFX81PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]310; GFX81PLUS-NEXT: ret half [[ADDF_SUM_0]]311;312 %v2_float = call <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i16.v8i32(i32 3, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)313 %v2_half = fptrunc <2 x float> %v2_float to <2 x half>314 %s0 = extractelement <2 x half> %v2_half, i64 0315 %s1 = extractelement <2 x half> %v2_half, i64 1316 %addf_sum.0 = fadd half %s0, %s1317 ret half %addf_sum.0318}319 320define amdgpu_ps half @load_1d_v3(i16 %s, <8 x i32> inreg %rsrc) {321; GFX7-LABEL: @load_1d_v3(322; GFX7-NEXT: [[V3_FLOAT:%.*]] = call <3 x float> @llvm.amdgcn.image.load.1d.v3f32.i16.v8i32(i32 7, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)323; GFX7-NEXT: [[V3_HALF:%.*]] = fptrunc <3 x float> [[V3_FLOAT]] to <3 x half>324; GFX7-NEXT: [[S0:%.*]] = extractelement <3 x half> [[V3_HALF]], i64 0325; GFX7-NEXT: [[S1:%.*]] = extractelement <3 x half> [[V3_HALF]], i64 1326; GFX7-NEXT: [[S2:%.*]] = extractelement <3 x half> [[V3_HALF]], i64 2327; GFX7-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]328; GFX7-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[ADDF_SUM_0]]329; GFX7-NEXT: ret half [[ADDF_SUM_1]]330;331; GFX81PLUS-LABEL: @load_1d_v3(332; GFX81PLUS-NEXT: [[V3_FLOAT:%.*]] = call <3 x half> @llvm.amdgcn.image.load.1d.v3f16.i16.v8i32(i32 7, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)333; GFX81PLUS-NEXT: [[S0:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 0334; GFX81PLUS-NEXT: [[S1:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 1335; GFX81PLUS-NEXT: [[S2:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 2336; GFX81PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]337; GFX81PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[ADDF_SUM_0]]338; GFX81PLUS-NEXT: ret half [[ADDF_SUM_1]]339;340 %v3_float = call <3 x float> @llvm.amdgcn.image.load.1d.v3f32.i16.v8i32(i32 7, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)341 %v3_half = fptrunc <3 x float> %v3_float to <3 x half>342 %s0 = extractelement <3 x half> %v3_half, i64 0343 %s1 = extractelement <3 x half> %v3_half, i64 1344 %s2 = extractelement <3 x half> %v3_half, i64 2345 %addf_sum.0 = fadd half %s0, %s1346 %addf_sum.1 = fadd half %s2, %addf_sum.0347 ret half %addf_sum.1348}349 350define amdgpu_ps half @load_1d_v4(i16 %s, <8 x i32> inreg %rsrc) {351; GFX7-LABEL: @load_1d_v4(352; GFX7-NEXT: [[V4_FLOAT:%.*]] = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16.v8i32(i32 15, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)353; GFX7-NEXT: [[V4_HALF:%.*]] = fptrunc <4 x float> [[V4_FLOAT]] to <4 x half>354; GFX7-NEXT: [[S0:%.*]] = extractelement <4 x half> [[V4_HALF]], i64 0355; GFX7-NEXT: [[S1:%.*]] = extractelement <4 x half> [[V4_HALF]], i64 1356; GFX7-NEXT: [[S2:%.*]] = extractelement <4 x half> [[V4_HALF]], i64 2357; GFX7-NEXT: [[S3:%.*]] = extractelement <4 x half> [[V4_HALF]], i64 3358; GFX7-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]359; GFX7-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[S3]]360; GFX7-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]361; GFX7-NEXT: ret half [[ADDF_SUM_2]]362;363; GFX81PLUS-LABEL: @load_1d_v4(364; GFX81PLUS-NEXT: [[V4_FLOAT:%.*]] = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16.v8i32(i32 15, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)365; GFX81PLUS-NEXT: [[S0:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 0366; GFX81PLUS-NEXT: [[S1:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 1367; GFX81PLUS-NEXT: [[S2:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 2368; GFX81PLUS-NEXT: [[S3:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 3369; GFX81PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]370; GFX81PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[S3]]371; GFX81PLUS-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]372; GFX81PLUS-NEXT: ret half [[ADDF_SUM_2]]373;374 %v4_float = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16.v8i32(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)375 %v4_half = fptrunc <4 x float> %v4_float to <4 x half>376 %s0 = extractelement <4 x half> %v4_half, i64 0377 %s1 = extractelement <4 x half> %v4_half, i64 1378 %s2 = extractelement <4 x half> %v4_half, i64 2379 %s3 = extractelement <4 x half> %v4_half, i64 3380 %addf_sum.0 = fadd half %s0, %s1381 %addf_sum.1 = fadd half %s2, %s3382 %addf_sum.2 = fadd half %addf_sum.0, %addf_sum.1383 ret half %addf_sum.2384}385 386define amdgpu_ps half @load_2dmsaa(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %fragid) {387; GFX7-LABEL: @load_2dmsaa(388; GFX7-NEXT: main_body:389; GFX7-NEXT: [[S_FLOAT:%.*]] = call float @llvm.amdgcn.image.msaa.load.x.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)390; GFX7-NEXT: [[S_HALF:%.*]] = fptrunc float [[S_FLOAT]] to half391; GFX7-NEXT: ret half [[S_HALF]]392;393; GFX81PLUS-LABEL: @load_2dmsaa(394; GFX81PLUS-NEXT: main_body:395; GFX81PLUS-NEXT: [[S_FLOAT:%.*]] = call half @llvm.amdgcn.image.msaa.load.x.2dmsaa.f16.i32.v8i32(i32 1, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)396; GFX81PLUS-NEXT: ret half [[S_FLOAT]]397;398main_body:399 %s_float = call float @llvm.amdgcn.image.msaa.load.x.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)400 %s_half = fptrunc float %s_float to half401 ret half %s_half402}403 404define amdgpu_ps half @load_2dmsaa_v2(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %fragid) {405; GFX7-LABEL: @load_2dmsaa_v2(406; GFX7-NEXT: main_body:407; GFX7-NEXT: [[V2_FLOAT:%.*]] = call <2 x float> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v2f32.i32.v8i32(i32 3, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)408; GFX7-NEXT: [[V2_HALF:%.*]] = fptrunc <2 x float> [[V2_FLOAT]] to <2 x half>409; GFX7-NEXT: [[S0:%.*]] = extractelement <2 x half> [[V2_HALF]], i64 0410; GFX7-NEXT: [[S1:%.*]] = extractelement <2 x half> [[V2_HALF]], i64 1411; GFX7-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]412; GFX7-NEXT: ret half [[ADDF_SUM_0]]413;414; GFX81PLUS-LABEL: @load_2dmsaa_v2(415; GFX81PLUS-NEXT: main_body:416; GFX81PLUS-NEXT: [[V2_FLOAT:%.*]] = call <2 x half> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v2f16.i32.v8i32(i32 3, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)417; GFX81PLUS-NEXT: [[S0:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 0418; GFX81PLUS-NEXT: [[S1:%.*]] = extractelement <2 x half> [[V2_FLOAT]], i64 1419; GFX81PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]420; GFX81PLUS-NEXT: ret half [[ADDF_SUM_0]]421;422main_body:423 %v2_float = call <2 x float> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v2f32.i32.v8i32(i32 3, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)424 %v2_half = fptrunc <2 x float> %v2_float to <2 x half>425 %s0 = extractelement <2 x half> %v2_half, i64 0426 %s1 = extractelement <2 x half> %v2_half, i64 1427 %addf_sum.0 = fadd half %s0, %s1428 ret half %addf_sum.0429}430 431define amdgpu_ps half @load_2dmsaa_v3(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %fragid) {432; GFX7-LABEL: @load_2dmsaa_v3(433; GFX7-NEXT: main_body:434; GFX7-NEXT: [[V3_FLOAT:%.*]] = call <3 x float> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v3f32.i32.v8i32(i32 7, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)435; GFX7-NEXT: [[V3_HALF:%.*]] = fptrunc <3 x float> [[V3_FLOAT]] to <3 x half>436; GFX7-NEXT: [[S0:%.*]] = extractelement <3 x half> [[V3_HALF]], i64 0437; GFX7-NEXT: [[S1:%.*]] = extractelement <3 x half> [[V3_HALF]], i64 1438; GFX7-NEXT: [[S2:%.*]] = extractelement <3 x half> [[V3_HALF]], i64 2439; GFX7-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]440; GFX7-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[ADDF_SUM_0]]441; GFX7-NEXT: ret half [[ADDF_SUM_1]]442;443; GFX81PLUS-LABEL: @load_2dmsaa_v3(444; GFX81PLUS-NEXT: main_body:445; GFX81PLUS-NEXT: [[V3_FLOAT:%.*]] = call <3 x half> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v3f16.i32.v8i32(i32 7, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)446; GFX81PLUS-NEXT: [[S0:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 0447; GFX81PLUS-NEXT: [[S1:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 1448; GFX81PLUS-NEXT: [[S2:%.*]] = extractelement <3 x half> [[V3_FLOAT]], i64 2449; GFX81PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]450; GFX81PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[ADDF_SUM_0]]451; GFX81PLUS-NEXT: ret half [[ADDF_SUM_1]]452;453main_body:454 %v3_float = call <3 x float> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v3f32.i32.v8i32(i32 7, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)455 %v3_half = fptrunc <3 x float> %v3_float to <3 x half>456 %s0 = extractelement <3 x half> %v3_half, i64 0457 %s1 = extractelement <3 x half> %v3_half, i64 1458 %s2 = extractelement <3 x half> %v3_half, i64 2459 %addf_sum.0 = fadd half %s0, %s1460 %addf_sum.1 = fadd half %s2, %addf_sum.0461 ret half %addf_sum.1462}463 464define amdgpu_ps half @load_2dmsaa_v4(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %fragid) {465; GFX7-LABEL: @load_2dmsaa_v4(466; GFX7-NEXT: main_body:467; GFX7-NEXT: [[V4_FLOAT:%.*]] = call <4 x float> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v4f32.i32.v8i32(i32 15, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)468; GFX7-NEXT: [[V4_HALF:%.*]] = fptrunc <4 x float> [[V4_FLOAT]] to <4 x half>469; GFX7-NEXT: [[S0:%.*]] = extractelement <4 x half> [[V4_HALF]], i64 0470; GFX7-NEXT: [[S1:%.*]] = extractelement <4 x half> [[V4_HALF]], i64 1471; GFX7-NEXT: [[S2:%.*]] = extractelement <4 x half> [[V4_HALF]], i64 2472; GFX7-NEXT: [[S3:%.*]] = extractelement <4 x half> [[V4_HALF]], i64 3473; GFX7-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]474; GFX7-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[S3]]475; GFX7-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]476; GFX7-NEXT: ret half [[ADDF_SUM_2]]477;478; GFX81PLUS-LABEL: @load_2dmsaa_v4(479; GFX81PLUS-NEXT: main_body:480; GFX81PLUS-NEXT: [[V4_FLOAT:%.*]] = call <4 x half> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v4f16.i32.v8i32(i32 15, i32 [[S:%.*]], i32 [[T:%.*]], i32 [[FRAGID:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)481; GFX81PLUS-NEXT: [[S0:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 0482; GFX81PLUS-NEXT: [[S1:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 1483; GFX81PLUS-NEXT: [[S2:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 2484; GFX81PLUS-NEXT: [[S3:%.*]] = extractelement <4 x half> [[V4_FLOAT]], i64 3485; GFX81PLUS-NEXT: [[ADDF_SUM_0:%.*]] = fadd half [[S0]], [[S1]]486; GFX81PLUS-NEXT: [[ADDF_SUM_1:%.*]] = fadd half [[S2]], [[S3]]487; GFX81PLUS-NEXT: [[ADDF_SUM_2:%.*]] = fadd half [[ADDF_SUM_0]], [[ADDF_SUM_1]]488; GFX81PLUS-NEXT: ret half [[ADDF_SUM_2]]489;490main_body:491 %v4_float = call <4 x float> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v4f32.i32.v8i32(i32 15, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)492 %v4_half = fptrunc <4 x float> %v4_float to <4 x half>493 %s0 = extractelement <4 x half> %v4_half, i64 0494 %s1 = extractelement <4 x half> %v4_half, i64 1495 %s2 = extractelement <4 x half> %v4_half, i64 2496 %s3 = extractelement <4 x half> %v4_half, i64 3497 %addf_sum.0 = fadd half %s0, %s1498 %addf_sum.1 = fadd half %s2, %s3499 %addf_sum.2 = fadd half %addf_sum.0, %addf_sum.1500 ret half %addf_sum.2501}502 503declare float @llvm.amdgcn.image.sample.lz.2d.f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0504declare <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0505declare <3 x float> @llvm.amdgcn.image.sample.lz.2d.v3f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0506declare <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0507 508declare <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f16(i32, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #0509 510declare float @llvm.amdgcn.image.load.1d.f32.i16(i32, i16, <8 x i32>, i32, i32) #0511declare <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i16(i32, i16, <8 x i32>, i32, i32) #0512declare <3 x float> @llvm.amdgcn.image.load.1d.v3f32.i16(i32, i16, <8 x i32>, i32, i32) #0513declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #0514 515declare float @llvm.amdgcn.image.msaa.load.x.2dmsaa.f32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #0516declare <2 x float> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v2f32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #0517declare <3 x float> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v3f32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #0518declare <4 x float> @llvm.amdgcn.image.msaa.load.x.2dmsaa.v4f32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #0519 520attributes #0 = { nounwind readonly willreturn}521 522