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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=instcombine < %s | FileCheck -check-prefixes=CHECK,WAVE64 %s3; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mattr=+wavefrontsize32 -passes=instcombine < %s | FileCheck -check-prefixes=CHECK,WAVE32 %s4; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mattr=+wavefrontsize64 -passes=instcombine < %s | FileCheck -check-prefixes=CHECK,WAVE64 %s5 6; --------------------------------------------------------------------7; llvm.amdgcn.readlane8; --------------------------------------------------------------------9 10define i32 @readlane_31(i32 %arg) #0 {11; CHECK-LABEL: define i32 @readlane_31(12; CHECK-SAME: i32 [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {13; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 31)14; CHECK-NEXT: ret i32 [[RES]]15;16 %res = call i32 @llvm.amdgcn.readlane.i32(i32 %arg, i32 31)17 ret i32 %res18}19 20define i32 @readlane_32(i32 %arg) #0 {21; WAVE64-LABEL: define i32 @readlane_32(22; WAVE64-SAME: i32 [[ARG:%.*]]) #[[ATTR0]] {23; WAVE64-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 32)24; WAVE64-NEXT: ret i32 [[RES]]25;26; WAVE32-LABEL: define i32 @readlane_32(27; WAVE32-SAME: i32 [[ARG:%.*]]) #[[ATTR0]] {28; WAVE32-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 0)29; WAVE32-NEXT: ret i32 [[RES]]30;31 %res = call i32 @llvm.amdgcn.readlane.i32(i32 %arg, i32 32)32 ret i32 %res33}34 35define i32 @readlane_33(i32 %arg) #0 {36; WAVE64-LABEL: define i32 @readlane_33(37; WAVE64-SAME: i32 [[ARG:%.*]]) #[[ATTR0]] {38; WAVE64-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 33)39; WAVE64-NEXT: ret i32 [[RES]]40;41; WAVE32-LABEL: define i32 @readlane_33(42; WAVE32-SAME: i32 [[ARG:%.*]]) #[[ATTR0]] {43; WAVE32-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 1)44; WAVE32-NEXT: ret i32 [[RES]]45;46 %res = call i32 @llvm.amdgcn.readlane.i32(i32 %arg, i32 33)47 ret i32 %res48}49 50define i32 @readlane_63(i32 %arg) #0 {51; WAVE64-LABEL: define i32 @readlane_63(52; WAVE64-SAME: i32 [[ARG:%.*]]) #[[ATTR0]] {53; WAVE64-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 63)54; WAVE64-NEXT: ret i32 [[RES]]55;56; WAVE32-LABEL: define i32 @readlane_63(57; WAVE32-SAME: i32 [[ARG:%.*]]) #[[ATTR0]] {58; WAVE32-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 31)59; WAVE32-NEXT: ret i32 [[RES]]60;61 %res = call i32 @llvm.amdgcn.readlane.i32(i32 %arg, i32 63)62 ret i32 %res63}64 65define i32 @readlane_64(i32 %arg) #0 {66; CHECK-LABEL: define i32 @readlane_64(67; CHECK-SAME: i32 [[ARG:%.*]]) #[[ATTR0]] {68; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 0)69; CHECK-NEXT: ret i32 [[RES]]70;71 %res = call i32 @llvm.amdgcn.readlane.i32(i32 %arg, i32 64)72 ret i32 %res73}74 75define i32 @readlane_and_31(i32 %arg, i32 %idx) #0 {76; WAVE64-LABEL: define i32 @readlane_and_31(77; WAVE64-SAME: i32 [[ARG:%.*]], i32 [[IDX:%.*]]) #[[ATTR0]] {78; WAVE64-NEXT: [[IDX_CLAMP:%.*]] = and i32 [[IDX]], 3179; WAVE64-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 [[IDX_CLAMP]])80; WAVE64-NEXT: ret i32 [[RES]]81;82; WAVE32-LABEL: define i32 @readlane_and_31(83; WAVE32-SAME: i32 [[ARG:%.*]], i32 [[IDX:%.*]]) #[[ATTR0]] {84; WAVE32-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 [[IDX]])85; WAVE32-NEXT: ret i32 [[RES]]86;87 %idx.clamp = and i32 %idx, 3188 %res = call i32 @llvm.amdgcn.readlane.i32(i32 %arg, i32 %idx.clamp)89 ret i32 %res90}91 92define i32 @readlane_and_63(i32 %arg, i32 %idx) #0 {93; CHECK-LABEL: define i32 @readlane_and_63(94; CHECK-SAME: i32 [[ARG:%.*]], i32 [[IDX:%.*]]) #[[ATTR0]] {95; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 [[IDX]])96; CHECK-NEXT: ret i32 [[RES]]97;98 %idx.clamp = and i32 %idx, 6399 %res = call i32 @llvm.amdgcn.readlane.i32(i32 %arg, i32 %idx.clamp)100 ret i32 %res101}102 103define i32 @readlane_poison(i32 %arg) #0 {104; CHECK-LABEL: define i32 @readlane_poison(105; CHECK-SAME: i32 [[ARG:%.*]]) #[[ATTR0]] {106; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 poison)107; CHECK-NEXT: ret i32 [[RES]]108;109 %res = call i32 @llvm.amdgcn.readlane.i32(i32 %arg, i32 poison)110 ret i32 %res111}112 113define float @readlane_f32_63(float %arg) #0 {114; WAVE64-LABEL: define float @readlane_f32_63(115; WAVE64-SAME: float [[ARG:%.*]]) #[[ATTR0]] {116; WAVE64-NEXT: [[RES:%.*]] = call float @llvm.amdgcn.readlane.f32(float [[ARG]], i32 63)117; WAVE64-NEXT: ret float [[RES]]118;119; WAVE32-LABEL: define float @readlane_f32_63(120; WAVE32-SAME: float [[ARG:%.*]]) #[[ATTR0]] {121; WAVE32-NEXT: [[RES:%.*]] = call float @llvm.amdgcn.readlane.f32(float [[ARG]], i32 31)122; WAVE32-NEXT: ret float [[RES]]123;124 %res = call float @llvm.amdgcn.readlane.f32(float %arg, i32 63)125 ret float %res126}127 128; --------------------------------------------------------------------129; llvm.amdgcn.writelane130; --------------------------------------------------------------------131 132define i32 @writelane_31(i32 %arg0, i32 %arg1) #0 {133; CHECK-LABEL: define i32 @writelane_31(134; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) #[[ATTR0]] {135; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[ARG0]], i32 31, i32 [[ARG1]])136; CHECK-NEXT: ret i32 [[RES]]137;138 %res = call i32 @llvm.amdgcn.writelane.i32(i32 %arg0, i32 31, i32 %arg1)139 ret i32 %res140}141 142define i32 @writelane_32(i32 %arg0, i32 %arg1) #0 {143; WAVE64-LABEL: define i32 @writelane_32(144; WAVE64-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) #[[ATTR0]] {145; WAVE64-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[ARG0]], i32 32, i32 [[ARG1]])146; WAVE64-NEXT: ret i32 [[RES]]147;148; WAVE32-LABEL: define i32 @writelane_32(149; WAVE32-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) #[[ATTR0]] {150; WAVE32-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[ARG0]], i32 0, i32 [[ARG1]])151; WAVE32-NEXT: ret i32 [[RES]]152;153 %res = call i32 @llvm.amdgcn.writelane.i32(i32 %arg0, i32 32, i32 %arg1)154 ret i32 %res155}156 157define i32 @writelane_33(i32 %arg0, i32 %arg1) #0 {158; WAVE64-LABEL: define i32 @writelane_33(159; WAVE64-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) #[[ATTR0]] {160; WAVE64-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[ARG0]], i32 33, i32 [[ARG1]])161; WAVE64-NEXT: ret i32 [[RES]]162;163; WAVE32-LABEL: define i32 @writelane_33(164; WAVE32-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) #[[ATTR0]] {165; WAVE32-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[ARG0]], i32 1, i32 [[ARG1]])166; WAVE32-NEXT: ret i32 [[RES]]167;168 %res = call i32 @llvm.amdgcn.writelane.i32(i32 %arg0, i32 33, i32 %arg1)169 ret i32 %res170}171 172define i32 @writelane_63(i32 %arg0, i32 %arg1) #0 {173; WAVE64-LABEL: define i32 @writelane_63(174; WAVE64-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) #[[ATTR0]] {175; WAVE64-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[ARG0]], i32 63, i32 [[ARG1]])176; WAVE64-NEXT: ret i32 [[RES]]177;178; WAVE32-LABEL: define i32 @writelane_63(179; WAVE32-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) #[[ATTR0]] {180; WAVE32-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[ARG0]], i32 31, i32 [[ARG1]])181; WAVE32-NEXT: ret i32 [[RES]]182;183 %res = call i32 @llvm.amdgcn.writelane.i32(i32 %arg0, i32 63, i32 %arg1)184 ret i32 %res185}186 187define i32 @writelane_64(i32 %arg0, i32 %arg1) #0 {188; CHECK-LABEL: define i32 @writelane_64(189; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) #[[ATTR0]] {190; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[ARG0]], i32 0, i32 [[ARG1]])191; CHECK-NEXT: ret i32 [[RES]]192;193 %res = call i32 @llvm.amdgcn.writelane.i32(i32 %arg0, i32 64, i32 %arg1)194 ret i32 %res195}196 197define i32 @writelane_and_31(i32 %arg0, i32 %arg1, i32 %idx) #0 {198; WAVE64-LABEL: define i32 @writelane_and_31(199; WAVE64-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]], i32 [[IDX:%.*]]) #[[ATTR0]] {200; WAVE64-NEXT: [[IDX_CLAMP:%.*]] = and i32 [[IDX]], 31201; WAVE64-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[ARG0]], i32 [[IDX_CLAMP]], i32 [[ARG1]])202; WAVE64-NEXT: ret i32 [[RES]]203;204; WAVE32-LABEL: define i32 @writelane_and_31(205; WAVE32-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]], i32 [[IDX:%.*]]) #[[ATTR0]] {206; WAVE32-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[ARG0]], i32 [[IDX]], i32 [[ARG1]])207; WAVE32-NEXT: ret i32 [[RES]]208;209 %idx.clamp = and i32 %idx, 31210 %res = call i32 @llvm.amdgcn.writelane.i32(i32 %arg0, i32 %idx.clamp, i32 %arg1)211 ret i32 %res212}213 214define i32 @writelane_and_63(i32 %arg0, i32 %arg1, i32 %idx) #0 {215; CHECK-LABEL: define i32 @writelane_and_63(216; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]], i32 [[IDX:%.*]]) #[[ATTR0]] {217; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[ARG0]], i32 [[IDX]], i32 [[ARG1]])218; CHECK-NEXT: ret i32 [[RES]]219;220 %idx.clamp = and i32 %idx, 63221 %res = call i32 @llvm.amdgcn.writelane.i32(i32 %arg0, i32 %idx.clamp, i32 %arg1)222 ret i32 %res223}224 225define i32 @writelane_poison(i32 %arg0, i32 %arg1) #0 {226; CHECK-LABEL: define i32 @writelane_poison(227; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) #[[ATTR0]] {228; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[ARG0]], i32 poison, i32 [[ARG1]])229; CHECK-NEXT: ret i32 [[RES]]230;231 %res = call i32 @llvm.amdgcn.writelane.i32(i32 %arg0, i32 poison, i32 %arg1)232 ret i32 %res233}234 235define float @writelane_f32_63(float %arg0, float %arg1) #0 {236; WAVE64-LABEL: define float @writelane_f32_63(237; WAVE64-SAME: float [[ARG0:%.*]], float [[ARG1:%.*]]) #[[ATTR0]] {238; WAVE64-NEXT: [[RES:%.*]] = call float @llvm.amdgcn.writelane.f32(float [[ARG0]], i32 63, float [[ARG1]])239; WAVE64-NEXT: ret float [[RES]]240;241; WAVE32-LABEL: define float @writelane_f32_63(242; WAVE32-SAME: float [[ARG0:%.*]], float [[ARG1:%.*]]) #[[ATTR0]] {243; WAVE32-NEXT: [[RES:%.*]] = call float @llvm.amdgcn.writelane.f32(float [[ARG0]], i32 31, float [[ARG1]])244; WAVE32-NEXT: ret float [[RES]]245;246 %res = call float @llvm.amdgcn.writelane.f32(float %arg0, i32 63, float %arg1)247 ret float %res248}249 250attributes #0 = { nounwind }251