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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -mtriple=amdgcn-- -mcpu=gfx1030 -passes=instcombine -S < %s | FileCheck %s3 4; The readfirstlane version of this test covers all the interesting cases of the5; shared logic. This testcase focuses on readlane specific pitfalls.6 7; test unary8 9define float @hoist_fneg_f32(float %arg, i32 %lane) {10; CHECK-LABEL: define float @hoist_fneg_f32(11; CHECK-SAME: float [[ARG:%.*]], i32 [[LANE:%.*]]) #[[ATTR0:[0-9]+]] {12; CHECK-NEXT: [[BB:.*:]]13; CHECK-NEXT: [[RL:%.*]] = call float @llvm.amdgcn.readlane.f32(float [[ARG]], i32 [[LANE]])14; CHECK-NEXT: [[RFL:%.*]] = fneg float [[RL]]15; CHECK-NEXT: ret float [[RFL]]16;17bb:18 %val = fneg float %arg19 %rl = call float @llvm.amdgcn.readlane.f32(float %val, i32 %lane)20 ret float %rl21}22 23define double @hoist_fneg_f64(double %arg, i32 %lane) {24; CHECK-LABEL: define double @hoist_fneg_f64(25; CHECK-SAME: double [[ARG:%.*]], i32 [[LANE:%.*]]) #[[ATTR0]] {26; CHECK-NEXT: [[BB:.*:]]27; CHECK-NEXT: [[RL:%.*]] = call double @llvm.amdgcn.readlane.f64(double [[ARG]], i32 [[LANE]])28; CHECK-NEXT: [[RFL:%.*]] = fneg double [[RL]]29; CHECK-NEXT: ret double [[RFL]]30;31bb:32 %val = fneg double %arg33 %rl = call double @llvm.amdgcn.readlane.f64(double %val, i32 %lane)34 ret double %rl35}36 37; test casts38 39define i32 @hoist_trunc(i64 %arg, i32 %lane) {40; CHECK-LABEL: define i32 @hoist_trunc(41; CHECK-SAME: i64 [[ARG:%.*]], i32 [[LANE:%.*]]) #[[ATTR0]] {42; CHECK-NEXT: [[BB:.*:]]43; CHECK-NEXT: [[RL:%.*]] = call i64 @llvm.amdgcn.readlane.i64(i64 [[ARG]], i32 [[LANE]])44; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[RL]] to i3245; CHECK-NEXT: ret i32 [[TMP0]]46;47bb:48 %val = trunc i64 %arg to i3249 %rl = call i32 @llvm.amdgcn.readlane.i32(i32 %val, i32 %lane)50 ret i32 %rl51}52 53define i64 @hoist_zext(i32 %arg, i32 %lane) {54; CHECK-LABEL: define i64 @hoist_zext(55; CHECK-SAME: i32 [[ARG:%.*]], i32 [[LANE:%.*]]) #[[ATTR0]] {56; CHECK-NEXT: [[BB:.*:]]57; CHECK-NEXT: [[RL:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 [[LANE]])58; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[RL]] to i6459; CHECK-NEXT: ret i64 [[TMP0]]60;61bb:62 %val = zext i32 %arg to i6463 %rl = call i64 @llvm.amdgcn.readlane.i64(i64 %val, i32 %lane)64 ret i64 %rl65}66 67; test binary i3268 69define i32 @hoist_add_i32(i32 %arg, i32 %lane) {70; CHECK-LABEL: define i32 @hoist_add_i32(71; CHECK-SAME: i32 [[ARG:%.*]], i32 [[LANE:%.*]]) #[[ATTR0]] {72; CHECK-NEXT: [[BB:.*:]]73; CHECK-NEXT: [[RL:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 [[LANE]])74; CHECK-NEXT: [[RFL:%.*]] = add i32 [[RL]], 1677721575; CHECK-NEXT: ret i32 [[RFL]]76;77bb:78 %val = add i32 %arg, 1677721579 %rl = call i32 @llvm.amdgcn.readlane.i32(i32 %val, i32 %lane)80 ret i32 %rl81}82 83define float @hoist_fadd_f32(float %arg, i32 %lane) {84; CHECK-LABEL: define float @hoist_fadd_f32(85; CHECK-SAME: float [[ARG:%.*]], i32 [[LANE:%.*]]) #[[ATTR0]] {86; CHECK-NEXT: [[BB:.*:]]87; CHECK-NEXT: [[RL:%.*]] = call float @llvm.amdgcn.readlane.f32(float [[ARG]], i32 [[LANE]])88; CHECK-NEXT: [[RFL:%.*]] = fadd float [[RL]], 1.280000e+0289; CHECK-NEXT: ret float [[RFL]]90;91bb:92 %val = fadd float %arg, 128.093 %rl = call float @llvm.amdgcn.readlane.f32(float %val, i32 %lane)94 ret float %rl95}96 97; test binary i6498 99define i64 @hoist_and_i64(i64 %arg, i32 %lane) {100; CHECK-LABEL: define i64 @hoist_and_i64(101; CHECK-SAME: i64 [[ARG:%.*]], i32 [[LANE:%.*]]) #[[ATTR0]] {102; CHECK-NEXT: [[BB:.*:]]103; CHECK-NEXT: [[RL:%.*]] = call i64 @llvm.amdgcn.readlane.i64(i64 [[ARG]], i32 [[LANE]])104; CHECK-NEXT: [[RFL:%.*]] = and i64 [[RL]], 16777215105; CHECK-NEXT: ret i64 [[RFL]]106;107bb:108 %val = and i64 %arg, 16777215109 %rl = call i64 @llvm.amdgcn.readlane.i32(i64 %val, i32 %lane)110 ret i64 %rl111}112 113define double @hoist_fadd_f64(double %arg, i32 %lane) {114; CHECK-LABEL: define double @hoist_fadd_f64(115; CHECK-SAME: double [[ARG:%.*]], i32 [[LANE:%.*]]) #[[ATTR0]] {116; CHECK-NEXT: [[BB:.*:]]117; CHECK-NEXT: [[RL:%.*]] = call double @llvm.amdgcn.readlane.f64(double [[ARG]], i32 [[LANE]])118; CHECK-NEXT: [[RFL:%.*]] = fadd double [[RL]], 1.280000e+02119; CHECK-NEXT: ret double [[RFL]]120;121bb:122 %val = fadd double %arg, 128.0123 %rl = call double @llvm.amdgcn.readlane.f64(double %val, i32 %lane)124 ret double %rl125}126 127; test constant on LHS128 129define i32 @hoist_sub_i32_lhs(i32 %arg, i32 %lane) {130; CHECK-LABEL: define i32 @hoist_sub_i32_lhs(131; CHECK-SAME: i32 [[ARG:%.*]], i32 [[LANE:%.*]]) #[[ATTR0]] {132; CHECK-NEXT: [[BB:.*:]]133; CHECK-NEXT: [[RL:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 [[LANE]])134; CHECK-NEXT: [[RFL:%.*]] = sub i32 16777215, [[RL]]135; CHECK-NEXT: ret i32 [[RFL]]136;137bb:138 %val = sub i32 16777215, %arg139 %rl = call i32 @llvm.amdgcn.readlane.i32(i32 %val, i32 %lane)140 ret i32 %rl141}142 143define float @hoist_fsub_f32_lhs(float %arg, i32 %lane) {144; CHECK-LABEL: define float @hoist_fsub_f32_lhs(145; CHECK-SAME: float [[ARG:%.*]], i32 [[LANE:%.*]]) #[[ATTR0]] {146; CHECK-NEXT: [[BB:.*:]]147; CHECK-NEXT: [[RL:%.*]] = call float @llvm.amdgcn.readlane.f32(float [[ARG]], i32 [[LANE]])148; CHECK-NEXT: [[RFL:%.*]] = fsub float 1.280000e+02, [[RL]]149; CHECK-NEXT: ret float [[RFL]]150;151bb:152 %val = fsub float 128.0, %arg153 %rl = call float @llvm.amdgcn.readlane.f32(float %val, i32 %lane)154 ret float %rl155}156 157define i32 @readlane_lane_op_in_other_block(i1 %cond, i32 %arg, i32 %base) {158; CHECK-LABEL: define i32 @readlane_lane_op_in_other_block(159; CHECK-SAME: i1 [[COND:%.*]], i32 [[ARG:%.*]], i32 [[BASE:%.*]]) #[[ATTR0]] {160; CHECK-NEXT: [[BB:.*]]:161; CHECK-NEXT: [[LANE:%.*]] = add i32 [[BASE]], 2162; CHECK-NEXT: br i1 [[COND]], label %[[THEN:.*]], label %[[END:.*]]163; CHECK: [[THEN]]:164; CHECK-NEXT: [[RL:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 [[LANE]])165; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[RL]], 16777215166; CHECK-NEXT: br label %[[END]]167; CHECK: [[END]]:168; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[TMP0]], %[[THEN]] ], [ [[LANE]], %[[BB]] ]169; CHECK-NEXT: ret i32 [[RES]]170;171bb:172 %lane = add i32 %base, 2173 br i1 %cond, label %then, label %end174 175then:176 %val = add i32 %arg, 16777215177 %rl = call i32 @llvm.amdgcn.readlane.i32(i32 %val, i32 %lane)178 br label %end179 180end:181 %res = phi i32 [%rl, %then], [%lane, %bb]182 ret i32 %res183}184 185; Check cases where we can't move the readlane higher186 187define float @cannot_move_readlane(float %arg, i32 %base) {188; CHECK-LABEL: define float @cannot_move_readlane(189; CHECK-SAME: float [[ARG:%.*]], i32 [[BASE:%.*]]) #[[ATTR0]] {190; CHECK-NEXT: [[BB:.*:]]191; CHECK-NEXT: [[VAL:%.*]] = fsub float 1.280000e+02, [[ARG]]192; CHECK-NEXT: [[LANE:%.*]] = add i32 [[BASE]], 2193; CHECK-NEXT: [[RFL:%.*]] = call float @llvm.amdgcn.readlane.f32(float [[VAL]], i32 [[LANE]])194; CHECK-NEXT: ret float [[RFL]]195;196bb:197 %val = fsub float 128.0, %arg198 %lane = add i32 %base, 2199 %rl = call float @llvm.amdgcn.readlane.f32(float %val, i32 %lane)200 ret float %rl201}202 203 204; test that convergence tokens are preserved205 206define i32 @hoist_preserves_convergence_token(i1 %cond, i32 %arg, i32 %lane) convergent {207; CHECK-LABEL: define i32 @hoist_preserves_convergence_token(208; CHECK-SAME: i1 [[COND:%.*]], i32 [[ARG:%.*]], i32 [[LANE:%.*]]) #[[ATTR1:[0-9]+]] {209; CHECK-NEXT: [[BB:.*]]:210; CHECK-NEXT: [[ENTRY:%.*]] = call token @llvm.experimental.convergence.entry()211; CHECK-NEXT: br i1 [[COND]], label %[[THEN:.*]], label %[[END:.*]]212; CHECK: [[THEN]]:213; CHECK-NEXT: [[RL:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[ARG]], i32 [[LANE]]) [ "convergencectrl"(token [[ENTRY]]) ]214; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[RL]], 16777215215; CHECK-NEXT: br label %[[END]]216; CHECK: [[END]]:217; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[TMP0]], %[[THEN]] ], [ [[ARG]], %[[BB]] ]218; CHECK-NEXT: ret i32 [[RES]]219;220bb:221 %entry = call token @llvm.experimental.convergence.entry()222 br i1 %cond, label %then, label %end223 224then:225 %val = add i32 %arg, 16777215226 %rl = call i32 @llvm.amdgcn.readlane.i32(i32 %val, i32 %lane) [ "convergencectrl"(token %entry)]227 br label %end228 229end:230 %res = phi i32 [%rl, %then], [%arg, %bb]231 ret i32 %res232}233