450 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -passes=instcombine < %s | FileCheck %s3 4define i16 @extract_elt0_v2i16_readfirstlane(<2 x i16> %src) {5; CHECK-LABEL: define i16 @extract_elt0_v2i16_readfirstlane(6; CHECK-SAME: <2 x i16> [[SRC:%.*]]) #[[ATTR0:[0-9]+]] {7; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i16> [[SRC]], i64 08; CHECK-NEXT: [[ELT:%.*]] = call i16 @llvm.amdgcn.readfirstlane.i16(i16 [[TMP1]])9; CHECK-NEXT: ret i16 [[ELT]]10;11 %vec = call <2 x i16> @llvm.amdgcn.readfirstlane.v2i16(<2 x i16> %src)12 %elt = extractelement <2 x i16> %vec, i32 013 ret i16 %elt14}15 16define i16 @extract_elt0_v1i16_readfirstlane(<1 x i16> %src) {17; CHECK-LABEL: define i16 @extract_elt0_v1i16_readfirstlane(18; CHECK-SAME: <1 x i16> [[SRC:%.*]]) #[[ATTR0]] {19; CHECK-NEXT: [[TMP1:%.*]] = extractelement <1 x i16> [[SRC]], i64 020; CHECK-NEXT: [[ELT:%.*]] = call i16 @llvm.amdgcn.readfirstlane.i16(i16 [[TMP1]])21; CHECK-NEXT: ret i16 [[ELT]]22;23 %vec = call <1 x i16> @llvm.amdgcn.readfirstlane.v1i16(<1 x i16> %src)24 %elt = extractelement <1 x i16> %vec, i32 025 ret i16 %elt26}27 28define i16 @extract_elt1_v2i16_readfirstlane(<2 x i16> %src) {29; CHECK-LABEL: define i16 @extract_elt1_v2i16_readfirstlane(30; CHECK-SAME: <2 x i16> [[SRC:%.*]]) #[[ATTR0]] {31; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i16> [[SRC]], i64 132; CHECK-NEXT: [[ELT:%.*]] = call i16 @llvm.amdgcn.readfirstlane.i16(i16 [[TMP1]])33; CHECK-NEXT: ret i16 [[ELT]]34;35 %vec = call <2 x i16> @llvm.amdgcn.readfirstlane.v2i16(<2 x i16> %src)36 %elt = extractelement <2 x i16> %vec, i32 137 ret i16 %elt38}39 40define i16 @extract_elt0_v4i16_readfirstlane(<4 x i16> %src) {41; CHECK-LABEL: define i16 @extract_elt0_v4i16_readfirstlane(42; CHECK-SAME: <4 x i16> [[SRC:%.*]]) #[[ATTR0]] {43; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i16> [[SRC]], i64 044; CHECK-NEXT: [[ELT:%.*]] = call i16 @llvm.amdgcn.readfirstlane.i16(i16 [[TMP1]])45; CHECK-NEXT: ret i16 [[ELT]]46;47 %vec = call <4 x i16> @llvm.amdgcn.readfirstlane.v4i16(<4 x i16> %src)48 %elt = extractelement <4 x i16> %vec, i32 049 ret i16 %elt50}51 52define i16 @extract_elt2_v4i16_readfirstlane(<4 x i16> %src) {53; CHECK-LABEL: define i16 @extract_elt2_v4i16_readfirstlane(54; CHECK-SAME: <4 x i16> [[SRC:%.*]]) #[[ATTR0]] {55; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i16> [[SRC]], i64 256; CHECK-NEXT: [[ELT:%.*]] = call i16 @llvm.amdgcn.readfirstlane.i16(i16 [[TMP1]])57; CHECK-NEXT: ret i16 [[ELT]]58;59 %vec = call <4 x i16> @llvm.amdgcn.readfirstlane.v4i16(<4 x i16> %src)60 %elt = extractelement <4 x i16> %vec, i32 261 ret i16 %elt62}63 64define <2 x i16> @extract_elt01_v4i16_readfirstlane(<4 x i16> %src) {65; CHECK-LABEL: define <2 x i16> @extract_elt01_v4i16_readfirstlane(66; CHECK-SAME: <4 x i16> [[SRC:%.*]]) #[[ATTR0]] {67; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i16> [[SRC]], <4 x i16> poison, <2 x i32> <i32 0, i32 1>68; CHECK-NEXT: [[SHUFFLE:%.*]] = call <2 x i16> @llvm.amdgcn.readfirstlane.v2i16(<2 x i16> [[TMP1]])69; CHECK-NEXT: ret <2 x i16> [[SHUFFLE]]70;71 %vec = call <4 x i16> @llvm.amdgcn.readfirstlane.v4i16(<4 x i16> %src)72 %shuffle = shufflevector <4 x i16> %vec, <4 x i16> poison, <2 x i32> <i32 0, i32 1>73 ret <2 x i16> %shuffle74}75 76define <2 x i16> @extract_elt12_v4i16_readfirstlane(<4 x i16> %src) {77; CHECK-LABEL: define <2 x i16> @extract_elt12_v4i16_readfirstlane(78; CHECK-SAME: <4 x i16> [[SRC:%.*]]) #[[ATTR0]] {79; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i16> [[SRC]], <4 x i16> poison, <2 x i32> <i32 1, i32 2>80; CHECK-NEXT: [[SHUFFLE:%.*]] = call <2 x i16> @llvm.amdgcn.readfirstlane.v2i16(<2 x i16> [[TMP1]])81; CHECK-NEXT: ret <2 x i16> [[SHUFFLE]]82;83 %vec = call <4 x i16> @llvm.amdgcn.readfirstlane.v4i16(<4 x i16> %src)84 %shuffle = shufflevector <4 x i16> %vec, <4 x i16> poison, <2 x i32> <i32 1, i32 2>85 ret <2 x i16> %shuffle86}87 88define <2 x i16> @extract_elt23_v4i16_readfirstlane(<4 x i16> %src) {89; CHECK-LABEL: define <2 x i16> @extract_elt23_v4i16_readfirstlane(90; CHECK-SAME: <4 x i16> [[SRC:%.*]]) #[[ATTR0]] {91; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i16> [[SRC]], <4 x i16> poison, <2 x i32> <i32 2, i32 3>92; CHECK-NEXT: [[SHUFFLE:%.*]] = call <2 x i16> @llvm.amdgcn.readfirstlane.v2i16(<2 x i16> [[TMP1]])93; CHECK-NEXT: ret <2 x i16> [[SHUFFLE]]94;95 %vec = call <4 x i16> @llvm.amdgcn.readfirstlane.v4i16(<4 x i16> %src)96 %shuffle = shufflevector <4 x i16> %vec, <4 x i16> poison, <2 x i32> <i32 2, i32 3>97 ret <2 x i16> %shuffle98}99 100define <2 x i16> @extract_elt10_v4i16_readfirstlane(<4 x i16> %src) {101; CHECK-LABEL: define <2 x i16> @extract_elt10_v4i16_readfirstlane(102; CHECK-SAME: <4 x i16> [[SRC:%.*]]) #[[ATTR0]] {103; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i16> [[SRC]], <4 x i16> poison, <2 x i32> <i32 0, i32 1>104; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.amdgcn.readfirstlane.v2i16(<2 x i16> [[TMP1]])105; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x i16> [[TMP2]], <2 x i16> poison, <2 x i32> <i32 1, i32 0>106; CHECK-NEXT: ret <2 x i16> [[SHUFFLE]]107;108 %vec = call <4 x i16> @llvm.amdgcn.readfirstlane.v4i16(<4 x i16> %src)109 %shuffle = shufflevector <4 x i16> %vec, <4 x i16> poison, <2 x i32> <i32 1, i32 0>110 ret <2 x i16> %shuffle111}112 113define <2 x i16> @extract_elt32_v4i16_readfirstlane(<4 x i16> %src) {114; CHECK-LABEL: define <2 x i16> @extract_elt32_v4i16_readfirstlane(115; CHECK-SAME: <4 x i16> [[SRC:%.*]]) #[[ATTR0]] {116; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i16> [[SRC]], <4 x i16> poison, <2 x i32> <i32 2, i32 3>117; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.amdgcn.readfirstlane.v2i16(<2 x i16> [[TMP1]])118; CHECK-NEXT: [[VEC:%.*]] = shufflevector <2 x i16> [[TMP2]], <2 x i16> poison, <4 x i32> <i32 poison, i32 poison, i32 0, i32 1>119; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[VEC]], <4 x i16> poison, <2 x i32> <i32 3, i32 2>120; CHECK-NEXT: ret <2 x i16> [[SHUFFLE]]121;122 %vec = call <4 x i16> @llvm.amdgcn.readfirstlane.v4i16(<4 x i16> %src)123 %shuffle = shufflevector <4 x i16> %vec, <4 x i16> poison, <2 x i32> <i32 3, i32 2>124 ret <2 x i16> %shuffle125}126 127define <2 x i16> @extract_elt30_v4i16_readfirstlane(<4 x i16> %src) {128; CHECK-LABEL: define <2 x i16> @extract_elt30_v4i16_readfirstlane(129; CHECK-SAME: <4 x i16> [[SRC:%.*]]) #[[ATTR0]] {130; CHECK-NEXT: [[VEC:%.*]] = call <4 x i16> @llvm.amdgcn.readfirstlane.v4i16(<4 x i16> [[SRC]])131; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[VEC]], <4 x i16> poison, <2 x i32> <i32 3, i32 0>132; CHECK-NEXT: ret <2 x i16> [[SHUFFLE]]133;134 %vec = call <4 x i16> @llvm.amdgcn.readfirstlane.v4i16(<4 x i16> %src)135 %shuffle = shufflevector <4 x i16> %vec, <4 x i16> poison, <2 x i32> <i32 3, i32 0>136 ret <2 x i16> %shuffle137}138 139define half @extract_elt0_v2f16_readfirstlane(<2 x half> %src) {140; CHECK-LABEL: define half @extract_elt0_v2f16_readfirstlane(141; CHECK-SAME: <2 x half> [[SRC:%.*]]) #[[ATTR0]] {142; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x half> [[SRC]], i64 0143; CHECK-NEXT: [[ELT:%.*]] = call half @llvm.amdgcn.readfirstlane.f16(half [[TMP1]])144; CHECK-NEXT: ret half [[ELT]]145;146 %vec = call <2 x half> @llvm.amdgcn.readfirstlane.v2i16(<2 x half> %src)147 %elt = extractelement <2 x half> %vec, i32 0148 ret half %elt149}150 151define half @extract_elt1_v2f16_readfirstlane(<2 x half> %src) {152; CHECK-LABEL: define half @extract_elt1_v2f16_readfirstlane(153; CHECK-SAME: <2 x half> [[SRC:%.*]]) #[[ATTR0]] {154; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x half> [[SRC]], i64 1155; CHECK-NEXT: [[ELT:%.*]] = call half @llvm.amdgcn.readfirstlane.f16(half [[TMP1]])156; CHECK-NEXT: ret half [[ELT]]157;158 %vec = call <2 x half> @llvm.amdgcn.readfirstlane.v2i16(<2 x half> %src)159 %elt = extractelement <2 x half> %vec, i32 1160 ret half %elt161}162 163; Don't break on illegal types164define i8 @extract_elt0_v4i8_readfirstlane(<4 x i8> %src) {165; CHECK-LABEL: define i8 @extract_elt0_v4i8_readfirstlane(166; CHECK-SAME: <4 x i8> [[SRC:%.*]]) #[[ATTR0]] {167; CHECK-NEXT: [[VEC:%.*]] = call <4 x i8> @llvm.amdgcn.readfirstlane.v4i8(<4 x i8> [[SRC]])168; CHECK-NEXT: [[ELT:%.*]] = extractelement <4 x i8> [[VEC]], i64 0169; CHECK-NEXT: ret i8 [[ELT]]170;171 %vec = call <4 x i8> @llvm.amdgcn.readfirstlane.v4ii8(<4 x i8> %src)172 %elt = extractelement <4 x i8> %vec, i32 0173 ret i8 %elt174}175 176; Don't break on illegal types177define i32 @extract_elt0_nxv4i32_readfirstlane(<vscale x 2 x i32> %src) {178; CHECK-LABEL: define i32 @extract_elt0_nxv4i32_readfirstlane(179; CHECK-SAME: <vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {180; CHECK-NEXT: [[VEC:%.*]] = call <vscale x 2 x i32> @llvm.amdgcn.readfirstlane.nxv2i32(<vscale x 2 x i32> [[SRC]])181; CHECK-NEXT: [[ELT:%.*]] = extractelement <vscale x 2 x i32> [[VEC]], i64 0182; CHECK-NEXT: ret i32 [[ELT]]183;184 %vec = call <vscale x 2 x i32> @llvm.amdgcn.readfirstlane.nxv2i32(<vscale x 2 x i32> %src)185 %elt = extractelement <vscale x 2 x i32> %vec, i32 0186 ret i32 %elt187}188 189define i32 @extract_elt0_v2i32_readfirstlane(<2 x i32> %src) {190; CHECK-LABEL: define i32 @extract_elt0_v2i32_readfirstlane(191; CHECK-SAME: <2 x i32> [[SRC:%.*]]) #[[ATTR0]] {192; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[SRC]], i64 0193; CHECK-NEXT: [[ELT:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP1]])194; CHECK-NEXT: ret i32 [[ELT]]195;196 %vec = call <2 x i32> @llvm.amdgcn.readfirstlane.v2i32(<2 x i32> %src)197 %elt = extractelement <2 x i32> %vec, i32 0198 ret i32 %elt199}200 201define ptr addrspace(3) @extract_elt0_v2p3_readfirstlane(<2 x ptr addrspace(3)> %src) {202; CHECK-LABEL: define ptr addrspace(3) @extract_elt0_v2p3_readfirstlane(203; CHECK-SAME: <2 x ptr addrspace(3)> [[SRC:%.*]]) #[[ATTR0]] {204; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x ptr addrspace(3)> [[SRC]], i64 0205; CHECK-NEXT: [[ELT:%.*]] = call ptr addrspace(3) @llvm.amdgcn.readfirstlane.p3(ptr addrspace(3) [[TMP1]])206; CHECK-NEXT: ret ptr addrspace(3) [[ELT]]207;208 %vec = call <2 x ptr addrspace(3)> @llvm.amdgcn.readfirstlane.v2p3(<2 x ptr addrspace(3)> %src)209 %elt = extractelement <2 x ptr addrspace(3)> %vec, i32 0210 ret ptr addrspace(3) %elt211}212 213define i64 @extract_elt0_v2i64_readfirstlane(<2 x i64> %src) {214; CHECK-LABEL: define i64 @extract_elt0_v2i64_readfirstlane(215; CHECK-SAME: <2 x i64> [[SRC:%.*]]) #[[ATTR0]] {216; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[SRC]], i64 0217; CHECK-NEXT: [[ELT:%.*]] = call i64 @llvm.amdgcn.readfirstlane.i64(i64 [[TMP1]])218; CHECK-NEXT: ret i64 [[ELT]]219;220 %vec = call <2 x i64> @llvm.amdgcn.readfirstlane.v2i64(<2 x i64> %src)221 %elt = extractelement <2 x i64> %vec, i32 0222 ret i64 %elt223}224 225define i64 @extract_elt1_v2i64_readfirstlane(<2 x i64> %src) {226; CHECK-LABEL: define i64 @extract_elt1_v2i64_readfirstlane(227; CHECK-SAME: <2 x i64> [[SRC:%.*]]) #[[ATTR0]] {228; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[SRC]], i64 1229; CHECK-NEXT: [[ELT:%.*]] = call i64 @llvm.amdgcn.readfirstlane.i64(i64 [[TMP1]])230; CHECK-NEXT: ret i64 [[ELT]]231;232 %vec = call <2 x i64> @llvm.amdgcn.readfirstlane.v2i64(<2 x i64> %src)233 %elt = extractelement <2 x i64> %vec, i32 1234 ret i64 %elt235}236 237define <3 x i16> @extract_elt012_v4i16_readfirstlane(<4 x i16> %src) {238; CHECK-LABEL: define <3 x i16> @extract_elt012_v4i16_readfirstlane(239; CHECK-SAME: <4 x i16> [[SRC:%.*]]) #[[ATTR0]] {240; CHECK-NEXT: [[VEC:%.*]] = call <4 x i16> @llvm.amdgcn.readfirstlane.v4i16(<4 x i16> [[SRC]])241; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[VEC]], <4 x i16> poison, <3 x i32> <i32 0, i32 1, i32 2>242; CHECK-NEXT: ret <3 x i16> [[SHUFFLE]]243;244 %vec = call <4 x i16> @llvm.amdgcn.readfirstlane.v4i16(<4 x i16> %src)245 %shuffle = shufflevector <4 x i16> %vec, <4 x i16> poison, <3 x i32> <i32 0, i32 1, i32 2>246 ret <3 x i16> %shuffle247}248 249define <3 x i16> @extract_elt123_v4i16_readfirstlane(<4 x i16> %src) {250; CHECK-LABEL: define <3 x i16> @extract_elt123_v4i16_readfirstlane(251; CHECK-SAME: <4 x i16> [[SRC:%.*]]) #[[ATTR0]] {252; CHECK-NEXT: [[VEC:%.*]] = call <4 x i16> @llvm.amdgcn.readfirstlane.v4i16(<4 x i16> [[SRC]])253; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[VEC]], <4 x i16> poison, <3 x i32> <i32 1, i32 2, i32 3>254; CHECK-NEXT: ret <3 x i16> [[SHUFFLE]]255;256 %vec = call <4 x i16> @llvm.amdgcn.readfirstlane.v4i16(<4 x i16> %src)257 %shuffle = shufflevector <4 x i16> %vec, <4 x i16> poison, <3 x i32> <i32 1, i32 2, i32 3>258 ret <3 x i16> %shuffle259}260 261define <3 x i32> @extract_elt012_v4i32_readfirstlane(<4 x i32> %src) {262; CHECK-LABEL: define <3 x i32> @extract_elt012_v4i32_readfirstlane(263; CHECK-SAME: <4 x i32> [[SRC:%.*]]) #[[ATTR0]] {264; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[SRC]], <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>265; CHECK-NEXT: [[SHUFFLE:%.*]] = call <3 x i32> @llvm.amdgcn.readfirstlane.v3i32(<3 x i32> [[TMP1]])266; CHECK-NEXT: ret <3 x i32> [[SHUFFLE]]267;268 %vec = call <4 x i32> @llvm.amdgcn.readfirstlane.v4i32(<4 x i32> %src)269 %shuffle = shufflevector <4 x i32> %vec, <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>270 ret <3 x i32> %shuffle271}272 273define <3 x i32> @extract_elt123_v4i32_readfirstlane(<4 x i32> %src) {274; CHECK-LABEL: define <3 x i32> @extract_elt123_v4i32_readfirstlane(275; CHECK-SAME: <4 x i32> [[SRC:%.*]]) #[[ATTR0]] {276; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[SRC]], <4 x i32> poison, <3 x i32> <i32 1, i32 2, i32 3>277; CHECK-NEXT: [[SHUFFLE:%.*]] = call <3 x i32> @llvm.amdgcn.readfirstlane.v3i32(<3 x i32> [[TMP1]])278; CHECK-NEXT: ret <3 x i32> [[SHUFFLE]]279;280 %vec = call <4 x i32> @llvm.amdgcn.readfirstlane.v4i32(<4 x i32> %src)281 %shuffle = shufflevector <4 x i32> %vec, <4 x i32> poison, <3 x i32> <i32 1, i32 2, i32 3>282 ret <3 x i32> %shuffle283}284 285define <2 x i32> @extract_elt13_v4i32_readfirstlane(<4 x i32> %src) {286; CHECK-LABEL: define <2 x i32> @extract_elt13_v4i32_readfirstlane(287; CHECK-SAME: <4 x i32> [[SRC:%.*]]) #[[ATTR0]] {288; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[SRC]], <4 x i32> poison, <3 x i32> <i32 1, i32 poison, i32 3>289; CHECK-NEXT: [[TMP2:%.*]] = call <3 x i32> @llvm.amdgcn.readfirstlane.v3i32(<3 x i32> [[TMP1]])290; CHECK-NEXT: [[VEC:%.*]] = shufflevector <3 x i32> [[TMP2]], <3 x i32> poison, <4 x i32> <i32 poison, i32 0, i32 poison, i32 2>291; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[VEC]], <4 x i32> poison, <2 x i32> <i32 1, i32 3>292; CHECK-NEXT: ret <2 x i32> [[SHUFFLE]]293;294 %vec = call <4 x i32> @llvm.amdgcn.readfirstlane.v4i32(<4 x i32> %src)295 %shuffle = shufflevector <4 x i32> %vec, <4 x i32> poison, <2 x i32> <i32 1, i32 3>296 ret <2 x i32> %shuffle297}298 299define <2 x i16> @extract_elt13_v4i16readfirstlane(<4 x i16> %src) {300; CHECK-LABEL: define <2 x i16> @extract_elt13_v4i16readfirstlane(301; CHECK-SAME: <4 x i16> [[SRC:%.*]]) #[[ATTR0]] {302; CHECK-NEXT: [[VEC:%.*]] = call <4 x i16> @llvm.amdgcn.readfirstlane.v4i16(<4 x i16> [[SRC]])303; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[VEC]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>304; CHECK-NEXT: ret <2 x i16> [[SHUFFLE]]305;306 %vec = call <4 x i16> @llvm.amdgcn.readfirstlane.v4i16(<4 x i16> %src)307 %shuffle = shufflevector <4 x i16> %vec, <4 x i16> poison, <2 x i32> <i32 1, i32 3>308 ret <2 x i16> %shuffle309}310 311define <2 x i32> @extract_elt13_v4i32_readfirstlane_source_simplify0(i32 %src0, i32 %src2) {312; CHECK-LABEL: define <2 x i32> @extract_elt13_v4i32_readfirstlane_source_simplify0(313; CHECK-SAME: i32 [[SRC0:%.*]], i32 [[SRC2:%.*]]) #[[ATTR0]] {314; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[SRC0]])315; CHECK-NEXT: [[SHUFFLE:%.*]] = insertelement <2 x i32> poison, i32 [[TMP1]], i64 0316; CHECK-NEXT: ret <2 x i32> [[SHUFFLE]]317;318 %ins.0 = insertelement <4 x i32> poison, i32 %src0, i32 0319 %ins.1 = insertelement <4 x i32> %ins.0, i32 %src0, i32 1320 %vec = call <4 x i32> @llvm.amdgcn.readfirstlane.v4i32(<4 x i32> %ins.1)321 %shuffle = shufflevector <4 x i32> %vec, <4 x i32> poison, <2 x i32> <i32 1, i32 3>322 ret <2 x i32> %shuffle323}324 325define < 2 x i32> @extract_elt13_v4i32_readfirstlane_source_simplify1(i32 %src0, i32 %src2) {326; CHECK-LABEL: define <2 x i32> @extract_elt13_v4i32_readfirstlane_source_simplify1(327; CHECK-SAME: i32 [[SRC0:%.*]], i32 [[SRC2:%.*]]) #[[ATTR0]] {328; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[SRC0]], i64 0329; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <3 x i32> <i32 0, i32 poison, i32 0>330; CHECK-NEXT: [[TMP3:%.*]] = call <3 x i32> @llvm.amdgcn.readfirstlane.v3i32(<3 x i32> [[TMP2]])331; CHECK-NEXT: [[VEC:%.*]] = shufflevector <3 x i32> [[TMP3]], <3 x i32> poison, <4 x i32> <i32 poison, i32 0, i32 poison, i32 2>332; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[VEC]], <4 x i32> poison, <2 x i32> <i32 1, i32 3>333; CHECK-NEXT: ret <2 x i32> [[SHUFFLE]]334;335 %ins.0 = insertelement <4 x i32> poison, i32 %src0, i32 1336 %ins.1 = insertelement <4 x i32> %ins.0, i32 %src0, i32 3337 %vec = call <4 x i32> @llvm.amdgcn.readfirstlane.v4i32(<4 x i32> %ins.1)338 %shuffle = shufflevector <4 x i32> %vec, <4 x i32> poison, <2 x i32> <i32 1, i32 3>339 ret <2 x i32> %shuffle340}341 342define < 2 x i32> @extract_elt13_v4i32_readfirstlane_source_simplify2(i32 %src0, i32 %src2) {343; CHECK-LABEL: define <2 x i32> @extract_elt13_v4i32_readfirstlane_source_simplify2(344; CHECK-SAME: i32 [[SRC0:%.*]], i32 [[SRC2:%.*]]) #[[ATTR0]] {345; CHECK-NEXT: ret <2 x i32> poison346;347 %ins.0 = insertelement <4 x i32> poison, i32 %src0, i32 0348 %ins.1 = insertelement <4 x i32> %ins.0, i32 %src0, i32 2349 %vec = call <4 x i32> @llvm.amdgcn.readfirstlane.v4i32(<4 x i32> %ins.1)350 %shuffle = shufflevector <4 x i32> %vec, <4 x i32> poison, <2 x i32> <i32 1, i32 3>351 ret <2 x i32> %shuffle352}353 354define i32 @extract_elt0_v2i32_readfirstlane_convergencetoken(<2 x i32> %src) convergent {355; CHECK-LABEL: define i32 @extract_elt0_v2i32_readfirstlane_convergencetoken(356; CHECK-SAME: <2 x i32> [[SRC:%.*]]) #[[ATTR1:[0-9]+]] {357; CHECK-NEXT: [[T:%.*]] = call token @llvm.experimental.convergence.entry()358; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[SRC]], i64 0359; CHECK-NEXT: [[ELT:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP1]]) [ "convergencectrl"(token [[T]]) ]360; CHECK-NEXT: ret i32 [[ELT]]361;362 %t = call token @llvm.experimental.convergence.entry()363 %vec = call <2 x i32> @llvm.amdgcn.readfirstlane.v2i32(<2 x i32> %src) [ "convergencectrl"(token %t) ]364 %elt = extractelement <2 x i32> %vec, i32 0365 ret i32 %elt366}367 368define < 2 x i32> @extract_elt13_v4i32_readfirstlane_source_simplify1_convergencetoken(i32 %src0, i32 %src2) convergent {369; CHECK-LABEL: define <2 x i32> @extract_elt13_v4i32_readfirstlane_source_simplify1_convergencetoken(370; CHECK-SAME: i32 [[SRC0:%.*]], i32 [[SRC2:%.*]]) #[[ATTR1]] {371; CHECK-NEXT: [[T:%.*]] = call token @llvm.experimental.convergence.entry()372; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[SRC0]], i64 0373; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <3 x i32> <i32 0, i32 poison, i32 0>374; CHECK-NEXT: [[TMP3:%.*]] = call <3 x i32> @llvm.amdgcn.readfirstlane.v3i32(<3 x i32> [[TMP2]]) [ "convergencectrl"(token [[T]]) ]375; CHECK-NEXT: [[VEC:%.*]] = shufflevector <3 x i32> [[TMP3]], <3 x i32> poison, <4 x i32> <i32 poison, i32 0, i32 poison, i32 2>376; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[VEC]], <4 x i32> poison, <2 x i32> <i32 1, i32 3>377; CHECK-NEXT: ret <2 x i32> [[SHUFFLE]]378;379 %t = call token @llvm.experimental.convergence.entry()380 %ins.0 = insertelement <4 x i32> poison, i32 %src0, i32 1381 %ins.1 = insertelement <4 x i32> %ins.0, i32 %src0, i32 3382 %vec = call <4 x i32> @llvm.amdgcn.readfirstlane.v4i32(<4 x i32> %ins.1) [ "convergencectrl"(token %t) ]383 %shuffle = shufflevector <4 x i32> %vec, <4 x i32> poison, <2 x i32> <i32 1, i32 3>384 ret <2 x i32> %shuffle385}386 387define i1 @extract_elt0_v2i1_readfirstlane(<2 x i1> %src) {388; CHECK-LABEL: define i1 @extract_elt0_v2i1_readfirstlane(389; CHECK-SAME: <2 x i1> [[SRC:%.*]]) #[[ATTR0]] {390; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i1> [[SRC]], i64 0391; CHECK-NEXT: [[ELT:%.*]] = call i1 @llvm.amdgcn.readfirstlane.i1(i1 [[TMP1]])392; CHECK-NEXT: ret i1 [[ELT]]393;394 %vec = call <2 x i1> @llvm.amdgcn.readfirstlane.v2i1(<2 x i1> %src)395 %elt = extractelement <2 x i1> %vec, i32 0396 ret i1 %elt397}398 399define <2 x i1> @extract_elt01_v4i1_readfirstlane(<4 x i1> %src) {400; CHECK-LABEL: define <2 x i1> @extract_elt01_v4i1_readfirstlane(401; CHECK-SAME: <4 x i1> [[SRC:%.*]]) #[[ATTR0]] {402; CHECK-NEXT: [[VEC:%.*]] = call <4 x i1> @llvm.amdgcn.readfirstlane.v4i1(<4 x i1> [[SRC]])403; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i1> [[VEC]], <4 x i1> poison, <2 x i32> <i32 0, i32 1>404; CHECK-NEXT: ret <2 x i1> [[SHUFFLE]]405;406 %vec = call <4 x i1> @llvm.amdgcn.readfirstlane.v4i1(<4 x i1> %src)407 %shuffle = shufflevector <4 x i1> %vec, <4 x i1> poison, <2 x i32> <i32 0, i32 1>408 ret <2 x i1> %shuffle409}410 411define <2 x i32> @extract_elt13_v8i32_readfirstlane(<8 x i32> %src) {412; CHECK-LABEL: define <2 x i32> @extract_elt13_v8i32_readfirstlane(413; CHECK-SAME: <8 x i32> [[SRC:%.*]]) #[[ATTR0]] {414; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[SRC]], <8 x i32> poison, <3 x i32> <i32 1, i32 poison, i32 3>415; CHECK-NEXT: [[TMP2:%.*]] = call <3 x i32> @llvm.amdgcn.readfirstlane.v3i32(<3 x i32> [[TMP1]])416; CHECK-NEXT: [[VEC:%.*]] = shufflevector <3 x i32> [[TMP2]], <3 x i32> poison, <8 x i32> <i32 poison, i32 0, i32 poison, i32 2, i32 poison, i32 poison, i32 poison, i32 poison>417; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <8 x i32> [[VEC]], <8 x i32> poison, <2 x i32> <i32 1, i32 3>418; CHECK-NEXT: ret <2 x i32> [[SHUFFLE]]419;420 %vec = call <8 x i32> @llvm.amdgcn.readfirstlane.v8i32(<8 x i32> %src)421 %shuffle = shufflevector <8 x i32> %vec, <8 x i32> poison, <2 x i32> <i32 1, i32 3>422 ret <2 x i32> %shuffle423}424 425define <2 x i32> @extract_elt03_v4i32_readfirstlane(<4 x i32> %src) {426; CHECK-LABEL: define <2 x i32> @extract_elt03_v4i32_readfirstlane(427; CHECK-SAME: <4 x i32> [[SRC:%.*]]) #[[ATTR0]] {428; CHECK-NEXT: [[VEC:%.*]] = call <4 x i32> @llvm.amdgcn.readfirstlane.v4i32(<4 x i32> [[SRC]])429; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[VEC]], <4 x i32> poison, <2 x i32> <i32 0, i32 3>430; CHECK-NEXT: ret <2 x i32> [[SHUFFLE]]431;432 %vec = call <4 x i32> @llvm.amdgcn.readfirstlane.v4i32(<4 x i32> %src)433 %shuffle = shufflevector <4 x i32> %vec, <4 x i32> poison, <2 x i32> <i32 0, i32 3>434 ret <2 x i32> %shuffle435}436 437define <3 x i32> @extract_elt124_v8i32_readfirstlane(<8 x i32> %src) {438; CHECK-LABEL: define <3 x i32> @extract_elt124_v8i32_readfirstlane(439; CHECK-SAME: <8 x i32> [[SRC:%.*]]) #[[ATTR0]] {440; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[SRC]], <8 x i32> poison, <4 x i32> <i32 1, i32 2, i32 poison, i32 4>441; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.amdgcn.readfirstlane.v4i32(<4 x i32> [[TMP1]])442; CHECK-NEXT: [[VEC:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <8 x i32> <i32 poison, i32 0, i32 1, i32 poison, i32 3, i32 poison, i32 poison, i32 poison>443; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <8 x i32> [[VEC]], <8 x i32> poison, <3 x i32> <i32 1, i32 2, i32 4>444; CHECK-NEXT: ret <3 x i32> [[SHUFFLE]]445;446 %vec = call <8 x i32> @llvm.amdgcn.readfirstlane.v8i32(<8 x i32> %src)447 %shuffle = shufflevector <8 x i32> %vec, <8 x i32> poison, <3 x i32> <i32 1, i32 2, i32 4>448 ret <3 x i32> %shuffle449}450