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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -mtriple=amdgcn -mcpu=gfx1010 -passes=instcombine -S < %s | FileCheck %s3 4; Use readfirstlane to demonstrate when InstCombine deems an input to5; be trivially uniform.6 7; Constants are trivially uniform.8define i32 @test_constant() {9; CHECK-LABEL: define i32 @test_constant(10; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {11; CHECK-NEXT: ret i32 712;13 %r = call i32 @llvm.amdgcn.readfirstlane(i32 7)14 ret i32 %r15}16 17; The result of an AlwaysUniform intrinsic is trivially uniform.18define i32 @test_intrinsic(i32 %x) {19; CHECK-LABEL: define i32 @test_intrinsic(20; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] {21; CHECK-NEXT: [[Y:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[X]])22; CHECK-NEXT: ret i32 [[Y]]23;24 %y = call i32 @llvm.amdgcn.readfirstlane(i32 %x)25 %r = call i32 @llvm.amdgcn.readfirstlane(i32 %y)26 ret i32 %r27}28 29; In compute kernels, all arguments are trivially uniform.30 31define amdgpu_kernel void @test_compute_i32(ptr %out, i32 %x) {32; CHECK-LABEL: define amdgpu_kernel void @test_compute_i32(33; CHECK-SAME: ptr [[OUT:%.*]], i32 [[X:%.*]]) #[[ATTR0]] {34; CHECK-NEXT: store i32 [[X]], ptr [[OUT]], align 435; CHECK-NEXT: ret void36;37 %r = call i32 @llvm.amdgcn.readfirstlane(i32 %x)38 store i32 %r, ptr %out39 ret void40}41 42define amdgpu_kernel void @test_compute_i1(ptr %out, i1 %x) {43; CHECK-LABEL: define amdgpu_kernel void @test_compute_i1(44; CHECK-SAME: ptr [[OUT:%.*]], i1 [[X:%.*]]) #[[ATTR0]] {45; CHECK-NEXT: store i1 [[X]], ptr [[OUT]], align 146; CHECK-NEXT: ret void47;48 %r = call i1 @llvm.amdgcn.readfirstlane(i1 %x)49 store i1 %r, ptr %out50 ret void51}52 53define amdgpu_kernel void @test_compute_v32i1(ptr %out, <32 x i1> %x) {54; CHECK-LABEL: define amdgpu_kernel void @test_compute_v32i1(55; CHECK-SAME: ptr [[OUT:%.*]], <32 x i1> [[X:%.*]]) #[[ATTR0]] {56; CHECK-NEXT: store <32 x i1> [[X]], ptr [[OUT]], align 457; CHECK-NEXT: ret void58;59 %r = call <32 x i1> @llvm.amdgcn.readfirstlane(<32 x i1> %x)60 store <32 x i1> %r, ptr %out61 ret void62}63 64; In graphics shaders, inreg arguments are trivially uniform.65 66define amdgpu_ps i32 @test_graphics_i32(i32 inreg %x) {67; CHECK-LABEL: define amdgpu_ps i32 @test_graphics_i32(68; CHECK-SAME: i32 inreg [[X:%.*]]) #[[ATTR0]] {69; CHECK-NEXT: ret i32 [[X]]70;71 %r = call i32 @llvm.amdgcn.readfirstlane(i32 %x)72 ret i32 %r73}74 75define amdgpu_ps i1 @test_graphics_i1(i1 inreg %x) {76; CHECK-LABEL: define amdgpu_ps i1 @test_graphics_i1(77; CHECK-SAME: i1 inreg [[X:%.*]]) #[[ATTR0]] {78; CHECK-NEXT: ret i1 [[X]]79;80 %r = call i1 @llvm.amdgcn.readfirstlane(i1 %x)81 ret i1 %r82}83 84define amdgpu_ps <32 x i1> @test_graphics_v32i1(<32 x i1> inreg %x) {85; CHECK-LABEL: define amdgpu_ps <32 x i1> @test_graphics_v32i1(86; CHECK-SAME: <32 x i1> inreg [[X:%.*]]) #[[ATTR0]] {87; CHECK-NEXT: ret <32 x i1> [[X]]88;89 %r = call <32 x i1> @llvm.amdgcn.readfirstlane(<32 x i1> %x)90 ret <32 x i1> %r91}92 93; In graphics shaders, non-inreg arguments are not trivially uniform.94 95define amdgpu_ps i32 @test_graphics_i32_negative(i32 %x) {96; CHECK-LABEL: define amdgpu_ps i32 @test_graphics_i32_negative(97; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] {98; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[X]])99; CHECK-NEXT: ret i32 [[R]]100;101 %r = call i32 @llvm.amdgcn.readfirstlane(i32 %x)102 ret i32 %r103}104 105define amdgpu_ps i1 @test_graphics_i1_negative(i1 %x) {106; CHECK-LABEL: define amdgpu_ps i1 @test_graphics_i1_negative(107; CHECK-SAME: i1 [[X:%.*]]) #[[ATTR0]] {108; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.amdgcn.readfirstlane.i1(i1 [[X]])109; CHECK-NEXT: ret i1 [[R]]110;111 %r = call i1 @llvm.amdgcn.readfirstlane(i1 %x)112 ret i1 %r113}114 115define amdgpu_ps <32 x i1> @test_graphics_v32i1_negative(<32 x i1> %x) {116; CHECK-LABEL: define amdgpu_ps <32 x i1> @test_graphics_v32i1_negative(117; CHECK-SAME: <32 x i1> [[X:%.*]]) #[[ATTR0]] {118; CHECK-NEXT: [[R:%.*]] = call <32 x i1> @llvm.amdgcn.readfirstlane.v32i1(<32 x i1> [[X]])119; CHECK-NEXT: ret <32 x i1> [[R]]120;121 %r = call <32 x i1> @llvm.amdgcn.readfirstlane(<32 x i1> %x)122 ret <32 x i1> %r123}124 125; Test i1 arguments in non-entry functions.126 127define amdgpu_gfx i1 @test_callable_i1(i1 inreg %x) {128; CHECK-LABEL: define amdgpu_gfx i1 @test_callable_i1(129; CHECK-SAME: i1 inreg [[X:%.*]]) #[[ATTR0]] {130; CHECK-NEXT: ret i1 [[X]]131;132 %r = call i1 @llvm.amdgcn.readfirstlane(i1 %x)133 ret i1 %r134}135 136define amdgpu_gfx <32 x i1> @test_callable_v32i1(<32 x i1> inreg %x) {137; CHECK-LABEL: define amdgpu_gfx <32 x i1> @test_callable_v32i1(138; CHECK-SAME: <32 x i1> inreg [[X:%.*]]) #[[ATTR0]] {139; CHECK-NEXT: ret <32 x i1> [[X]]140;141 %r = call <32 x i1> @llvm.amdgcn.readfirstlane(<32 x i1> %x)142 ret <32 x i1> %r143}144 145define amdgpu_gfx i1 @test_callable_i1_negative(i1 %x) {146; CHECK-LABEL: define amdgpu_gfx i1 @test_callable_i1_negative(147; CHECK-SAME: i1 [[X:%.*]]) #[[ATTR0]] {148; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.amdgcn.readfirstlane.i1(i1 [[X]])149; CHECK-NEXT: ret i1 [[R]]150;151 %r = call i1 @llvm.amdgcn.readfirstlane(i1 %x)152 ret i1 %r153}154 155define amdgpu_gfx <32 x i1> @test_callable_v32i1_negative(<32 x i1> %x) {156; CHECK-LABEL: define amdgpu_gfx <32 x i1> @test_callable_v32i1_negative(157; CHECK-SAME: <32 x i1> [[X:%.*]]) #[[ATTR0]] {158; CHECK-NEXT: [[R:%.*]] = call <32 x i1> @llvm.amdgcn.readfirstlane.v32i1(<32 x i1> [[X]])159; CHECK-NEXT: ret <32 x i1> [[R]]160;161 %r = call <32 x i1> @llvm.amdgcn.readfirstlane(<32 x i1> %x)162 ret <32 x i1> %r163}164