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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S -passes=instcombine < %s | FileCheck %s3 4define <4 x i32> @mulByZero(<4 x i16> %x) nounwind readnone ssp {5; CHECK-LABEL: define <4 x i32> @mulByZero(6; CHECK-SAME: <4 x i16> [[X:%.*]]) #[[ATTR0:[0-9]+]] {7; CHECK-NEXT: [[ENTRY:.*:]]8; CHECK-NEXT: ret <4 x i32> zeroinitializer9;10entry:11 %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %x, <4 x i16> zeroinitializer) nounwind12 ret <4 x i32> %a13}14 15define <4 x i32> @mulByOne(<4 x i16> %x) nounwind readnone ssp {16; CHECK-LABEL: define <4 x i32> @mulByOne(17; CHECK-SAME: <4 x i16> [[X:%.*]]) #[[ATTR0]] {18; CHECK-NEXT: [[ENTRY:.*:]]19; CHECK-NEXT: [[A:%.*]] = sext <4 x i16> [[X]] to <4 x i32>20; CHECK-NEXT: ret <4 x i32> [[A]]21;22entry:23 %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %x, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind24 ret <4 x i32> %a25}26 27define <4 x i32> @constantMul() nounwind readnone ssp {28; CHECK-LABEL: define <4 x i32> @constantMul(29; CHECK-SAME: ) #[[ATTR0]] {30; CHECK-NEXT: [[ENTRY:.*:]]31; CHECK-NEXT: ret <4 x i32> splat (i32 6)32;33entry:34 %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind35 ret <4 x i32> %a36}37 38define <4 x i32> @constantMulS() nounwind readnone ssp {39; CHECK-LABEL: define <4 x i32> @constantMulS(40; CHECK-SAME: ) #[[ATTR0]] {41; CHECK-NEXT: [[ENTRY:.*:]]42; CHECK-NEXT: ret <4 x i32> splat (i32 -1)43;44entry:45 %b = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind46 ret <4 x i32> %b47}48 49define <4 x i32> @constantMulU() nounwind readnone ssp {50; CHECK-LABEL: define <4 x i32> @constantMulU(51; CHECK-SAME: ) #[[ATTR0]] {52; CHECK-NEXT: [[ENTRY:.*:]]53; CHECK-NEXT: ret <4 x i32> splat (i32 65535)54;55entry:56 %b = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind57 ret <4 x i32> %b58}59 60define <4 x i32> @complex1(<4 x i16> %x) nounwind readnone ssp {61; CHECK-LABEL: define <4 x i32> @complex1(62; CHECK-SAME: <4 x i16> [[X:%.*]]) #[[ATTR0]] {63; CHECK-NEXT: [[ENTRY:.*:]]64; CHECK-NEXT: [[A:%.*]] = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> splat (i16 2), <4 x i16> [[X]]) #[[ATTR2:[0-9]+]]65; CHECK-NEXT: ret <4 x i32> [[A]]66;67entry:68 %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) nounwind69 %b = add <4 x i32> zeroinitializer, %a70 ret <4 x i32> %b71}72 73define <4 x i32> @complex2(<4 x i32> %x) nounwind readnone ssp {74; CHECK-LABEL: define <4 x i32> @complex2(75; CHECK-SAME: <4 x i32> [[X:%.*]]) #[[ATTR0]] {76; CHECK-NEXT: [[ENTRY:.*:]]77; CHECK-NEXT: [[B:%.*]] = add <4 x i32> [[X]], splat (i32 6)78; CHECK-NEXT: ret <4 x i32> [[B]]79;80entry:81 %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind82 %b = add <4 x i32> %x, %a83 ret <4 x i32> %b84}85 86declare <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone87declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone88