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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s3 4declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>)5declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>)6declare <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double>, <4 x double>)7declare <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float>, <8 x float>)8declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8 immarg) #09 10;11; Demanded Elts12;13 14define double @elts_addsub_v2f64(<2 x double> %0, <2 x double> %1) {15; CHECK-LABEL: @elts_addsub_v2f64(16; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP1:%.*]], <2 x double> poison, <2 x i32> <i32 1, i32 poison>17; CHECK-NEXT: [[TMP4:%.*]] = fsub <2 x double> [[TMP0:%.*]], [[TMP3]]18; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i64 019; CHECK-NEXT: ret double [[TMP5]]20;21 %3 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> <i32 0, i32 0>22 %4 = shufflevector <2 x double> %1, <2 x double> undef, <2 x i32> <i32 1, i32 1>23 %5 = tail call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %3, <2 x double> %4)24 %6 = extractelement <2 x double> %5, i32 025 ret double %626}27 28define double @elts_addsub_v2f64_sub(<2 x double> %0, <2 x double> %1) {29; CHECK-LABEL: @elts_addsub_v2f64_sub(30; CHECK-NEXT: [[TMP3:%.*]] = fsub <2 x double> [[TMP0:%.*]], [[TMP1:%.*]]31; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i64 032; CHECK-NEXT: ret double [[TMP4]]33;34 %3 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> <i32 0, i32 0>35 %4 = shufflevector <2 x double> %1, <2 x double> undef, <2 x i32> <i32 0, i32 0>36 %5 = tail call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %3, <2 x double> %4)37 %6 = extractelement <2 x double> %5, i32 038 ret double %639}40 41define float @elts_addsub_v4f32(<4 x float> %0, <4 x float> %1) {42; CHECK-LABEL: @elts_addsub_v4f32(43; CHECK-NEXT: [[TMP3:%.*]] = tail call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> [[TMP0:%.*]], <4 x float> [[TMP1:%.*]])44; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i64 045; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x float> [[TMP3]], i64 146; CHECK-NEXT: [[TMP6:%.*]] = fadd float [[TMP4]], [[TMP5]]47; CHECK-NEXT: ret float [[TMP6]]48;49 %3 = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>50 %4 = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>51 %5 = tail call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %3, <4 x float> %4)52 %6 = extractelement <4 x float> %5, i32 053 %7 = extractelement <4 x float> %5, i32 154 %8 = fadd float %6, %755 ret float %856}57 58define float @elts_addsub_v4f32_add(<4 x float> %0, <4 x float> %1) {59; CHECK-LABEL: @elts_addsub_v4f32_add(60; CHECK-NEXT: [[TMP3:%.*]] = fadd <4 x float> [[TMP0:%.*]], [[TMP1:%.*]]61; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i64 162; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x float> [[TMP3]], i64 163; CHECK-NEXT: [[TMP6:%.*]] = fadd float [[TMP4]], [[TMP5]]64; CHECK-NEXT: ret float [[TMP6]]65;66 %3 = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>67 %4 = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>68 %5 = tail call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %3, <4 x float> %4)69 %6 = extractelement <4 x float> %5, i32 170 %7 = extractelement <4 x float> %5, i32 371 %8 = fadd float %6, %772 ret float %873}74 75define double @elts_addsub_v4f64(<4 x double> %0, <4 x double> %1) {76; CHECK-LABEL: @elts_addsub_v4f64(77; CHECK-NEXT: [[TMP3:%.*]] = tail call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> [[TMP0:%.*]], <4 x double> [[TMP1:%.*]])78; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x double> [[TMP3]], i64 079; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x double> [[TMP3]], i64 180; CHECK-NEXT: [[TMP6:%.*]] = fadd double [[TMP4]], [[TMP5]]81; CHECK-NEXT: ret double [[TMP6]]82;83 %3 = shufflevector <4 x double> %0, <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 3, i32 3>84 %4 = shufflevector <4 x double> %1, <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 3, i32 3>85 %5 = tail call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> %3, <4 x double> %4)86 %6 = extractelement <4 x double> %5, i32 087 %7 = extractelement <4 x double> %5, i32 188 %8 = fadd double %6, %789 ret double %890}91 92define double @elts_addsub_v4f64_add(<4 x double> %0, <4 x double> %1) {93; CHECK-LABEL: @elts_addsub_v4f64_add(94; CHECK-NEXT: [[TMP3:%.*]] = fadd <4 x double> [[TMP0:%.*]], [[TMP1:%.*]]95; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x double> [[TMP3]], i64 196; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x double> [[TMP3]], i64 397; CHECK-NEXT: [[TMP6:%.*]] = fadd double [[TMP4]], [[TMP5]]98; CHECK-NEXT: ret double [[TMP6]]99;100 %3 = shufflevector <4 x double> %0, <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 3, i32 3>101 %4 = shufflevector <4 x double> %1, <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 3, i32 3>102 %5 = tail call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> %3, <4 x double> %4)103 %6 = extractelement <4 x double> %5, i32 1104 %7 = extractelement <4 x double> %5, i32 3105 %8 = fadd double %6, %7106 ret double %8107}108 109define float @elts_addsub_v8f32(<8 x float> %0, <8 x float> %1) {110; CHECK-LABEL: @elts_addsub_v8f32(111; CHECK-NEXT: [[TMP3:%.*]] = tail call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> [[TMP0:%.*]], <8 x float> [[TMP1:%.*]])112; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x float> [[TMP3]], i64 0113; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x float> [[TMP3]], i64 1114; CHECK-NEXT: [[TMP6:%.*]] = fadd float [[TMP4]], [[TMP5]]115; CHECK-NEXT: ret float [[TMP6]]116;117 %3 = shufflevector <8 x float> %0, <8 x float> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 4, i32 4, i32 4>118 %4 = shufflevector <8 x float> %1, <8 x float> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 4, i32 4, i32 4>119 %5 = tail call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> %3, <8 x float> %4)120 %6 = extractelement <8 x float> %5, i32 0121 %7 = extractelement <8 x float> %5, i32 1122 %8 = fadd float %6, %7123 ret float %8124}125 126define float @elts_addsub_v8f32_sub(<8 x float> %0, <8 x float> %1) {127; CHECK-LABEL: @elts_addsub_v8f32_sub(128; CHECK-NEXT: [[TMP3:%.*]] = fsub <8 x float> [[TMP0:%.*]], [[TMP1:%.*]]129; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x float> [[TMP3]], i64 0130; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x float> [[TMP3]], i64 4131; CHECK-NEXT: [[TMP6:%.*]] = fadd float [[TMP4]], [[TMP5]]132; CHECK-NEXT: ret float [[TMP6]]133;134 %3 = shufflevector <8 x float> %0, <8 x float> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 4, i32 4, i32 4>135 %4 = shufflevector <8 x float> %1, <8 x float> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 4, i32 4, i32 4>136 %5 = tail call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> %3, <8 x float> %4)137 %6 = extractelement <8 x float> %5, i32 0138 %7 = extractelement <8 x float> %5, i32 4139 %8 = fadd float %6, %7140 ret float %8141}142 143define void @PR46277(float %0, float %1, float %2, float %3, <4 x float> %4, ptr %5) {144; CHECK-LABEL: @PR46277(145; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x float> poison, float [[TMP0:%.*]], i64 0146; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x float> [[TMP7]], float [[TMP1:%.*]], i64 1147; CHECK-NEXT: [[TMP9:%.*]] = tail call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> [[TMP8]], <4 x float> [[TMP4:%.*]])148; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x float> [[TMP9]], i64 0149; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw i8, ptr [[TMP5:%.*]], i64 4150; CHECK-NEXT: store float [[TMP10]], ptr [[TMP5]], align 4151; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x float> [[TMP9]], i64 1152; CHECK-NEXT: store float [[TMP12]], ptr [[TMP11]], align 4153; CHECK-NEXT: ret void154;155 %7 = insertelement <4 x float> undef, float %0, i32 0156 %8 = insertelement <4 x float> %7, float %1, i32 1157 %9 = insertelement <4 x float> %8, float %2, i32 2158 %10 = insertelement <4 x float> %9, float %3, i32 3159 %11 = tail call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %10, <4 x float> %4)160 %12 = extractelement <4 x float> %11, i32 0161 %13 = getelementptr inbounds float, ptr %5, i64 1162 store float %12, ptr %5, align 4163 %14 = extractelement <4 x float> %11, i32 1164 store float %14, ptr %13, align 4165 ret void166}167 168define double @PR48476_fsub(<2 x double> %x) {169; CHECK-LABEL: @PR48476_fsub(170; CHECK-NEXT: [[TMP1:%.*]] = fsub <2 x double> <double 0.000000e+00, double poison>, [[X:%.*]]171; CHECK-NEXT: [[T2:%.*]] = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> [[TMP1]], <2 x double> [[X]], i8 6)172; CHECK-NEXT: [[VECEXT:%.*]] = extractelement <2 x double> [[T2]], i64 0173; CHECK-NEXT: ret double [[VECEXT]]174;175 %t1 = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> zeroinitializer, <2 x double> %x)176 %t2 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %t1, <2 x double> %x, i8 6)177 %vecext = extractelement <2 x double> %t2, i32 0178 ret double %vecext179}180 181define double @PR48476_fadd_fsub(<2 x double> %x) {182; CHECK-LABEL: @PR48476_fadd_fsub(183; CHECK-NEXT: [[TMP1:%.*]] = fadd <2 x double> [[X:%.*]], <double poison, double 0.000000e+00>184; CHECK-NEXT: [[S:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <2 x i32> <i32 1, i32 poison>185; CHECK-NEXT: [[TMP2:%.*]] = fsub <2 x double> [[S]], [[X]]186; CHECK-NEXT: [[VECEXT:%.*]] = extractelement <2 x double> [[TMP2]], i64 0187; CHECK-NEXT: ret double [[VECEXT]]188;189 %t1 = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> zeroinitializer, <2 x double> %x)190 %s = shufflevector <2 x double> %t1, <2 x double> undef, <2 x i32> <i32 1, i32 0>191 %t2 = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %s, <2 x double> %x)192 %vecext = extractelement <2 x double> %t2, i32 0193 ret double %vecext194}195