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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=instcombine -data-layout="n8:16:32" -S | FileCheck %s3; RUN: opt < %s -passes=instcombine -data-layout="n16" -S | FileCheck %s4 5; PR35792 - https://bugs.llvm.org/show_bug.cgi?id=357926 7define i16 @zext_add(i8 %x) {8; CHECK-LABEL: @zext_add(9; CHECK-NEXT: [[TMP1:%.*]] = add i8 [[X:%.*]], 4410; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X]]11; CHECK-NEXT: [[R:%.*]] = zext i8 [[TMP2]] to i1612; CHECK-NEXT: ret i16 [[R]]13;14 %z = zext i8 %x to i1615 %b = add i16 %z, 4416 %r = and i16 %b, %z17 ret i16 %r18}19 20define i16 @zext_sub(i8 %x) {21; CHECK-LABEL: @zext_sub(22; CHECK-NEXT: [[TMP1:%.*]] = sub i8 -5, [[X:%.*]]23; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X]]24; CHECK-NEXT: [[R:%.*]] = zext i8 [[TMP2]] to i1625; CHECK-NEXT: ret i16 [[R]]26;27 %z = zext i8 %x to i1628 %b = sub i16 -5, %z29 %r = and i16 %b, %z30 ret i16 %r31}32 33define i16 @zext_mul(i8 %x) {34; CHECK-LABEL: @zext_mul(35; CHECK-NEXT: [[TMP1:%.*]] = mul i8 [[X:%.*]], 336; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X]]37; CHECK-NEXT: [[R:%.*]] = zext i8 [[TMP2]] to i1638; CHECK-NEXT: ret i16 [[R]]39;40 %z = zext i8 %x to i1641 %b = mul i16 %z, 342 %r = and i16 %b, %z43 ret i16 %r44}45 46define i16 @zext_lshr(i8 %x) {47; CHECK-LABEL: @zext_lshr(48; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 [[X:%.*]], 449; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X]]50; CHECK-NEXT: [[R:%.*]] = zext nneg i8 [[TMP2]] to i1651; CHECK-NEXT: ret i16 [[R]]52;53 %z = zext i8 %x to i1654 %b = lshr i16 %z, 455 %r = and i16 %b, %z56 ret i16 %r57}58 59define i16 @zext_ashr(i8 %x) {60; CHECK-LABEL: @zext_ashr(61; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 [[X:%.*]], 262; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X]]63; CHECK-NEXT: [[R:%.*]] = zext nneg i8 [[TMP2]] to i1664; CHECK-NEXT: ret i16 [[R]]65;66 %z = zext i8 %x to i1667 %b = ashr i16 %z, 268 %r = and i16 %b, %z69 ret i16 %r70}71 72define i16 @zext_shl(i8 %x) {73; CHECK-LABEL: @zext_shl(74; CHECK-NEXT: [[TMP1:%.*]] = shl i8 [[X:%.*]], 375; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X]]76; CHECK-NEXT: [[R:%.*]] = zext i8 [[TMP2]] to i1677; CHECK-NEXT: ret i16 [[R]]78;79 %z = zext i8 %x to i1680 %b = shl i16 %z, 381 %r = and i16 %b, %z82 ret i16 %r83}84 85define <2 x i16> @zext_add_vec(<2 x i8> %x) {86; CHECK-LABEL: @zext_add_vec(87; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i8> [[X:%.*]], <i8 44, i8 42>88; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i8> [[TMP1]], [[X]]89; CHECK-NEXT: [[R:%.*]] = zext <2 x i8> [[TMP2]] to <2 x i16>90; CHECK-NEXT: ret <2 x i16> [[R]]91;92 %z = zext <2 x i8> %x to <2 x i16>93 %b = add <2 x i16> %z, <i16 44, i16 42>94 %r = and <2 x i16> %b, %z95 ret <2 x i16> %r96}97 98define <2 x i16> @zext_sub_vec(<2 x i8> %x) {99; CHECK-LABEL: @zext_sub_vec(100; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i8> <i8 -5, i8 -4>, [[X:%.*]]101; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i8> [[TMP1]], [[X]]102; CHECK-NEXT: [[R:%.*]] = zext <2 x i8> [[TMP2]] to <2 x i16>103; CHECK-NEXT: ret <2 x i16> [[R]]104;105 %z = zext <2 x i8> %x to <2 x i16>106 %b = sub <2 x i16> <i16 -5, i16 -4>, %z107 %r = and <2 x i16> %b, %z108 ret <2 x i16> %r109}110 111define <2 x i16> @zext_mul_vec(<2 x i8> %x) {112; CHECK-LABEL: @zext_mul_vec(113; CHECK-NEXT: [[TMP1:%.*]] = mul <2 x i8> [[X:%.*]], <i8 3, i8 -2>114; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i8> [[TMP1]], [[X]]115; CHECK-NEXT: [[R:%.*]] = zext <2 x i8> [[TMP2]] to <2 x i16>116; CHECK-NEXT: ret <2 x i16> [[R]]117;118 %z = zext <2 x i8> %x to <2 x i16>119 %b = mul <2 x i16> %z, <i16 3, i16 -2>120 %r = and <2 x i16> %b, %z121 ret <2 x i16> %r122}123 124define <2 x i16> @zext_lshr_vec(<2 x i8> %x) {125; CHECK-LABEL: @zext_lshr_vec(126; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i8> [[X:%.*]], <i8 4, i8 2>127; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i8> [[TMP1]], [[X]]128; CHECK-NEXT: [[R:%.*]] = zext nneg <2 x i8> [[TMP2]] to <2 x i16>129; CHECK-NEXT: ret <2 x i16> [[R]]130;131 %z = zext <2 x i8> %x to <2 x i16>132 %b = lshr <2 x i16> %z, <i16 4, i16 2>133 %r = and <2 x i16> %b, %z134 ret <2 x i16> %r135}136 137define <2 x i16> @zext_ashr_vec(<2 x i8> %x) {138; CHECK-LABEL: @zext_ashr_vec(139; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i8> [[X:%.*]], <i8 2, i8 3>140; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i8> [[TMP1]], [[X]]141; CHECK-NEXT: [[R:%.*]] = zext nneg <2 x i8> [[TMP2]] to <2 x i16>142; CHECK-NEXT: ret <2 x i16> [[R]]143;144 %z = zext <2 x i8> %x to <2 x i16>145 %b = ashr <2 x i16> %z, <i16 2, i16 3>146 %r = and <2 x i16> %b, %z147 ret <2 x i16> %r148}149 150define <2 x i16> @zext_shl_vec(<2 x i8> %x) {151; CHECK-LABEL: @zext_shl_vec(152; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i8> [[X:%.*]], <i8 3, i8 2>153; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i8> [[TMP1]], [[X]]154; CHECK-NEXT: [[R:%.*]] = zext <2 x i8> [[TMP2]] to <2 x i16>155; CHECK-NEXT: ret <2 x i16> [[R]]156;157 %z = zext <2 x i8> %x to <2 x i16>158 %b = shl <2 x i16> %z, <i16 3, i16 2>159 %r = and <2 x i16> %b, %z160 ret <2 x i16> %r161}162 163; Don't create poison by narrowing a shift below the shift amount.164 165define <2 x i16> @zext_lshr_vec_overshift(<2 x i8> %x) {166; CHECK-LABEL: @zext_lshr_vec_overshift(167; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>168; CHECK-NEXT: [[B:%.*]] = lshr <2 x i16> [[Z]], <i16 4, i16 8>169; CHECK-NEXT: [[R:%.*]] = and <2 x i16> [[B]], [[Z]]170; CHECK-NEXT: ret <2 x i16> [[R]]171;172 %z = zext <2 x i8> %x to <2 x i16>173 %b = lshr <2 x i16> %z, <i16 4, i16 8>174 %r = and <2 x i16> %b, %z175 ret <2 x i16> %r176}177 178define <2 x i16> @zext_lshr_vec_undef(<2 x i8> %x) {179; CHECK-LABEL: @zext_lshr_vec_undef(180; CHECK-NEXT: ret <2 x i16> poison181;182 %z = zext <2 x i8> %x to <2 x i16>183 %b = lshr <2 x i16> %z, undef184 %r = and <2 x i16> %b, %z185 ret <2 x i16> %r186}187 188; Don't create poison by narrowing a shift below the shift amount.189 190define <2 x i16> @zext_shl_vec_overshift(<2 x i8> %x) {191; CHECK-LABEL: @zext_shl_vec_overshift(192; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>193; CHECK-NEXT: [[B:%.*]] = shl <2 x i16> [[Z]], <i16 8, i16 2>194; CHECK-NEXT: [[R:%.*]] = and <2 x i16> [[B]], [[Z]]195; CHECK-NEXT: ret <2 x i16> [[R]]196;197 %z = zext <2 x i8> %x to <2 x i16>198 %b = shl <2 x i16> %z, <i16 8, i16 2>199 %r = and <2 x i16> %b, %z200 ret <2 x i16> %r201}202 203define <2 x i16> @zext_shl_vec_undef(<2 x i8> %x) {204; CHECK-LABEL: @zext_shl_vec_undef(205; CHECK-NEXT: ret <2 x i16> poison206;207 %z = zext <2 x i8> %x to <2 x i16>208 %b = shl <2 x i16> %z, undef209 %r = and <2 x i16> %b, %z210 ret <2 x i16> %r211}212