89 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=instcombine -S | FileCheck %s3 4define i5 @XorZextXor(i3 %a) {5; CHECK-LABEL: @XorZextXor(6; CHECK-NEXT: [[CAST:%.*]] = zext i3 [[A:%.*]] to i57; CHECK-NEXT: [[OP2:%.*]] = xor i5 [[CAST]], 158; CHECK-NEXT: ret i5 [[OP2]]9;10 %op1 = xor i3 %a, 311 %cast = zext i3 %op1 to i512 %op2 = xor i5 %cast, 1213 ret i5 %op214}15 16define <2 x i32> @XorZextXorVec(<2 x i1> %a) {17; CHECK-LABEL: @XorZextXorVec(18; CHECK-NEXT: [[CAST:%.*]] = zext <2 x i1> [[A:%.*]] to <2 x i32>19; CHECK-NEXT: [[OP2:%.*]] = xor <2 x i32> [[CAST]], <i32 2, i32 1>20; CHECK-NEXT: ret <2 x i32> [[OP2]]21;22 %op1 = xor <2 x i1> %a, <i1 true, i1 false>23 %cast = zext <2 x i1> %op1 to <2 x i32>24 %op2 = xor <2 x i32> %cast, <i32 3, i32 1>25 ret <2 x i32> %op226}27 28define i5 @OrZextOr(i3 %a) {29; CHECK-LABEL: @OrZextOr(30; CHECK-NEXT: [[CAST:%.*]] = zext i3 [[A:%.*]] to i531; CHECK-NEXT: [[OP2:%.*]] = or i5 [[CAST]], 1132; CHECK-NEXT: ret i5 [[OP2]]33;34 %op1 = or i3 %a, 335 %cast = zext i3 %op1 to i536 %op2 = or i5 %cast, 837 ret i5 %op238}39 40define <2 x i32> @OrZextOrVec(<2 x i2> %a) {41; CHECK-LABEL: @OrZextOrVec(42; CHECK-NEXT: [[CAST:%.*]] = zext <2 x i2> [[A:%.*]] to <2 x i32>43; CHECK-NEXT: [[OP2:%.*]] = or <2 x i32> [[CAST]], <i32 3, i32 5>44; CHECK-NEXT: ret <2 x i32> [[OP2]]45;46 %op1 = or <2 x i2> %a, <i2 2, i2 0>47 %cast = zext <2 x i2> %op1 to <2 x i32>48 %op2 = or <2 x i32> %cast, <i32 1, i32 5>49 ret <2 x i32> %op250}51 52; Unlike the rest, this case is handled by SimplifyDemandedBits / ShrinkDemandedConstant.53 54define i5 @AndZextAnd(i3 %a) {55; CHECK-LABEL: @AndZextAnd(56; CHECK-NEXT: [[TMP1:%.*]] = and i3 [[A:%.*]], 257; CHECK-NEXT: [[OP2:%.*]] = zext nneg i3 [[TMP1]] to i558; CHECK-NEXT: ret i5 [[OP2]]59;60 %op1 = and i3 %a, 361 %cast = zext i3 %op1 to i562 %op2 = and i5 %cast, 1463 ret i5 %op264}65 66define <2 x i32> @AndZextAndVec(<2 x i8> %a) {67; CHECK-LABEL: @AndZextAndVec(68; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> [[A:%.*]], <i8 5, i8 0>69; CHECK-NEXT: [[OP2:%.*]] = zext nneg <2 x i8> [[TMP1]] to <2 x i32>70; CHECK-NEXT: ret <2 x i32> [[OP2]]71;72 %op1 = and <2 x i8> %a, <i8 7, i8 0>73 %cast = zext <2 x i8> %op1 to <2 x i32>74 %op2 = and <2 x i32> %cast, <i32 261, i32 1>75 ret <2 x i32> %op276}77 78define i24 @zext_nneg(i16 %a) {79; CHECK-LABEL: @zext_nneg(80; CHECK-NEXT: [[TMP1:%.*]] = and i16 [[A:%.*]], 3276781; CHECK-NEXT: [[AND2:%.*]] = zext nneg i16 [[TMP1]] to i2482; CHECK-NEXT: ret i24 [[AND2]]83;84 %and1 = and i16 %a, 3276785 %resize = zext nneg i16 %and1 to i2486 %and2 = and i24 %resize, 838860787 ret i24 %and288}89