245 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 22; RUN: opt < %s -passes=instcombine -S | FileCheck %s3 4define i64 @add_select_zext(i1 %c) {5; CHECK-LABEL: define i64 @add_select_zext6; CHECK-SAME: (i1 [[C:%.*]]) {7; CHECK-NEXT: [[ADD:%.*]] = select i1 [[C]], i64 65, i64 18; CHECK-NEXT: ret i64 [[ADD]]9;10 %sel = select i1 %c, i64 64, i64 111 %ext = zext i1 %c to i6412 %add = add i64 %sel, %ext13 ret i64 %add14}15 16define i64 @add_select_sext(i1 %c) {17; CHECK-LABEL: define i64 @add_select_sext18; CHECK-SAME: (i1 [[C:%.*]]) {19; CHECK-NEXT: [[ADD:%.*]] = select i1 [[C]], i64 63, i64 120; CHECK-NEXT: ret i64 [[ADD]]21;22 %sel = select i1 %c, i64 64, i64 123 %ext = sext i1 %c to i6424 %add = add i64 %sel, %ext25 ret i64 %add26}27 28define i64 @add_select_not_zext(i1 %c) {29; CHECK-LABEL: define i64 @add_select_not_zext30; CHECK-SAME: (i1 [[C:%.*]]) {31; CHECK-NEXT: [[ADD:%.*]] = select i1 [[C]], i64 64, i64 232; CHECK-NEXT: ret i64 [[ADD]]33;34 %sel = select i1 %c, i64 64, i64 135 %not.c = xor i1 %c, true36 %ext = zext i1 %not.c to i6437 %add = add i64 %sel, %ext38 ret i64 %add39}40 41define i64 @add_select_not_sext(i1 %c) {42; CHECK-LABEL: define i64 @add_select_not_sext43; CHECK-SAME: (i1 [[C:%.*]]) {44; CHECK-NEXT: [[ADD:%.*]] = select i1 [[C]], i64 64, i64 045; CHECK-NEXT: ret i64 [[ADD]]46;47 %sel = select i1 %c, i64 64, i64 148 %not.c = xor i1 %c, true49 %ext = sext i1 %not.c to i6450 %add = add i64 %sel, %ext51 ret i64 %add52}53 54define i64 @sub_select_sext(i1 %c, i64 %arg) {55; CHECK-LABEL: define i64 @sub_select_sext56; CHECK-SAME: (i1 [[C:%.*]], i64 [[ARG:%.*]]) {57; CHECK-NEXT: [[SUB:%.*]] = select i1 [[C]], i64 65, i64 [[ARG]]58; CHECK-NEXT: ret i64 [[SUB]]59;60 %sel = select i1 %c, i64 64, i64 %arg61 %ext = sext i1 %c to i6462 %sub = sub i64 %sel, %ext63 ret i64 %sub64}65 66define i64 @sub_select_not_zext(i1 %c, i64 %arg) {67; CHECK-LABEL: define i64 @sub_select_not_zext68; CHECK-SAME: (i1 [[C:%.*]], i64 [[ARG:%.*]]) {69; CHECK-NEXT: [[SUB:%.*]] = select i1 [[C]], i64 [[ARG]], i64 6370; CHECK-NEXT: ret i64 [[SUB]]71;72 %sel = select i1 %c, i64 %arg, i64 6473 %not.c = xor i1 %c, true74 %ext = zext i1 %not.c to i6475 %sub = sub i64 %sel, %ext76 ret i64 %sub77}78 79define i64 @sub_select_not_sext(i1 %c, i64 %arg) {80; CHECK-LABEL: define i64 @sub_select_not_sext81; CHECK-SAME: (i1 [[C:%.*]], i64 [[ARG:%.*]]) {82; CHECK-NEXT: [[SUB:%.*]] = select i1 [[C]], i64 [[ARG]], i64 6583; CHECK-NEXT: ret i64 [[SUB]]84;85 %sel = select i1 %c, i64 %arg, i64 6486 %not.c = xor i1 %c, true87 %ext = sext i1 %not.c to i6488 %sub = sub i64 %sel, %ext89 ret i64 %sub90}91 92define i64 @mul_select_zext(i1 %c, i64 %arg) {93; CHECK-LABEL: define i64 @mul_select_zext94; CHECK-SAME: (i1 [[C:%.*]], i64 [[ARG:%.*]]) {95; CHECK-NEXT: [[MUL:%.*]] = select i1 [[C]], i64 [[ARG]], i64 096; CHECK-NEXT: ret i64 [[MUL]]97;98 %sel = select i1 %c, i64 %arg, i64 199 %ext = zext i1 %c to i64100 %mul = mul i64 %sel, %ext101 ret i64 %mul102}103 104define i64 @mul_select_sext(i1 %c) {105; CHECK-LABEL: define i64 @mul_select_sext106; CHECK-SAME: (i1 [[C:%.*]]) {107; CHECK-NEXT: [[MUL:%.*]] = select i1 [[C]], i64 -64, i64 0108; CHECK-NEXT: ret i64 [[MUL]]109;110 %sel = select i1 %c, i64 64, i64 1111 %ext = sext i1 %c to i64112 %mul = mul i64 %sel, %ext113 ret i64 %mul114}115 116define i64 @select_zext_different_condition(i1 %c, i1 %d) {117; CHECK-LABEL: define i64 @select_zext_different_condition118; CHECK-SAME: (i1 [[C:%.*]], i1 [[D:%.*]]) {119; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C]], i64 64, i64 1120; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[D]] to i64121; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i64 [[SEL]], [[EXT]]122; CHECK-NEXT: ret i64 [[ADD]]123;124 %sel = select i1 %c, i64 64, i64 1125 %ext = zext i1 %d to i64126 %add = add i64 %sel, %ext127 ret i64 %add128}129 130define <2 x i64> @vector_test(i1 %c) {131; CHECK-LABEL: define <2 x i64> @vector_test132; CHECK-SAME: (i1 [[C:%.*]]) {133; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C]], <2 x i64> splat (i64 64), <2 x i64> splat (i64 1)134; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[C]] to i64135; CHECK-NEXT: [[VEC0:%.*]] = insertelement <2 x i64> poison, i64 [[EXT]], i64 0136; CHECK-NEXT: [[VEC1:%.*]] = shufflevector <2 x i64> [[VEC0]], <2 x i64> poison, <2 x i32> zeroinitializer137; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw <2 x i64> [[SEL]], [[VEC1]]138; CHECK-NEXT: ret <2 x i64> [[ADD]]139;140 %sel = select i1 %c, <2 x i64> <i64 64, i64 64>, <2 x i64> <i64 1, i64 1>141 %ext = zext i1 %c to i64142 %vec0 = insertelement <2 x i64> undef, i64 %ext, i32 0143 %vec1 = insertelement <2 x i64> %vec0, i64 %ext, i32 1144 %add = add <2 x i64> %sel, %vec1145 ret <2 x i64> %add146}147 148define i64 @multiuse_add(i1 %c) {149; CHECK-LABEL: define i64 @multiuse_add150; CHECK-SAME: (i1 [[C:%.*]]) {151; CHECK-NEXT: [[ADD2:%.*]] = select i1 [[C]], i64 66, i64 2152; CHECK-NEXT: ret i64 [[ADD2]]153;154 %sel = select i1 %c, i64 64, i64 1155 %ext = zext i1 %c to i64156 %add = add i64 %sel, %ext157 %add2 = add i64 %add, 1158 ret i64 %add2159}160 161define i64 @multiuse_select(i1 %c) {162; CHECK-LABEL: define i64 @multiuse_select163; CHECK-SAME: (i1 [[C:%.*]]) {164; CHECK-NEXT: [[MUL:%.*]] = select i1 [[C]], i64 4032, i64 0165; CHECK-NEXT: ret i64 [[MUL]]166;167 %sel = select i1 %c, i64 64, i64 0168 %ext = zext i1 %c to i64169 %add = sub i64 %sel, %ext170 %mul = mul i64 %sel, %add171 ret i64 %mul172}173 174define i64 @select_non_const_sides(i1 %c, i64 %arg1, i64 %arg2) {175; CHECK-LABEL: define i64 @select_non_const_sides176; CHECK-SAME: (i1 [[C:%.*]], i64 [[ARG1:%.*]], i64 [[ARG2:%.*]]) {177; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[ARG1]], -1178; CHECK-NEXT: [[SUB:%.*]] = select i1 [[C]], i64 [[TMP1]], i64 [[ARG2]]179; CHECK-NEXT: ret i64 [[SUB]]180;181 %ext = zext i1 %c to i64182 %sel = select i1 %c, i64 %arg1, i64 %arg2183 %sub = sub i64 %sel, %ext184 ret i64 %sub185}186 187define i6 @sub_select_sext_op_swapped_non_const_args(i1 %c, i6 %argT, i6 %argF) {188; CHECK-LABEL: define i6 @sub_select_sext_op_swapped_non_const_args189; CHECK-SAME: (i1 [[C:%.*]], i6 [[ARGT:%.*]], i6 [[ARGF:%.*]]) {190; CHECK-NEXT: [[TMP1:%.*]] = xor i6 [[ARGT]], -1191; CHECK-NEXT: [[TMP2:%.*]] = sub i6 0, [[ARGF]]192; CHECK-NEXT: [[SUB:%.*]] = select i1 [[C]], i6 [[TMP1]], i6 [[TMP2]]193; CHECK-NEXT: ret i6 [[SUB]]194;195 %sel = select i1 %c, i6 %argT, i6 %argF196 %ext = sext i1 %c to i6197 %sub = sub i6 %ext, %sel198 ret i6 %sub199}200 201define i6 @sub_select_zext_op_swapped_non_const_args(i1 %c, i6 %argT, i6 %argF) {202; CHECK-LABEL: define i6 @sub_select_zext_op_swapped_non_const_args203; CHECK-SAME: (i1 [[C:%.*]], i6 [[ARGT:%.*]], i6 [[ARGF:%.*]]) {204; CHECK-NEXT: [[TMP1:%.*]] = sub i6 1, [[ARGT]]205; CHECK-NEXT: [[TMP2:%.*]] = sub i6 0, [[ARGF]]206; CHECK-NEXT: [[SUB:%.*]] = select i1 [[C]], i6 [[TMP1]], i6 [[TMP2]]207; CHECK-NEXT: ret i6 [[SUB]]208;209 %sel = select i1 %c, i6 %argT, i6 %argF210 %ext = zext i1 %c to i6211 %sub = sub i6 %ext, %sel212 ret i6 %sub213}214 215define <2 x i8> @vectorized_add(<2 x i1> %c, <2 x i8> %arg) {216; CHECK-LABEL: define <2 x i8> @vectorized_add217; CHECK-SAME: (<2 x i1> [[C:%.*]], <2 x i8> [[ARG:%.*]]) {218; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i8> [[ARG]], splat (i8 1)219; CHECK-NEXT: [[ADD:%.*]] = select <2 x i1> [[C]], <2 x i8> [[TMP1]], <2 x i8> splat (i8 1)220; CHECK-NEXT: ret <2 x i8> [[ADD]]221;222 %zext = zext <2 x i1> %c to <2 x i8>223 %sel = select <2 x i1> %c, <2 x i8> %arg, <2 x i8> <i8 1, i8 1>224 %add = add <2 x i8> %sel, %zext225 ret <2 x i8> %add226}227 228@b = external global [72 x i32]229@c = external global i32230 231define i64 @pr64669(i64 %a) {232; CHECK-LABEL: define i64 @pr64669233; CHECK-SAME: (i64 [[A:%.*]]) {234; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq ptr getelementptr inbounds nuw (i8, ptr @b, i64 100), @c235; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[A]], 1236; CHECK-NEXT: [[ADD:%.*]] = select i1 [[CMP_NOT]], i64 0, i64 [[TMP1]]237; CHECK-NEXT: ret i64 [[ADD]]238;239 %cmp = icmp ne ptr getelementptr inbounds ([72 x i32], ptr @b, i64 0, i64 25), @c240 %mul = select i1 %cmp, i64 %a, i64 0241 %conv3 = zext i1 %cmp to i64242 %add = add nsw i64 %mul, %conv3243 ret i64 %add244}245