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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=instcombine -S | FileCheck %s3 4declare void @use(i32)5declare void @use_f32(float)6declare void @use_v2f16(<2 x half>)7declare void @use_v2i8(<2 x i8>)8declare i32 @llvm.sadd.sat.i32(i32, i32)9declare <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8>, <2 x i8>)10 11define i32 @test1(i1 %c, i32 %x, i32 %y) {12; CHECK-LABEL: @test1(13; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[X:%.*]]14; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 [[SUB]], i32 [[Y:%.*]]15; CHECK-NEXT: [[ADD:%.*]] = add i32 [[COND]], [[X]]16; CHECK-NEXT: ret i32 [[ADD]]17;18 %sub = sub i32 0, %x19 %cond = select i1 %c, i32 %sub, i32 %y20 %add = add i32 %cond, %x21 ret i32 %add22}23 24define i32 @test2(i1 %c, i32 %x, i32 %y) {25; CHECK-LABEL: @test2(26; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[X:%.*]]27; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 [[SUB]], i32 [[X]]28; CHECK-NEXT: [[ADD:%.*]] = add i32 [[COND]], [[X]]29; CHECK-NEXT: ret i32 [[ADD]]30;31 %sub = sub i32 0, %x32 %cond = select i1 %c, i32 %sub, i32 %x33 %add = add i32 %cond, %x34 ret i32 %add35}36 37define i32 @test3(i1 %c, i32 %x, i32 %y) {38; CHECK-LABEL: @test3(39; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[X:%.*]]40; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 [[SUB]], i32 141; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[COND]], [[X]]42; CHECK-NEXT: ret i32 [[MUL]]43;44 %sub = sub i32 0, %x45 %cond = select i1 %c, i32 %sub, i32 146 %mul = mul i32 %cond, %x47 ret i32 %mul48}49 50define i32 @test4(i1 %c, i32 %x, i32 %y) {51; CHECK-LABEL: @test4(52; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[X:%.*]]53; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 [[SUB]], i32 154; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[COND]], [[X]]55; CHECK-NEXT: ret i32 [[MUL]]56;57 %sub = sub i32 0, %x58 %cond = select i1 %c, i32 %sub, i32 159 %mul = mul i32 %cond, %x60 ret i32 %mul61}62 63define i32 @test5(i1 %c, i32 %x, i32 %y) {64; CHECK-LABEL: @test5(65; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 [[X:%.*]], i32 066; CHECK-NEXT: [[ADD:%.*]] = add i32 [[COND]], [[X]]67; CHECK-NEXT: ret i32 [[ADD]]68;69 %cond = select i1 %c, i32 %x, i32 070 %add = add i32 %cond, %x71 ret i32 %add72}73 74define i32 @test_sub_deduce_true(i32 %x, i32 %y) {75; CHECK-LABEL: @test_sub_deduce_true(76; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[X:%.*]], 977; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.sadd.sat.i32(i32 [[X]], i32 [[Y:%.*]])78; CHECK-NEXT: [[SUB:%.*]] = select i1 [[C]], i32 15, i32 [[TMP1]]79; CHECK-NEXT: ret i32 [[SUB]]80;81 %c = icmp eq i32 %x, 982 %cond = select i1 %c, i32 6, i32 %y83 %sub = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %cond)84 ret i32 %sub85}86 87define i32 @test_sub_deduce_true_no_const_fold(i32 %x, i32 %y) {88; CHECK-LABEL: @test_sub_deduce_true_no_const_fold(89; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[X:%.*]], 990; CHECK-NEXT: [[COND:%.*]] = select i1 [[C]], i32 [[Y:%.*]], i32 691; CHECK-NEXT: [[SUB:%.*]] = call i32 @llvm.sadd.sat.i32(i32 [[X]], i32 [[COND]])92; CHECK-NEXT: ret i32 [[SUB]]93;94 %c = icmp eq i32 %x, 995 %cond = select i1 %c, i32 %y, i32 696 %sub = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %cond)97 ret i32 %sub98}99 100define i32 @test_sub_deduce_false(i32 %x, i32 %y) {101; CHECK-LABEL: @test_sub_deduce_false(102; CHECK-NEXT: [[C_NOT:%.*]] = icmp eq i32 [[X:%.*]], 9103; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.sadd.sat.i32(i32 [[X]], i32 [[Y:%.*]])104; CHECK-NEXT: [[SUB:%.*]] = select i1 [[C_NOT]], i32 16, i32 [[TMP1]]105; CHECK-NEXT: ret i32 [[SUB]]106;107 %c = icmp ne i32 %x, 9108 %cond = select i1 %c, i32 %y, i32 7109 %sub = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %cond)110 ret i32 %sub111}112 113define <2 x i8> @test_sub_dont_deduce_with_undef_cond_vec(<2 x i8> %x, <2 x i8> %y) {114; CHECK-LABEL: @test_sub_dont_deduce_with_undef_cond_vec(115; CHECK-NEXT: [[C_NOT:%.*]] = icmp eq <2 x i8> [[X:%.*]], <i8 9, i8 undef>116; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[C_NOT]], <2 x i8> splat (i8 7), <2 x i8> [[Y:%.*]]117; CHECK-NEXT: [[SUB:%.*]] = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> [[X]], <2 x i8> [[COND]])118; CHECK-NEXT: ret <2 x i8> [[SUB]]119;120 %c = icmp ne <2 x i8> %x, <i8 9, i8 undef>121 %cond = select <2 x i1> %c, <2 x i8> %y, <2 x i8> <i8 7, i8 7>122 %sub = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %x, <2 x i8> %cond)123 ret <2 x i8> %sub124}125 126define <2 x i8> @test_sub_dont_deduce_with_poison_cond_vec(<2 x i8> %x, <2 x i8> %y) {127; CHECK-LABEL: @test_sub_dont_deduce_with_poison_cond_vec(128; CHECK-NEXT: [[C_NOT:%.*]] = icmp eq <2 x i8> [[X:%.*]], <i8 poison, i8 9>129; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[C_NOT]], <2 x i8> splat (i8 7), <2 x i8> [[Y:%.*]]130; CHECK-NEXT: [[SUB:%.*]] = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> [[X]], <2 x i8> [[COND]])131; CHECK-NEXT: ret <2 x i8> [[SUB]]132;133 %c = icmp ne <2 x i8> %x, <i8 poison, i8 9>134 %cond = select <2 x i1> %c, <2 x i8> %y, <2 x i8> <i8 7, i8 7>135 %sub = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %x, <2 x i8> %cond)136 ret <2 x i8> %sub137}138 139 140define <2 x i8> @test_sub_deduce_with_undef_val_vec(<2 x i8> %x, <2 x i8> %y) {141; CHECK-LABEL: @test_sub_deduce_with_undef_val_vec(142; CHECK-NEXT: [[C_NOT:%.*]] = icmp eq <2 x i8> [[X:%.*]], <i8 1, i8 2>143; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> [[X]], <2 x i8> [[Y:%.*]])144; CHECK-NEXT: [[SUB:%.*]] = select <2 x i1> [[C_NOT]], <2 x i8> <i8 4, i8 -1>, <2 x i8> [[TMP1]]145; CHECK-NEXT: ret <2 x i8> [[SUB]]146;147 %c = icmp ne <2 x i8> %x, <i8 1, i8 2>148 %cond = select <2 x i1> %c, <2 x i8> %y, <2 x i8> <i8 3, i8 undef>149 %sub = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %x, <2 x i8> %cond)150 ret <2 x i8> %sub151}152 153 154define i32 @test6(i1 %c, i32 %x, i32 %y) {155; CHECK-LABEL: @test6(156; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 7, i32 [[X:%.*]]157; CHECK-NEXT: [[AND:%.*]] = and i32 [[COND]], [[X]]158; CHECK-NEXT: ret i32 [[AND]]159;160 %cond = select i1 %c, i32 7, i32 %x161 %and = and i32 %cond, %x162 ret i32 %and163}164 165define i32 @test7(i1 %c, i32 %x) {166; CHECK-LABEL: @test7(167; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[X:%.*]]168; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 [[X]], i32 [[SUB]]169; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[X]], [[COND]]170; CHECK-NEXT: ret i32 [[DIV]]171;172 %sub = sub i32 0, %x173 %cond = select i1 %c, i32 %x, i32 %sub174 %div = sdiv i32 %x, %cond175 ret i32 %div176}177 178 179define i32 @test8(i1 %c, i32 %x, i32 %y) {180; CHECK-LABEL: @test8(181; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 7, i32 [[Y:%.*]]182; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 42, [[COND]]183; CHECK-NEXT: ret i32 [[DIV]]184;185 %cond = select i1 %c, i32 7, i32 %y186 %div = sdiv i32 42, %cond187 ret i32 %div188}189 190define i32 @test9(i1 %c, i32 %x, i32 %y) {191; CHECK-LABEL: @test9(192; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 1, i32 [[X:%.*]]193; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[COND]]194; CHECK-NEXT: ret i32 [[SUB]]195;196 %cond = select i1 %c, i32 1, i32 %x197 %sub = sub nsw i32 0, %cond198 ret i32 %sub199}200 201define i32 @test10(i1 %c, i32 %x, i32 %y) {202; CHECK-LABEL: @test10(203; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 7, i32 [[Y:%.*]]204; CHECK-NEXT: [[DIV:%.*]] = udiv i32 42, [[COND]]205; CHECK-NEXT: ret i32 [[DIV]]206;207 %cond = select i1 %c, i32 7, i32 %y208 %div = udiv i32 42, %cond209 ret i32 %div210}211 212define i32 @test11(i1 %c, i32 %x, i32 %y) {213; CHECK-LABEL: @test11(214; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 7, i32 [[Y:%.*]]215; CHECK-NEXT: [[DIV:%.*]] = srem i32 42, [[COND]]216; CHECK-NEXT: ret i32 [[DIV]]217;218 %cond = select i1 %c, i32 7, i32 %y219 %div = srem i32 42, %cond220 ret i32 %div221}222 223define i32 @test12(i1 %c, i32 %x, i32 %y) {224; CHECK-LABEL: @test12(225; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 7, i32 [[Y:%.*]]226; CHECK-NEXT: [[DIV:%.*]] = urem i32 42, [[COND]]227; CHECK-NEXT: ret i32 [[DIV]]228;229 %cond = select i1 %c, i32 7, i32 %y230 %div = urem i32 42, %cond231 ret i32 %div232}233 234define i32 @extra_use(i1 %c, i32 %x, i32 %y) {235; CHECK-LABEL: @extra_use(236; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 1, i32 [[X:%.*]]237; CHECK-NEXT: tail call void @use(i32 [[COND]])238; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[COND]]239; CHECK-NEXT: ret i32 [[SUB]]240;241 %cond = select i1 %c, i32 1, i32 %x242 tail call void @use(i32 %cond)243 %sub = sub nsw i32 0, %cond244 ret i32 %sub245}246 247 248define i32 @extra_use2(i1 %c, i32 %x) {249; CHECK-LABEL: @extra_use2(250; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[X:%.*]]251; CHECK-NEXT: [[COND:%.*]] = select i1 [[C:%.*]], i32 [[X]], i32 [[SUB]]252; CHECK-NEXT: tail call void @use(i32 [[COND]])253; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[COND]], [[X]]254; CHECK-NEXT: ret i32 [[DIV]]255;256 %sub = sub i32 0, %x257 %cond = select i1 %c, i32 %x, i32 %sub258 tail call void @use(i32 %cond)259 %div = sdiv i32 %cond, %x260 ret i32 %div261}262 263define i32 @and_sel_op0(i1 %b) {264; CHECK-LABEL: @and_sel_op0(265; CHECK-NEXT: [[S:%.*]] = zext i1 [[B:%.*]] to i32266; CHECK-NEXT: ret i32 [[S]]267;268 %s = select i1 %b, i32 25, i32 0269 %r = and i32 %s, 1270 ret i32 %r271}272 273define i32 @and_sel_op0_use(i1 %b) {274; CHECK-LABEL: @and_sel_op0_use(275; CHECK-NEXT: [[S:%.*]] = select i1 [[B:%.*]], i32 25, i32 0276; CHECK-NEXT: call void @use(i32 [[S]])277; CHECK-NEXT: [[R:%.*]] = and i32 [[S]], 1278; CHECK-NEXT: ret i32 [[R]]279;280 %s = select i1 %b, i32 25, i32 0281 call void @use(i32 %s)282 %r = and i32 %s, 1283 ret i32 %r284}285 286define i32 @mul_sel_op0(i1 %b, i32 %x) {287; CHECK-LABEL: @mul_sel_op0(288; CHECK-NEXT: [[R:%.*]] = select i1 [[B:%.*]], i32 0, i32 42289; CHECK-NEXT: ret i32 [[R]]290;291 %d = udiv exact i32 42, %x292 %s = select i1 %b, i32 0, i32 %d293 %r = mul i32 %s, %x294 ret i32 %r295}296 297define i32 @mul_sel_op0_use(i1 %b, i32 %x) {298; CHECK-LABEL: @mul_sel_op0_use(299; CHECK-NEXT: [[D:%.*]] = udiv exact i32 42, [[X:%.*]]300; CHECK-NEXT: [[S:%.*]] = select i1 [[B:%.*]], i32 0, i32 [[D]]301; CHECK-NEXT: call void @use(i32 [[S]])302; CHECK-NEXT: [[R:%.*]] = mul i32 [[S]], [[X]]303; CHECK-NEXT: ret i32 [[R]]304;305 %d = udiv exact i32 42, %x306 %s = select i1 %b, i32 0, i32 %d307 call void @use(i32 %s)308 %r = mul i32 %s, %x309 ret i32 %r310}311 312define i32 @sub_sel_op1(i1 %b) {313; CHECK-LABEL: @sub_sel_op1(314; CHECK-NEXT: [[NOT_B:%.*]] = xor i1 [[B:%.*]], true315; CHECK-NEXT: [[R:%.*]] = zext i1 [[NOT_B]] to i32316; CHECK-NEXT: ret i32 [[R]]317;318 %s = select i1 %b, i32 42, i32 41319 %r = sub nsw i32 42, %s320 ret i32 %r321}322 323define i32 @sub_sel_op1_use(i1 %b) {324; CHECK-LABEL: @sub_sel_op1_use(325; CHECK-NEXT: [[S:%.*]] = select i1 [[B:%.*]], i32 42, i32 41326; CHECK-NEXT: call void @use(i32 [[S]])327; CHECK-NEXT: [[R:%.*]] = sub nuw nsw i32 42, [[S]]328; CHECK-NEXT: ret i32 [[R]]329;330 %s = select i1 %b, i32 42, i32 41331 call void @use(i32 %s)332 %r = sub nuw nsw i32 42, %s333 ret i32 %r334}335 336define float @fadd_sel_op0(i1 %b, float %x) {337; CHECK-LABEL: @fadd_sel_op0(338; CHECK-NEXT: [[R:%.*]] = select i1 [[B:%.*]], float 0xFFF0000000000000, float 0x7FF0000000000000339; CHECK-NEXT: ret float [[R]]340;341 %s = select i1 %b, float 0xFFF0000000000000, float 0x7FF0000000000000342 %r = fadd nnan float %s, %x343 ret float %r344}345 346define float @fadd_sel_op0_use(i1 %b, float %x) {347; CHECK-LABEL: @fadd_sel_op0_use(348; CHECK-NEXT: [[S:%.*]] = select i1 [[B:%.*]], float 0xFFF0000000000000, float 0x7FF0000000000000349; CHECK-NEXT: call void @use_f32(float [[S]])350; CHECK-NEXT: [[R:%.*]] = fadd nnan float [[S]], [[X:%.*]]351; CHECK-NEXT: ret float [[R]]352;353 %s = select i1 %b, float 0xFFF0000000000000, float 0x7FF0000000000000354 call void @use_f32(float %s)355 %r = fadd nnan float %s, %x356 ret float %r357}358 359define <2 x half> @fmul_sel_op1(i1 %b, <2 x half> %p) {360; CHECK-LABEL: @fmul_sel_op1(361; CHECK-NEXT: ret <2 x half> zeroinitializer362;363 %x = fadd <2 x half> %p, <half 1.0, half 2.0> ; thwart complexity-based canonicalization364 %s = select i1 %b, <2 x half> zeroinitializer, <2 x half> <half 0xHffff, half 0xHffff>365 %r = fmul nnan nsz <2 x half> %x, %s366 ret <2 x half> %r367}368 369define <2 x half> @fmul_sel_op1_use(i1 %b, <2 x half> %p) {370; CHECK-LABEL: @fmul_sel_op1_use(371; CHECK-NEXT: [[X:%.*]] = fadd <2 x half> [[P:%.*]], <half 0xH3C00, half 0xH4000>372; CHECK-NEXT: [[S:%.*]] = select i1 [[B:%.*]], <2 x half> zeroinitializer, <2 x half> splat (half 0xHFFFF)373; CHECK-NEXT: call void @use_v2f16(<2 x half> [[S]])374; CHECK-NEXT: [[R:%.*]] = fmul nnan nsz <2 x half> [[X]], [[S]]375; CHECK-NEXT: ret <2 x half> [[R]]376;377 %x = fadd <2 x half> %p, <half 1.0, half 2.0> ; thwart complexity-based canonicalization378 %s = select i1 %b, <2 x half> zeroinitializer, <2 x half> <half 0xHffff, half 0xHffff>379 call void @use_v2f16(<2 x half> %s)380 %r = fmul nnan nsz <2 x half> %x, %s381 ret <2 x half> %r382}383 384define i32 @ashr_sel_op1(i1 %b) {385; CHECK-LABEL: @ashr_sel_op1(386; CHECK-NEXT: [[R:%.*]] = select i1 [[B:%.*]], i32 -1, i32 -2387; CHECK-NEXT: ret i32 [[R]]388;389 %s = select i1 %b, i32 2, i32 0390 %r = ashr i32 -2, %s391 ret i32 %r392}393 394define i32 @ashr_sel_op1_use(i1 %b) {395; CHECK-LABEL: @ashr_sel_op1_use(396; CHECK-NEXT: [[S:%.*]] = select i1 [[B:%.*]], i32 2, i32 0397; CHECK-NEXT: call void @use(i32 [[S]])398; CHECK-NEXT: [[R:%.*]] = ashr i32 -2, [[S]]399; CHECK-NEXT: ret i32 [[R]]400;401 %s = select i1 %b, i32 2, i32 0402 call void @use(i32 %s)403 %r = ashr i32 -2, %s404 ret i32 %r405}406 407define i8 @commonArgWithOr0(i1 %arg0) {408; CHECK-LABEL: @commonArgWithOr0(409; CHECK-NEXT: [[V3:%.*]] = select i1 [[ARG0:%.*]], i8 17, i8 24410; CHECK-NEXT: ret i8 [[V3]]411;412 %v0 = zext i1 %arg0 to i8413 %v1 = select i1 %arg0, i8 0, i8 8414 %v2 = or i8 %v1, %v0415 %v3 = or i8 %v2, 16416 ret i8 %v3417}418 419define i8 @commonArgWithOr1(i1 %arg0) {420; CHECK-LABEL: @commonArgWithOr1(421; CHECK-NEXT: [[V3:%.*]] = select i1 [[ARG0:%.*]], i8 17, i8 23422; CHECK-NEXT: ret i8 [[V3]]423;424 %v0 = zext i1 %arg0 to i8425 %v1 = select i1 %arg0, i8 1, i8 7426 %v2 = or i8 %v1, %v0427 %v3 = or i8 %v2, 16428 ret i8 %v3429}430 431define i8 @commonArgWithOr2(i1 %arg0) {432; CHECK-LABEL: @commonArgWithOr2(433; CHECK-NEXT: [[V3:%.*]] = select i1 [[ARG0:%.*]], i8 21, i8 58434; CHECK-NEXT: ret i8 [[V3]]435;436 %v0 = zext i1 %arg0 to i8437 %v1 = select i1 %arg0, i8 21, i8 42438 %v2 = or i8 %v1, %v0439 %v3 = or i8 %v2, 16440 ret i8 %v3441}442 443define i8 @commonArgWithAnd0(i1 %arg0) {444; CHECK-LABEL: @commonArgWithAnd0(445; CHECK-NEXT: ret i8 16446;447 %v0 = zext i1 %arg0 to i8448 %v1 = select i1 %arg0, i8 0, i8 8449 %v2 = and i8 %v1, %v0450 %v3 = or i8 %v2, 16451 ret i8 %v3452}453 454define i8 @commonArgWithAnd1(i1 %arg0) {455; CHECK-LABEL: @commonArgWithAnd1(456; CHECK-NEXT: ret i8 16457;458 %v0 = zext i1 %arg0 to i8459 %v1 = select i1 %arg0, i8 8, i8 1460 %v2 = and i8 %v1, %v0461 %v3 = or i8 %v2, 16462 ret i8 %v3463}464 465define i8 @commonArgWithAnd2(i1 %arg0) {466; CHECK-LABEL: @commonArgWithAnd2(467; CHECK-NEXT: [[V2:%.*]] = zext i1 [[ARG0:%.*]] to i8468; CHECK-NEXT: [[V3:%.*]] = or disjoint i8 [[V2]], 16469; CHECK-NEXT: ret i8 [[V3]]470;471 %v0 = zext i1 %arg0 to i8472 %v1 = select i1 %arg0, i8 1, i8 7473 %v2 = and i8 %v1, %v0474 %v3 = or i8 %v2, 16475 ret i8 %v3476}477 478define i8 @commonArgWithAnd3(i1 %arg0) {479; CHECK-LABEL: @commonArgWithAnd3(480; CHECK-NEXT: [[V2:%.*]] = zext i1 [[ARG0:%.*]] to i8481; CHECK-NEXT: [[V3:%.*]] = or disjoint i8 [[V2]], 16482; CHECK-NEXT: ret i8 [[V3]]483;484 %v0 = zext i1 %arg0 to i8485 %v1 = select i1 %arg0, i8 21, i8 42486 %v2 = and i8 %v1, %v0487 %v3 = or i8 %v2, 16488 ret i8 %v3489}490 491define i8 @commonArgWithXor0(i1 %arg0) {492; CHECK-LABEL: @commonArgWithXor0(493; CHECK-NEXT: [[V3:%.*]] = select i1 [[ARG0:%.*]], i8 17, i8 24494; CHECK-NEXT: ret i8 [[V3]]495;496 %v0 = zext i1 %arg0 to i8497 %v1 = select i1 %arg0, i8 0, i8 8498 %v2 = xor i8 %v1, %v0499 %v3 = or i8 %v2, 16500 ret i8 %v3501}502 503define i8 @commonArgWithXor1(i1 %arg0) {504; CHECK-LABEL: @commonArgWithXor1(505; CHECK-NEXT: [[V2:%.*]] = select i1 [[ARG0:%.*]], i8 8, i8 1506; CHECK-NEXT: ret i8 [[V2]]507;508 %v0 = zext i1 %arg0 to i8509 %v1 = select i1 %arg0, i8 9, i8 1510 %v2 = xor i8 %v1, %v0511 ret i8 %v2512}513 514define i8 @commonArgWithXor2(i1 %arg0) {515; CHECK-LABEL: @commonArgWithXor2(516; CHECK-NEXT: [[V3:%.*]] = select i1 [[ARG0:%.*]], i8 16, i8 23517; CHECK-NEXT: ret i8 [[V3]]518;519 %v0 = zext i1 %arg0 to i8520 %v1 = select i1 %arg0, i8 1, i8 7521 %v2 = xor i8 %v1, %v0522 %v3 = or i8 %v2, 16523 ret i8 %v3524}525 526define i8 @commonArgWithXor3(i1 %arg0) {527; CHECK-LABEL: @commonArgWithXor3(528; CHECK-NEXT: [[V3:%.*]] = select i1 [[ARG0:%.*]], i8 20, i8 61529; CHECK-NEXT: ret i8 [[V3]]530;531 %v0 = zext i1 %arg0 to i8532 %v1 = select i1 %arg0, i8 21, i8 45533 %v2 = xor i8 %v1, %v0534 %v3 = or i8 %v2, 16535 ret i8 %v3536}537 538define i8 @commonArgWithAdd0(i1 %arg0) {539; CHECK-LABEL: @commonArgWithAdd0(540; CHECK-NEXT: [[V3:%.*]] = select i1 [[ARG0:%.*]], i8 22, i8 61541; CHECK-NEXT: ret i8 [[V3]]542;543 %v0 = zext i1 %arg0 to i8544 %v1 = select i1 %arg0, i8 21, i8 45545 %v2 = add i8 %v1, %v0546 %v3 = or i8 %v2, 16547 ret i8 %v3548}549 550define i32 @OrSelectIcmpZero(i32 %a, i32 %b) {551; CHECK-LABEL: @OrSelectIcmpZero(552; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], 0553; CHECK-NEXT: [[OR:%.*]] = select i1 [[CMP]], i32 [[B:%.*]], i32 [[A]]554; CHECK-NEXT: ret i32 [[OR]]555;556 %cmp = icmp eq i32 %a, 0557 %sel = select i1 %cmp, i32 %b, i32 0558 %or = or i32 %sel, %a559 ret i32 %or560}561 562define i32 @OrSelectIcmpNonZero(i32 %a, i32 %b) {563; CHECK-LABEL: @OrSelectIcmpNonZero(564; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], 0565; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 [[B:%.*]], i32 42566; CHECK-NEXT: [[OR:%.*]] = or i32 [[SEL]], [[A]]567; CHECK-NEXT: ret i32 [[OR]]568;569 %cmp = icmp eq i32 %a, 0570 %sel = select i1 %cmp, i32 %b, i32 42571 %or = or i32 %sel, %a572 ret i32 %or573}574