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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=instcombine -S < %s | FileCheck %s3; RUN: opt -passes=instcombine -use-constant-int-for-fixed-length-splat -S < %s | FileCheck %s4 5; PR54386 7define i32 @test1(i32 %a, i32 %b) nounwind readnone {8; CHECK-LABEL: @test1(9; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[B:%.*]], [[A:%.*]]10; CHECK-NEXT: [[T2:%.*]] = icmp sgt i32 [[TMP1]], -111; CHECK-NEXT: [[T3:%.*]] = zext i1 [[T2]] to i3212; CHECK-NEXT: ret i32 [[T3]]13;14 %t0 = icmp sgt i32 %a, -115 %t1 = icmp slt i32 %b, 016 %t2 = xor i1 %t1, %t017 %t3 = zext i1 %t2 to i3218 ret i32 %t319}20 21; TODO: This optimizes partially but not all the way.22define i32 @test2(i32 %a, i32 %b) nounwind readnone {23; CHECK-LABEL: @test2(24; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]25; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 326; CHECK-NEXT: [[DOTLOBIT:%.*]] = and i32 [[TMP2]], 127; CHECK-NEXT: [[T3:%.*]] = xor i32 [[DOTLOBIT]], 128; CHECK-NEXT: ret i32 [[T3]]29;30 %t0 = and i32 %a, 831 %t1 = and i32 %b, 832 %t2 = icmp eq i32 %t0, %t133 %t3 = zext i1 %t2 to i3234 ret i32 %t335}36 37define i32 @test3(i32 %a, i32 %b) nounwind readnone {38; CHECK-LABEL: @test3(39; CHECK-NEXT: [[T2_UNSHIFTED:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]40; CHECK-NEXT: [[T2:%.*]] = icmp sgt i32 [[T2_UNSHIFTED]], -141; CHECK-NEXT: [[T3:%.*]] = zext i1 [[T2]] to i3242; CHECK-NEXT: ret i32 [[T3]]43;44 %t0 = lshr i32 %a, 3145 %t1 = lshr i32 %b, 3146 %t2 = icmp eq i32 %t0, %t147 %t3 = zext i1 %t2 to i3248 ret i32 %t349}50 51define <2 x i32> @test3vec(<2 x i32> %a, <2 x i32> %b) nounwind readnone {52; CHECK-LABEL: @test3vec(53; CHECK-NEXT: [[T2_UNSHIFTED:%.*]] = xor <2 x i32> [[A:%.*]], [[B:%.*]]54; CHECK-NEXT: [[T2:%.*]] = icmp sgt <2 x i32> [[T2_UNSHIFTED]], splat (i32 -1)55; CHECK-NEXT: [[T3:%.*]] = zext <2 x i1> [[T2]] to <2 x i32>56; CHECK-NEXT: ret <2 x i32> [[T3]]57;58 %t0 = lshr <2 x i32> %a, <i32 31, i32 31>59 %t1 = lshr <2 x i32> %b, <i32 31, i32 31>60 %t2 = icmp eq <2 x i32> %t0, %t161 %t3 = zext <2 x i1> %t2 to <2 x i32>62 ret <2 x i32> %t363}64 65define <2 x i32> @test3vec_poison1(<2 x i32> %a, <2 x i32> %b) nounwind readnone {66; CHECK-LABEL: @test3vec_poison1(67; CHECK-NEXT: [[T2_UNSHIFTED:%.*]] = xor <2 x i32> [[A:%.*]], [[B:%.*]]68; CHECK-NEXT: [[T2:%.*]] = icmp ult <2 x i32> [[T2_UNSHIFTED]], splat (i32 16777216)69; CHECK-NEXT: [[T3:%.*]] = zext <2 x i1> [[T2]] to <2 x i32>70; CHECK-NEXT: ret <2 x i32> [[T3]]71;72 %t0 = lshr <2 x i32> %a, <i32 24, i32 poison>73 %t1 = lshr <2 x i32> %b, <i32 24, i32 24>74 %t2 = icmp eq <2 x i32> %t0, %t175 %t3 = zext <2 x i1> %t2 to <2 x i32>76 ret <2 x i32> %t377}78 79define <2 x i32> @test3vec_poison2(<2 x i32> %a, <2 x i32> %b) nounwind readnone {80; CHECK-LABEL: @test3vec_poison2(81; CHECK-NEXT: [[T2_UNSHIFTED:%.*]] = xor <2 x i32> [[A:%.*]], [[B:%.*]]82; CHECK-NEXT: [[T2:%.*]] = icmp ult <2 x i32> [[T2_UNSHIFTED]], splat (i32 131072)83; CHECK-NEXT: [[T3:%.*]] = zext <2 x i1> [[T2]] to <2 x i32>84; CHECK-NEXT: ret <2 x i32> [[T3]]85;86 %t0 = lshr <2 x i32> %a, <i32 poison, i32 17>87 %t1 = lshr <2 x i32> %b, <i32 poison, i32 17>88 %t2 = icmp eq <2 x i32> %t0, %t189 %t3 = zext <2 x i1> %t2 to <2 x i32>90 ret <2 x i32> %t391}92 93; negative test94 95define <2 x i32> @test3vec_diff(<2 x i32> %a, <2 x i32> %b) nounwind readnone {96; CHECK-LABEL: @test3vec_diff(97; CHECK-NEXT: [[T0:%.*]] = lshr <2 x i32> [[A:%.*]], splat (i32 31)98; CHECK-NEXT: [[T1:%.*]] = lshr <2 x i32> [[B:%.*]], splat (i32 30)99; CHECK-NEXT: [[T2:%.*]] = icmp eq <2 x i32> [[T0]], [[T1]]100; CHECK-NEXT: [[T3:%.*]] = zext <2 x i1> [[T2]] to <2 x i32>101; CHECK-NEXT: ret <2 x i32> [[T3]]102;103 %t0 = lshr <2 x i32> %a, <i32 31, i32 31>104 %t1 = lshr <2 x i32> %b, <i32 30, i32 30>105 %t2 = icmp eq <2 x i32> %t0, %t1106 %t3 = zext <2 x i1> %t2 to <2 x i32>107 ret <2 x i32> %t3108}109 110define <2 x i32> @test3vec_non-uniform(<2 x i32> %a, <2 x i32> %b) nounwind readnone {111; CHECK-LABEL: @test3vec_non-uniform(112; CHECK-NEXT: [[T0:%.*]] = lshr <2 x i32> [[A:%.*]], <i32 30, i32 31>113; CHECK-NEXT: [[T1:%.*]] = lshr <2 x i32> [[B:%.*]], <i32 30, i32 31>114; CHECK-NEXT: [[T2:%.*]] = icmp eq <2 x i32> [[T0]], [[T1]]115; CHECK-NEXT: [[T3:%.*]] = zext <2 x i1> [[T2]] to <2 x i32>116; CHECK-NEXT: ret <2 x i32> [[T3]]117;118 %t0 = lshr <2 x i32> %a, <i32 30, i32 31>119 %t1 = lshr <2 x i32> %b, <i32 30, i32 31>120 %t2 = icmp eq <2 x i32> %t0, %t1121 %t3 = zext <2 x i1> %t2 to <2 x i32>122 ret <2 x i32> %t3123}124 125; Variation on @test3: checking the 2nd bit in a situation where the 5th bit126; is one, not zero.127define i32 @test3i(i32 %a, i32 %b) nounwind readnone {128; CHECK-LABEL: @test3i(129; CHECK-NEXT: [[T01:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]130; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T01]], -1131; CHECK-NEXT: [[T5:%.*]] = zext i1 [[T4]] to i32132; CHECK-NEXT: ret i32 [[T5]]133;134 %t0 = lshr i32 %a, 29135 %t1 = lshr i32 %b, 29136 %t2 = or i32 %t0, 35137 %t3 = or i32 %t1, 35138 %t4 = icmp eq i32 %t2, %t3139 %t5 = zext i1 %t4 to i32140 ret i32 %t5141}142 143define i1 @test4a(i32 %a) {144; CHECK-LABEL: @test4a(145; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[A:%.*]], 1146; CHECK-NEXT: ret i1 [[C]]147;148 %l = ashr i32 %a, 31149 %na = sub i32 0, %a150 %r = lshr i32 %na, 31151 %signum = or i32 %l, %r152 %c = icmp slt i32 %signum, 1153 ret i1 %c154}155 156define i1 @test4a_commuted(i32 %a) {157; CHECK-LABEL: @test4a_commuted(158; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[SIGNUM:%.*]], 1159; CHECK-NEXT: ret i1 [[C]]160;161 %l = ashr i32 %a, 31162 %na = sub i32 0, %a163 %r = lshr i32 %na, 31164 %signum = or i32 %r, %l165 %c = icmp slt i32 %signum, 1166 ret i1 %c167}168 169define <2 x i1> @test4a_vec(<2 x i32> %a) {170; CHECK-LABEL: @test4a_vec(171; CHECK-NEXT: [[C:%.*]] = icmp slt <2 x i32> [[A:%.*]], splat (i32 1)172; CHECK-NEXT: ret <2 x i1> [[C]]173;174 %l = ashr <2 x i32> %a, <i32 31, i32 31>175 %na = sub <2 x i32> zeroinitializer, %a176 %r = lshr <2 x i32> %na, <i32 31, i32 31>177 %signum = or <2 x i32> %l, %r178 %c = icmp slt <2 x i32> %signum, <i32 1, i32 1>179 ret <2 x i1> %c180}181 182define i1 @test4b(i64 %a) {183; CHECK-LABEL: @test4b(184; CHECK-NEXT: [[C:%.*]] = icmp slt i64 [[A:%.*]], 1185; CHECK-NEXT: ret i1 [[C]]186;187 %l = ashr i64 %a, 63188 %na = sub i64 0, %a189 %r = lshr i64 %na, 63190 %signum = or i64 %l, %r191 %c = icmp slt i64 %signum, 1192 ret i1 %c193}194 195define i1 @test4c(i64 %a) {196; CHECK-LABEL: @test4c(197; CHECK-NEXT: [[C:%.*]] = icmp slt i64 [[A:%.*]], 1198; CHECK-NEXT: ret i1 [[C]]199;200 %l = ashr i64 %a, 63201 %na = sub i64 0, %a202 %r = lshr i64 %na, 63203 %signum = or i64 %l, %r204 %signum.trunc = trunc i64 %signum to i32205 %c = icmp slt i32 %signum.trunc, 1206 ret i1 %c207}208 209define <2 x i1> @test4c_vec(<2 x i64> %a) {210; CHECK-LABEL: @test4c_vec(211; CHECK-NEXT: [[C:%.*]] = icmp slt <2 x i64> [[A:%.*]], splat (i64 1)212; CHECK-NEXT: ret <2 x i1> [[C]]213;214 %l = ashr <2 x i64> %a, <i64 63, i64 63>215 %na = sub <2 x i64> zeroinitializer, %a216 %r = lshr <2 x i64> %na, <i64 63, i64 63>217 %signum = or <2 x i64> %l, %r218 %signum.trunc = trunc <2 x i64> %signum to <2 x i32>219 %c = icmp slt <2 x i32> %signum.trunc, <i32 1, i32 1>220 ret <2 x i1> %c221}222 223; PR49866224 225define i1 @shift_trunc_signbit_test(i32 %x) {226; CHECK-LABEL: @shift_trunc_signbit_test(227; CHECK-NEXT: [[R:%.*]] = icmp slt i32 [[X:%.*]], 0228; CHECK-NEXT: ret i1 [[R]]229;230 %sh = lshr i32 %x, 24231 %tr = trunc i32 %sh to i8232 %r = icmp slt i8 %tr, 0233 ret i1 %r234}235 236define <2 x i1> @shift_trunc_signbit_test_vec_uses(<2 x i17> %x, ptr %p1, ptr %p2) {237; CHECK-LABEL: @shift_trunc_signbit_test_vec_uses(238; CHECK-NEXT: [[SH:%.*]] = lshr <2 x i17> [[X:%.*]], splat (i17 4)239; CHECK-NEXT: store <2 x i17> [[SH]], ptr [[P1:%.*]], align 8240; CHECK-NEXT: [[TR:%.*]] = trunc nuw <2 x i17> [[SH]] to <2 x i13>241; CHECK-NEXT: store <2 x i13> [[TR]], ptr [[P2:%.*]], align 4242; CHECK-NEXT: [[R:%.*]] = icmp sgt <2 x i17> [[X]], splat (i17 -1)243; CHECK-NEXT: ret <2 x i1> [[R]]244;245 %sh = lshr <2 x i17> %x, <i17 4, i17 4>246 store <2 x i17> %sh, ptr %p1247 %tr = trunc <2 x i17> %sh to <2 x i13>248 store <2 x i13> %tr, ptr %p2249 %r = icmp sgt <2 x i13> %tr, <i13 -1, i13 -1>250 ret <2 x i1> %r251}252 253; negative test - but this reduces with a mask op254 255define i1 @shift_trunc_wrong_shift(i32 %x) {256; CHECK-LABEL: @shift_trunc_wrong_shift(257; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1073741824258; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[TMP1]], 0259; CHECK-NEXT: ret i1 [[R]]260;261 %sh = lshr i32 %x, 23262 %tr = trunc i32 %sh to i8263 %r = icmp slt i8 %tr, 0264 ret i1 %r265}266 267; negative test268 269define i1 @shift_trunc_wrong_cmp(i32 %x) {270; CHECK-LABEL: @shift_trunc_wrong_cmp(271; CHECK-NEXT: [[SH:%.*]] = lshr i32 [[X:%.*]], 24272; CHECK-NEXT: [[TR:%.*]] = trunc nuw i32 [[SH]] to i8273; CHECK-NEXT: [[R:%.*]] = icmp slt i8 [[TR]], 1274; CHECK-NEXT: ret i1 [[R]]275;276 %sh = lshr i32 %x, 24277 %tr = trunc i32 %sh to i8278 %r = icmp slt i8 %tr, 1279 ret i1 %r280}281