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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=instcombine -S < %s | FileCheck %s3 4define i1 @test1(i32 %n, i32 %d) {5; CHECK-LABEL: @test1(6; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 [[D:%.*]], [[N:%.*]]7; CHECK-NEXT: ret i1 [[CMP1]]8;9 %div = udiv i32 %n, %d10 %cmp1 = icmp eq i32 %div, 011 ret i1 %cmp112}13 14define <2 x i1> @test1vec(<2 x i32> %n, <2 x i32> %d) {15; CHECK-LABEL: @test1vec(16; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i32> [[D:%.*]], [[N:%.*]]17; CHECK-NEXT: ret <2 x i1> [[CMP1]]18;19 %div = udiv <2 x i32> %n, %d20 %cmp1 = icmp eq <2 x i32> %div, zeroinitializer21 ret <2 x i1> %cmp122}23 24define i1 @test2(i32 %d) {25; CHECK-LABEL: @test2(26; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 [[D:%.*]], 6427; CHECK-NEXT: ret i1 [[CMP1]]28;29 %div = udiv i32 64, %d30 %cmp1 = icmp eq i32 %div, 031 ret i1 %cmp132}33 34define <2 x i1> @test2vec(<2 x i32> %d) {35; CHECK-LABEL: @test2vec(36; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i32> [[D:%.*]], <i32 64, i32 63>37; CHECK-NEXT: ret <2 x i1> [[CMP1]]38;39 %div = udiv <2 x i32> <i32 64, i32 63>, %d40 %cmp1 = icmp eq <2 x i32> %div, zeroinitializer41 ret <2 x i1> %cmp142}43 44define i1 @test3(i32 %n, i32 %d) {45; CHECK-LABEL: @test3(46; CHECK-NEXT: [[CMP1:%.*]] = icmp ule i32 [[D:%.*]], [[N:%.*]]47; CHECK-NEXT: ret i1 [[CMP1]]48;49 %div = udiv i32 %n, %d50 %cmp1 = icmp ne i32 %div, 051 ret i1 %cmp152}53 54define <2 x i1> @test3vec(<2 x i32> %n, <2 x i32> %d) {55; CHECK-LABEL: @test3vec(56; CHECK-NEXT: [[CMP1:%.*]] = icmp ule <2 x i32> [[D:%.*]], [[N:%.*]]57; CHECK-NEXT: ret <2 x i1> [[CMP1]]58;59 %div = udiv <2 x i32> %n, %d60 %cmp1 = icmp ne <2 x i32> %div, zeroinitializer61 ret <2 x i1> %cmp162}63 64define i1 @test4(i32 %d) {65; CHECK-LABEL: @test4(66; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[D:%.*]], 6567; CHECK-NEXT: ret i1 [[CMP1]]68;69 %div = udiv i32 64, %d70 %cmp1 = icmp ne i32 %div, 071 ret i1 %cmp172}73 74define <2 x i1> @test4vec(<2 x i32> %d) {75; CHECK-LABEL: @test4vec(76; CHECK-NEXT: [[CMP1:%.*]] = icmp ult <2 x i32> [[D:%.*]], <i32 65, i32 66>77; CHECK-NEXT: ret <2 x i1> [[CMP1]]78;79 %div = udiv <2 x i32> <i32 64, i32 65>, %d80 %cmp1 = icmp ne <2 x i32> %div, zeroinitializer81 ret <2 x i1> %cmp182}83 84define i1 @test5(i32 %d) {85; CHECK-LABEL: @test5(86; CHECK-NEXT: ret i1 true87;88 %div = udiv i32 -1, %d89 %cmp1 = icmp ne i32 %div, 090 ret i1 %cmp191}92 93define <2 x i1> @test5vec(<2 x i32> %d) {94; CHECK-LABEL: @test5vec(95; CHECK-NEXT: ret <2 x i1> splat (i1 true)96;97 %div = udiv <2 x i32> <i32 -1, i32 -1>, %d98 %cmp1 = icmp ne <2 x i32> %div, zeroinitializer99 ret <2 x i1> %cmp1100}101 102define i1 @test6(i32 %d) {103; CHECK-LABEL: @test6(104; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[D:%.*]], 6105; CHECK-NEXT: ret i1 [[CMP1]]106;107 %div = udiv i32 5, %d108 %cmp1 = icmp ugt i32 %div, 0109 ret i1 %cmp1110}111 112define <2 x i1> @test6vec(<2 x i32> %d) {113; CHECK-LABEL: @test6vec(114; CHECK-NEXT: [[CMP1:%.*]] = icmp ult <2 x i32> [[D:%.*]], splat (i32 6)115; CHECK-NEXT: ret <2 x i1> [[CMP1]]116;117 %div = udiv <2 x i32> <i32 5, i32 5>, %d118 %cmp1 = icmp ugt <2 x i32> %div, zeroinitializer119 ret <2 x i1> %cmp1120}121 122; (icmp ugt (udiv C1, X), C1) -> false.123define i1 @test7(i32 %d) {124; CHECK-LABEL: @test7(125; CHECK-NEXT: ret i1 false126;127 %div = udiv i32 8, %d128 %cmp1 = icmp ugt i32 %div, 8129 ret i1 %cmp1130}131 132define <2 x i1> @test7vec(<2 x i32> %d) {133; CHECK-LABEL: @test7vec(134; CHECK-NEXT: ret <2 x i1> zeroinitializer135;136 %div = udiv <2 x i32> <i32 8, i32 8>, %d137 %cmp1 = icmp ugt <2 x i32> %div, <i32 8, i32 8>138 ret <2 x i1> %cmp1139}140 141define i1 @test8(i32 %d) {142; CHECK-LABEL: @test8(143; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[D:%.*]], 2144; CHECK-NEXT: ret i1 [[CMP1]]145;146 %div = udiv i32 4, %d147 %cmp1 = icmp ugt i32 %div, 3148 ret i1 %cmp1149}150 151define <2 x i1> @test8vec(<2 x i32> %d) {152; CHECK-LABEL: @test8vec(153; CHECK-NEXT: [[CMP1:%.*]] = icmp ult <2 x i32> [[D:%.*]], splat (i32 2)154; CHECK-NEXT: ret <2 x i1> [[CMP1]]155;156 %div = udiv <2 x i32> <i32 4, i32 4>, %d157 %cmp1 = icmp ugt <2 x i32> %div, <i32 3, i32 3>158 ret <2 x i1> %cmp1159}160 161define i1 @test9(i32 %d) {162; CHECK-LABEL: @test9(163; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[D:%.*]], 2164; CHECK-NEXT: ret i1 [[CMP1]]165;166 %div = udiv i32 4, %d167 %cmp1 = icmp ugt i32 %div, 2168 ret i1 %cmp1169}170 171define <2 x i1> @test9vec(<2 x i32> %d) {172; CHECK-LABEL: @test9vec(173; CHECK-NEXT: [[CMP1:%.*]] = icmp ult <2 x i32> [[D:%.*]], splat (i32 2)174; CHECK-NEXT: ret <2 x i1> [[CMP1]]175;176 %div = udiv <2 x i32> <i32 4, i32 4>, %d177 %cmp1 = icmp ugt <2 x i32> %div, <i32 2, i32 2>178 ret <2 x i1> %cmp1179}180 181define i1 @test10(i32 %d) {182; CHECK-LABEL: @test10(183; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[D:%.*]], 3184; CHECK-NEXT: ret i1 [[CMP1]]185;186 %div = udiv i32 4, %d187 %cmp1 = icmp ugt i32 %div, 1188 ret i1 %cmp1189}190 191define <2 x i1> @test10vec(<2 x i32> %d) {192; CHECK-LABEL: @test10vec(193; CHECK-NEXT: [[CMP1:%.*]] = icmp ult <2 x i32> [[D:%.*]], splat (i32 3)194; CHECK-NEXT: ret <2 x i1> [[CMP1]]195;196 %div = udiv <2 x i32> <i32 4, i32 4>, %d197 %cmp1 = icmp ugt <2 x i32> %div, <i32 1, i32 1>198 ret <2 x i1> %cmp1199}200 201define i1 @test11(i32 %d) {202; CHECK-LABEL: @test11(203; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 [[D:%.*]], 4204; CHECK-NEXT: ret i1 [[CMP1]]205;206 %div = udiv i32 4, %d207 %cmp1 = icmp ult i32 %div, 1208 ret i1 %cmp1209}210 211define <2 x i1> @test11vec(<2 x i32> %d) {212; CHECK-LABEL: @test11vec(213; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i32> [[D:%.*]], splat (i32 4)214; CHECK-NEXT: ret <2 x i1> [[CMP1]]215;216 %div = udiv <2 x i32> <i32 4, i32 4>, %d217 %cmp1 = icmp ult <2 x i32> %div, <i32 1, i32 1>218 ret <2 x i1> %cmp1219}220 221define i1 @test12(i32 %d) {222; CHECK-LABEL: @test12(223; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 [[D:%.*]], 2224; CHECK-NEXT: ret i1 [[CMP1]]225;226 %div = udiv i32 4, %d227 %cmp1 = icmp ult i32 %div, 2228 ret i1 %cmp1229}230 231define <2 x i1> @test12vec(<2 x i32> %d) {232; CHECK-LABEL: @test12vec(233; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i32> [[D:%.*]], splat (i32 2)234; CHECK-NEXT: ret <2 x i1> [[CMP1]]235;236 %div = udiv <2 x i32> <i32 4, i32 4>, %d237 %cmp1 = icmp ult <2 x i32> %div, <i32 2, i32 2>238 ret <2 x i1> %cmp1239}240 241define i1 @test13(i32 %d) {242; CHECK-LABEL: @test13(243; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 [[D:%.*]], 1244; CHECK-NEXT: ret i1 [[CMP1]]245;246 %div = udiv i32 4, %d247 %cmp1 = icmp ult i32 %div, 3248 ret i1 %cmp1249}250 251define <2 x i1> @test13vec(<2 x i32> %d) {252; CHECK-LABEL: @test13vec(253; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i32> [[D:%.*]], splat (i32 1)254; CHECK-NEXT: ret <2 x i1> [[CMP1]]255;256 %div = udiv <2 x i32> <i32 4, i32 4>, %d257 %cmp1 = icmp ult <2 x i32> %div, <i32 3, i32 3>258 ret <2 x i1> %cmp1259}260 261define i1 @test14(i32 %d) {262; CHECK-LABEL: @test14(263; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 [[D:%.*]], 1264; CHECK-NEXT: ret i1 [[CMP1]]265;266 %div = udiv i32 4, %d267 %cmp1 = icmp ult i32 %div, 4268 ret i1 %cmp1269}270 271define <2 x i1> @test14vec(<2 x i32> %d) {272; CHECK-LABEL: @test14vec(273; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i32> [[D:%.*]], splat (i32 1)274; CHECK-NEXT: ret <2 x i1> [[CMP1]]275;276 %div = udiv <2 x i32> <i32 4, i32 4>, %d277 %cmp1 = icmp ult <2 x i32> %div, <i32 4, i32 4>278 ret <2 x i1> %cmp1279}280 281; icmp ugt X, UINT_MAX -> false.282define i1 @test15(i32 %d) {283; CHECK-LABEL: @test15(284; CHECK-NEXT: ret i1 false285;286 %div = udiv i32 4, %d287 %cmp1 = icmp ugt i32 %div, -1288 ret i1 %cmp1289}290 291define <2 x i1> @test15vec(<2 x i32> %d) {292; CHECK-LABEL: @test15vec(293; CHECK-NEXT: ret <2 x i1> zeroinitializer294;295 %div = udiv <2 x i32> <i32 4, i32 4>, %d296 %cmp1 = icmp ugt <2 x i32> %div, <i32 -1, i32 -1>297 ret <2 x i1> %cmp1298}299 300; icmp ult X, UINT_MAX -> true.301define i1 @test16(i32 %d) {302; CHECK-LABEL: @test16(303; CHECK-NEXT: ret i1 true304;305 %div = udiv i32 4, %d306 %cmp1 = icmp ult i32 %div, -1307 ret i1 %cmp1308}309 310define <2 x i1> @test16vec(<2 x i32> %d) {311; CHECK-LABEL: @test16vec(312; CHECK-NEXT: ret <2 x i1> splat (i1 true)313;314 %div = udiv <2 x i32> <i32 4, i32 4>, %d315 %cmp1 = icmp ult <2 x i32> %div, <i32 -1, i32 -1>316 ret <2 x i1> %cmp1317}318 319