62 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -passes=instcombine -S < %s | FileCheck %s3 4; Case 1: Vector to Vector bitcast5define <4 x i2> @test_vector_to_vector(<1 x i8> %a0, <1 x i8> %a1) {6; CHECK-LABEL: define <4 x i2> @test_vector_to_vector(7; CHECK-SAME: <1 x i8> [[A0:%.*]], <1 x i8> [[A1:%.*]]) {8; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <1 x i8> [[A0]], [[A1]]9; CHECK-NEXT: [[EXT:%.*]] = sext <1 x i1> [[CMP]] to <1 x i8>10; CHECK-NEXT: [[SUB:%.*]] = bitcast <1 x i8> [[EXT]] to <4 x i2>11; CHECK-NEXT: ret <4 x i2> [[SUB]]12;13 %cmp = icmp sgt <1 x i8> %a0, %a114 %ext = sext <1 x i1> %cmp to <1 x i8>15 %sub = bitcast <1 x i8> %ext to <4 x i2>16 %sra = ashr <4 x i2> %sub, <i2 1, i2 1, i2 1, i2 1>17 ret <4 x i2> %sra18}19 20; Case 2: Scalar to Vector bitcast21define <2 x i16> @test_scalar_to_vector(i1 %cond) {22; CHECK-LABEL: define <2 x i16> @test_scalar_to_vector(23; CHECK-SAME: i1 [[COND:%.*]]) {24; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[COND]] to i3225; CHECK-NEXT: [[BC:%.*]] = bitcast i32 [[EXT]] to <2 x i16>26; CHECK-NEXT: ret <2 x i16> [[BC]]27;28 %ext = sext i1 %cond to i3229 %bc = bitcast i32 %ext to <2 x i16>30 %sra = ashr <2 x i16> %bc, <i16 8, i16 8>31 ret <2 x i16> %sra32}33 34 35; Case 3: Multiple right shifts36define <8 x i8> @test_multiple_shifts(i1 %cond) {37; CHECK-LABEL: define <8 x i8> @test_multiple_shifts(38; CHECK-SAME: i1 [[COND:%.*]]) {39; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[COND]] to i6440; CHECK-NEXT: [[BC:%.*]] = bitcast i64 [[EXT]] to <8 x i8>41; CHECK-NEXT: ret <8 x i8> [[BC]]42;43 %ext = sext i1 %cond to i6444 %bc = bitcast i64 %ext to <8 x i8>45 %sra1 = ashr <8 x i8> %bc, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 1>46 %sra2 = ashr <8 x i8> %sra1, <i8 2, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>47 ret <8 x i8> %sra248}49 50; (Negative) Case 4: Test with non-sign-extended source51define <4 x i8> @test_non_sign_extended(i32 %val) {52; CHECK-LABEL: define <4 x i8> @test_non_sign_extended(53; CHECK-SAME: i32 [[VAL:%.*]]) {54; CHECK-NEXT: [[BC:%.*]] = bitcast i32 [[VAL]] to <4 x i8>55; CHECK-NEXT: [[SRA:%.*]] = ashr <4 x i8> [[BC]], splat (i8 1)56; CHECK-NEXT: ret <4 x i8> [[SRA]]57;58 %bc = bitcast i32 %val to <4 x i8>59 %sra = ashr <4 x i8> %bc, <i8 1, i8 1, i8 1, i8 1>60 ret <4 x i8> %sra61}62