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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt %s -passes=instcombine -S | FileCheck %s3 4declare { i4, i1 } @llvm.smul.with.overflow.i4(i4, i4) #15 6define i1 @t0_umul(i4 %size, i4 %nmemb) {7; CHECK-LABEL: @t0_umul(8; CHECK-NEXT: [[NMEMB_FR:%.*]] = freeze i4 [[NMEMB:%.*]]9; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE:%.*]], i4 [[NMEMB_FR]])10; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 111; CHECK-NEXT: [[PHITMP:%.*]] = xor i1 [[SMUL_OV]], true12; CHECK-NEXT: ret i1 [[PHITMP]]13;14 %cmp = icmp eq i4 %size, 015 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)16 %smul.ov = extractvalue { i4, i1 } %smul, 117 %phitmp = xor i1 %smul.ov, true18 %or = select i1 %cmp, i1 true, i1 %phitmp19 ret i1 %or20}21 22define i1 @t1_commutative(i4 %size, i4 %nmemb) {23; CHECK-LABEL: @t1_commutative(24; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE:%.*]], i4 [[NMEMB:%.*]])25; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 126; CHECK-NEXT: [[PHITMP:%.*]] = xor i1 [[SMUL_OV]], true27; CHECK-NEXT: ret i1 [[PHITMP]]28;29 %cmp = icmp eq i4 %size, 030 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)31 %smul.ov = extractvalue { i4, i1 } %smul, 132 %phitmp = xor i1 %smul.ov, true33 %or = select i1 %phitmp, i1 true, i1 %cmp ; swapped34 ret i1 %or35}36 37define i1 @n2_wrong_size(i4 %size0, i4 %size1, i4 %nmemb) {38; CHECK-LABEL: @n2_wrong_size(39; CHECK-NEXT: [[CMP:%.*]] = icmp eq i4 [[SIZE1:%.*]], 040; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE0:%.*]], i4 [[NMEMB:%.*]])41; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 142; CHECK-NEXT: [[PHITMP:%.*]] = xor i1 [[SMUL_OV]], true43; CHECK-NEXT: [[OR:%.*]] = select i1 [[CMP]], i1 true, i1 [[PHITMP]]44; CHECK-NEXT: ret i1 [[OR]]45;46 %cmp = icmp eq i4 %size1, 0 ; not %size047 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size0, i4 %nmemb)48 %smul.ov = extractvalue { i4, i1 } %smul, 149 %phitmp = xor i1 %smul.ov, true50 %or = select i1 %cmp, i1 true, i1 %phitmp51 ret i1 %or52}53 54define i1 @n3_wrong_pred(i4 %size, i4 %nmemb) {55; CHECK-LABEL: @n3_wrong_pred(56; CHECK-NEXT: ret i1 true57;58 %cmp = icmp ne i4 %size, 0 ; not 'eq'59 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)60 %smul.ov = extractvalue { i4, i1 } %smul, 161 %phitmp = xor i1 %smul.ov, true62 %or = select i1 %cmp, i1 true, i1 %phitmp63 ret i1 %or64}65 66define i1 @n4_not_and(i4 %size, i4 %nmemb) {67; CHECK-LABEL: @n4_not_and(68; CHECK-NEXT: [[CMP:%.*]] = icmp eq i4 [[SIZE:%.*]], 069; CHECK-NEXT: ret i1 [[CMP]]70;71 %cmp = icmp eq i4 %size, 072 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)73 %smul.ov = extractvalue { i4, i1 } %smul, 174 %phitmp = xor i1 %smul.ov, true75 %or = select i1 %cmp, i1 %phitmp, i1 false ; not 'or'76 ret i1 %or77}78 79define i1 @n5_not_zero(i4 %size, i4 %nmemb) {80; CHECK-LABEL: @n5_not_zero(81; CHECK-NEXT: [[CMP:%.*]] = icmp eq i4 [[SIZE:%.*]], 182; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])83; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 184; CHECK-NEXT: [[PHITMP:%.*]] = xor i1 [[SMUL_OV]], true85; CHECK-NEXT: [[OR:%.*]] = select i1 [[CMP]], i1 true, i1 [[PHITMP]]86; CHECK-NEXT: ret i1 [[OR]]87;88 %cmp = icmp eq i4 %size, 1 ; should be '0'89 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)90 %smul.ov = extractvalue { i4, i1 } %smul, 191 %phitmp = xor i1 %smul.ov, true92 %or = select i1 %cmp, i1 true, i1 %phitmp93 ret i1 %or94}95