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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt %s -passes=instcombine -S | FileCheck %s3 4declare { i4, i1 } @llvm.smul.with.overflow.i4(i4, i4) #15 6define i1 @t0_smul(i4 %size, i4 %nmemb) {7; CHECK-LABEL: @t0_smul(8; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE:%.*]], i4 [[NMEMB:%.*]])9; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 110; CHECK-NEXT: ret i1 [[SMUL_OV]]11;12 %cmp = icmp ne i4 %size, 013 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)14 %smul.ov = extractvalue { i4, i1 } %smul, 115 %and = select i1 %smul.ov, i1 %cmp, i1 false16 ret i1 %and17}18 19define i1 @t1_commutative(i4 %size, i4 %nmemb) {20; CHECK-LABEL: @t1_commutative(21; CHECK-NEXT: [[NMEMB_FR:%.*]] = freeze i4 [[NMEMB:%.*]]22; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE:%.*]], i4 [[NMEMB_FR]])23; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 124; CHECK-NEXT: ret i1 [[SMUL_OV]]25;26 %cmp = icmp ne i4 %size, 027 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)28 %smul.ov = extractvalue { i4, i1 } %smul, 129 %and = select i1 %cmp, i1 %smul.ov, i1 false ; swapped30 ret i1 %and31}32 33define i1 @n2_wrong_size(i4 %size0, i4 %size1, i4 %nmemb) {34; CHECK-LABEL: @n2_wrong_size(35; CHECK-NEXT: [[CMP:%.*]] = icmp ne i4 [[SIZE1:%.*]], 036; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE0:%.*]], i4 [[NMEMB:%.*]])37; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 138; CHECK-NEXT: [[AND:%.*]] = select i1 [[SMUL_OV]], i1 [[CMP]], i1 false39; CHECK-NEXT: ret i1 [[AND]]40;41 %cmp = icmp ne i4 %size1, 0 ; not %size042 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size0, i4 %nmemb)43 %smul.ov = extractvalue { i4, i1 } %smul, 144 %and = select i1 %smul.ov, i1 %cmp, i1 false45 ret i1 %and46}47 48define i1 @n3_wrong_pred(i4 %size, i4 %nmemb) {49; CHECK-LABEL: @n3_wrong_pred(50; CHECK-NEXT: ret i1 false51;52 %cmp = icmp eq i4 %size, 0 ; not 'ne'53 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)54 %smul.ov = extractvalue { i4, i1 } %smul, 155 %and = select i1 %smul.ov, i1 %cmp, i1 false56 ret i1 %and57}58 59define i1 @n4_not_and(i4 %size, i4 %nmemb) {60; CHECK-LABEL: @n4_not_and(61; CHECK-NEXT: [[CMP:%.*]] = icmp ne i4 [[SIZE:%.*]], 062; CHECK-NEXT: ret i1 [[CMP]]63;64 %cmp = icmp ne i4 %size, 065 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)66 %smul.ov = extractvalue { i4, i1 } %smul, 167 %and = select i1 %smul.ov, i1 true, i1 %cmp ; not 'and'68 ret i1 %and69}70 71define i1 @n5_not_zero(i4 %size, i4 %nmemb) {72; CHECK-LABEL: @n5_not_zero(73; CHECK-NEXT: [[CMP:%.*]] = icmp ne i4 [[SIZE:%.*]], 174; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])75; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 176; CHECK-NEXT: [[AND:%.*]] = and i1 [[SMUL_OV]], [[CMP]]77; CHECK-NEXT: ret i1 [[AND]]78;79 %cmp = icmp ne i4 %size, 1 ; should be '0'80 %smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)81 %smul.ov = extractvalue { i4, i1 } %smul, 182 %and = select i1 %smul.ov, i1 %cmp, i1 false83 ret i1 %and84}85