100 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=instcombine -S | FileCheck %s3 4;------------------------------------------------------------------------------;5; Scalar tests6;------------------------------------------------------------------------------;7 8define i1 @umin_scalar(i1 %0, i1 %1) {9; CHECK-LABEL: define i1 @umin_scalar10; CHECK-SAME: (i1 [[TMP0:%.*]], i1 [[TMP1:%.*]]) {11; CHECK-NEXT: [[TMP3:%.*]] = and i1 [[TMP0]], [[TMP1]]12; CHECK-NEXT: ret i1 [[TMP3]]13;14 %3 = call i1 @llvm.umin.i1(i1 %0, i1 %1)15 ret i1 %316}17 18define i1 @smin_scalar(i1 %0, i1 %1) {19; CHECK-LABEL: define i1 @smin_scalar20; CHECK-SAME: (i1 [[TMP0:%.*]], i1 [[TMP1:%.*]]) {21; CHECK-NEXT: [[TMP3:%.*]] = or i1 [[TMP0]], [[TMP1]]22; CHECK-NEXT: ret i1 [[TMP3]]23;24 %3 = call i1 @llvm.smin.i1(i1 %0, i1 %1)25 ret i1 %326}27 28define i1 @umax_scalar(i1 %0, i1 %1) {29; CHECK-LABEL: define i1 @umax_scalar30; CHECK-SAME: (i1 [[TMP0:%.*]], i1 [[TMP1:%.*]]) {31; CHECK-NEXT: [[TMP3:%.*]] = or i1 [[TMP0]], [[TMP1]]32; CHECK-NEXT: ret i1 [[TMP3]]33;34 %3 = call i1 @llvm.umax.i1(i1 %0, i1 %1)35 ret i1 %336}37 38define i1 @smax_scalar(i1 %0, i1 %1) {39; CHECK-LABEL: define i1 @smax_scalar40; CHECK-SAME: (i1 [[TMP0:%.*]], i1 [[TMP1:%.*]]) {41; CHECK-NEXT: [[TMP3:%.*]] = and i1 [[TMP0]], [[TMP1]]42; CHECK-NEXT: ret i1 [[TMP3]]43;44 %3 = call i1 @llvm.smax.i1(i1 %0, i1 %1)45 ret i1 %346}47 48;------------------------------------------------------------------------------;49; Vector tests50;------------------------------------------------------------------------------;51 52define <4 x i1> @umin_vector(<4 x i1> %0, <4 x i1> %1) {53; CHECK-LABEL: define <4 x i1> @umin_vector54; CHECK-SAME: (<4 x i1> [[TMP0:%.*]], <4 x i1> [[TMP1:%.*]]) {55; CHECK-NEXT: [[TMP3:%.*]] = and <4 x i1> [[TMP0]], [[TMP1]]56; CHECK-NEXT: ret <4 x i1> [[TMP3]]57;58 %3 = call <4 x i1> @llvm.umin.v4i1(<4 x i1> %0, <4 x i1> %1)59 ret <4 x i1> %360}61 62define <4 x i1> @smin_vector(<4 x i1> %0, <4 x i1> %1) {63; CHECK-LABEL: define <4 x i1> @smin_vector64; CHECK-SAME: (<4 x i1> [[TMP0:%.*]], <4 x i1> [[TMP1:%.*]]) {65; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i1> [[TMP0]], [[TMP1]]66; CHECK-NEXT: ret <4 x i1> [[TMP3]]67;68 %3 = call <4 x i1> @llvm.smin.v4i1(<4 x i1> %0, <4 x i1> %1)69 ret <4 x i1> %370}71 72define <4 x i1> @umax_vector(<4 x i1> %0, <4 x i1> %1) {73; CHECK-LABEL: define <4 x i1> @umax_vector74; CHECK-SAME: (<4 x i1> [[TMP0:%.*]], <4 x i1> [[TMP1:%.*]]) {75; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i1> [[TMP0]], [[TMP1]]76; CHECK-NEXT: ret <4 x i1> [[TMP3]]77;78 %3 = call <4 x i1> @llvm.umax.v4i1(<4 x i1> %0, <4 x i1> %1)79 ret <4 x i1> %380}81 82define <4 x i1> @smax_vector(<4 x i1> %0, <4 x i1> %1) {83; CHECK-LABEL: define <4 x i1> @smax_vector84; CHECK-SAME: (<4 x i1> [[TMP0:%.*]], <4 x i1> [[TMP1:%.*]]) {85; CHECK-NEXT: [[TMP3:%.*]] = and <4 x i1> [[TMP0]], [[TMP1]]86; CHECK-NEXT: ret <4 x i1> [[TMP3]]87;88 %3 = call <4 x i1> @llvm.smax.v4i1(<4 x i1> %0, <4 x i1> %1)89 ret <4 x i1> %390}91 92declare i1 @llvm.umin.i1(i1, i1)93declare i1 @llvm.smin.i1(i1, i1)94declare i1 @llvm.umax.i1(i1, i1)95declare i1 @llvm.smax.i1(i1, i1)96declare <4 x i1> @llvm.umin.v4i1(<4 x i1>, <4 x i1>)97declare <4 x i1> @llvm.smin.v4i1(<4 x i1>, <4 x i1>)98declare <4 x i1> @llvm.umax.v4i1(<4 x i1>, <4 x i1>)99declare <4 x i1> @llvm.smax.v4i1(<4 x i1>, <4 x i1>)100