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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 62; RUN: opt -passes=instcombine %s -S | FileCheck %s3 4declare void @clobber.i32(i32)5 6define i16 @selective_shift_16(i32 %mask, i16 %upper, i16 %lower) {7; CHECK-LABEL: define i16 @selective_shift_16(8; CHECK-SAME: i32 [[MASK:%.*]], i16 [[UPPER:%.*]], i16 [[LOWER:%.*]]) {9; CHECK-NEXT: [[MASK_BIT:%.*]] = and i32 [[MASK]], 1610; CHECK-NEXT: [[MASK_BIT_Z:%.*]] = icmp eq i32 [[MASK_BIT]], 011; CHECK-NEXT: [[SEL_V:%.*]] = select i1 [[MASK_BIT_Z]], i16 [[LOWER]], i16 [[UPPER]]12; CHECK-NEXT: ret i16 [[SEL_V]]13;14 %upper.zext = zext i16 %upper to i3215 %upper.shl = shl nuw i32 %upper.zext, 1616 %lower.zext = zext i16 %lower to i3217 %pack = or disjoint i32 %upper.shl, %lower.zext18 %mask.bit = and i32 %mask, 1619 %sel = lshr i32 %pack, %mask.bit20 %trunc = trunc i32 %sel to i1621 ret i16 %trunc22}23 24; Will assert if InsertPoint is not set before creating an instruction25; with IRBuilder26define i16 @selective_shift_16_insertpt(i32 %mask, i16 %upper, i16 %lower) {27; CHECK-LABEL: define i16 @selective_shift_16_insertpt(28; CHECK-SAME: i32 [[MASK:%.*]], i16 [[UPPER:%.*]], i16 [[LOWER:%.*]]) {29; CHECK-NEXT: [[MASK_BIT:%.*]] = and i32 [[MASK]], 1630; CHECK-NEXT: [[MASK_BIT_Z:%.*]] = icmp eq i32 [[MASK_BIT]], 031; CHECK-NEXT: [[SEL_V:%.*]] = select i1 [[MASK_BIT_Z]], i16 [[LOWER]], i16 [[UPPER]]32; CHECK-NEXT: [[ADD_ONE:%.*]] = add i16 [[SEL_V]], 133; CHECK-NEXT: ret i16 [[ADD_ONE]]34;35 %mask.bit = and i32 %mask, 1636 %upper.zext = zext i16 %upper to i3237 %upper.shl = shl nuw i32 %upper.zext, 1638 %lower.zext = zext i16 %lower to i3239 %pack = or disjoint i32 %upper.shl, %lower.zext40 %sel = lshr i32 %pack, %mask.bit41 %add.one = add i32 %sel, 142 %trunc = trunc i32 %add.one to i1643 ret i16 %trunc44}45 46define i16 @selective_shift_16.commute(i32 %mask, i16 %upper, i16 %lower) {47; CHECK-LABEL: define i16 @selective_shift_16.commute(48; CHECK-SAME: i32 [[MASK:%.*]], i16 [[UPPER:%.*]], i16 [[LOWER:%.*]]) {49; CHECK-NEXT: [[MASK_BIT:%.*]] = and i32 [[MASK]], 1650; CHECK-NEXT: [[MASK_BIT_Z:%.*]] = icmp eq i32 [[MASK_BIT]], 051; CHECK-NEXT: [[SEL_V:%.*]] = select i1 [[MASK_BIT_Z]], i16 [[LOWER]], i16 [[UPPER]]52; CHECK-NEXT: ret i16 [[SEL_V]]53;54 %upper.zext = zext i16 %upper to i3255 %upper.shl = shl nuw i32 %upper.zext, 1656 %lower.zext = zext i16 %lower to i3257 %pack = or disjoint i32 %lower.zext, %upper.shl58 %mask.bit = and i32 %mask, 1659 %sel = lshr i32 %pack, %mask.bit60 %trunc = trunc i32 %sel to i1661 ret i16 %trunc62}63 64define i16 @selective_shift_16.range(i32 %mask, i32 %upper, i32 range(i32 0, 65536) %lower) {65; CHECK-LABEL: define i16 @selective_shift_16.range(66; CHECK-SAME: i32 [[MASK:%.*]], i32 [[UPPER:%.*]], i32 range(i32 0, 65536) [[LOWER:%.*]]) {67; CHECK-NEXT: [[MASK_BIT:%.*]] = and i32 [[MASK]], 1668; CHECK-NEXT: [[MASK_BIT_Z:%.*]] = icmp eq i32 [[MASK_BIT]], 069; CHECK-NEXT: [[SEL:%.*]] = select i1 [[MASK_BIT_Z]], i32 [[LOWER]], i32 [[UPPER]]70; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SEL]] to i1671; CHECK-NEXT: ret i16 [[TRUNC]]72;73 %upper.shl = shl nuw i32 %upper, 1674 %pack = or disjoint i32 %upper.shl, %lower75 %mask.bit = and i32 %mask, 1676 %sel = lshr i32 %pack, %mask.bit77 %trunc = trunc i32 %sel to i1678 ret i16 %trunc79}80 81define i16 @selective_shift_16.range.commute(i32 %mask, i32 %upper, i32 range(i32 0, 65536) %lower) {82; CHECK-LABEL: define i16 @selective_shift_16.range.commute(83; CHECK-SAME: i32 [[MASK:%.*]], i32 [[UPPER:%.*]], i32 range(i32 0, 65536) [[LOWER:%.*]]) {84; CHECK-NEXT: [[MASK_BIT:%.*]] = and i32 [[MASK]], 1685; CHECK-NEXT: [[MASK_BIT_Z:%.*]] = icmp eq i32 [[MASK_BIT]], 086; CHECK-NEXT: [[SEL:%.*]] = select i1 [[MASK_BIT_Z]], i32 [[LOWER]], i32 [[UPPER]]87; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SEL]] to i1688; CHECK-NEXT: ret i16 [[TRUNC]]89;90 %upper.shl = shl nuw i32 %upper, 1691 %pack = or disjoint i32 %lower, %upper.shl92 %mask.bit = and i32 %mask, 1693 %sel = lshr i32 %pack, %mask.bit94 %trunc = trunc i32 %sel to i1695 ret i16 %trunc96}97 98define i32 @selective_shift_16.masked(i32 %mask, i16 %upper, i16 %lower) {99; CHECK-LABEL: define i32 @selective_shift_16.masked(100; CHECK-SAME: i32 [[MASK:%.*]], i16 [[UPPER:%.*]], i16 [[LOWER:%.*]]) {101; CHECK-NEXT: [[MASK_BIT:%.*]] = and i32 [[MASK]], 16102; CHECK-NEXT: [[MASK_BIT_Z:%.*]] = icmp eq i32 [[MASK_BIT]], 0103; CHECK-NEXT: [[SEL_V:%.*]] = select i1 [[MASK_BIT_Z]], i16 [[LOWER]], i16 [[UPPER]]104; CHECK-NEXT: [[SEL:%.*]] = zext i16 [[SEL_V]] to i32105; CHECK-NEXT: ret i32 [[SEL]]106;107 %upper.zext = zext i16 %upper to i32108 %upper.shl = shl nuw i32 %upper.zext, 16109 %lower.zext = zext i16 %lower to i32110 %pack = or disjoint i32 %lower.zext, %upper.shl111 %mask.bit = and i32 %mask, 16112 %sel = lshr i32 %pack, %mask.bit113 %sel.masked = and i32 %sel, 65535114 ret i32 %sel.masked115}116 117define i32 @selective_shift_16.masked.commute(i32 %mask, i16 %upper, i16 %lower) {118; CHECK-LABEL: define i32 @selective_shift_16.masked.commute(119; CHECK-SAME: i32 [[MASK:%.*]], i16 [[UPPER:%.*]], i16 [[LOWER:%.*]]) {120; CHECK-NEXT: [[MASK_BIT:%.*]] = and i32 [[MASK]], 16121; CHECK-NEXT: [[MASK_BIT_Z:%.*]] = icmp eq i32 [[MASK_BIT]], 0122; CHECK-NEXT: [[SEL_V:%.*]] = select i1 [[MASK_BIT_Z]], i16 [[LOWER]], i16 [[UPPER]]123; CHECK-NEXT: [[SEL:%.*]] = zext i16 [[SEL_V]] to i32124; CHECK-NEXT: ret i32 [[SEL]]125;126 %upper.zext = zext i16 %upper to i32127 %upper.shl = shl nuw i32 %upper.zext, 16128 %lower.zext = zext i16 %lower to i32129 %pack = or disjoint i32 %upper.shl, %lower.zext130 %mask.bit = and i32 %mask, 16131 %sel = lshr i32 %pack, %mask.bit132 %sel.masked = and i32 %sel, 65535133 ret i32 %sel.masked134}135 136define <2 x i16> @selective_shift.v16(<2 x i32> %mask, <2 x i16> %upper, <2 x i16> %lower) {137; CHECK-LABEL: define <2 x i16> @selective_shift.v16(138; CHECK-SAME: <2 x i32> [[MASK:%.*]], <2 x i16> [[UPPER:%.*]], <2 x i16> [[LOWER:%.*]]) {139; CHECK-NEXT: [[MASK_BIT:%.*]] = and <2 x i32> [[MASK]], splat (i32 16)140; CHECK-NEXT: [[MASK_BIT_Z:%.*]] = icmp eq <2 x i32> [[MASK_BIT]], zeroinitializer141; CHECK-NEXT: [[SEL_V:%.*]] = select <2 x i1> [[MASK_BIT_Z]], <2 x i16> [[LOWER]], <2 x i16> [[UPPER]]142; CHECK-NEXT: ret <2 x i16> [[SEL_V]]143;144 %upper.zext = zext <2 x i16> %upper to <2 x i32>145 %upper.shl = shl nuw <2 x i32> %upper.zext, splat(i32 16)146 %lower.zext = zext <2 x i16> %lower to <2 x i32>147 %pack = or disjoint <2 x i32> %upper.shl, %lower.zext148 %mask.bit = and <2 x i32> %mask, splat(i32 16)149 %sel = lshr <2 x i32> %pack, %mask.bit150 %trunc = trunc <2 x i32> %sel to <2 x i16>151 ret <2 x i16> %trunc152}153 154define i16 @selective_shift_16.wide(i64 %mask, i16 %upper, i16 %lower) {155; CHECK-LABEL: define i16 @selective_shift_16.wide(156; CHECK-SAME: i64 [[MASK:%.*]], i16 [[UPPER:%.*]], i16 [[LOWER:%.*]]) {157; CHECK-NEXT: [[MASK_BIT:%.*]] = and i64 [[MASK]], 16158; CHECK-NEXT: [[MASK_BIT_Z:%.*]] = icmp eq i64 [[MASK_BIT]], 0159; CHECK-NEXT: [[SEL_V:%.*]] = select i1 [[MASK_BIT_Z]], i16 [[LOWER]], i16 [[UPPER]]160; CHECK-NEXT: ret i16 [[SEL_V]]161;162 %upper.zext = zext i16 %upper to i64163 %upper.shl = shl nuw i64 %upper.zext, 16164 %lower.zext = zext i16 %lower to i64165 %pack = or disjoint i64 %upper.shl, %lower.zext166 %mask.bit = and i64 %mask, 16167 %sel = lshr i64 %pack, %mask.bit168 %trunc = trunc i64 %sel to i16169 ret i16 %trunc170}171 172; narrow zext type blocks fold173define i16 @selective_shift_16.narrow(i24 %mask, i16 %upper, i16 %lower) {174; CHECK-LABEL: define i16 @selective_shift_16.narrow(175; CHECK-SAME: i24 [[MASK:%.*]], i16 [[UPPER:%.*]], i16 [[LOWER:%.*]]) {176; CHECK-NEXT: [[UPPER_ZEXT:%.*]] = zext i16 [[UPPER]] to i24177; CHECK-NEXT: [[UPPER_SHL:%.*]] = shl i24 [[UPPER_ZEXT]], 16178; CHECK-NEXT: [[LOWER_ZEXT:%.*]] = zext i16 [[LOWER]] to i24179; CHECK-NEXT: [[PACK:%.*]] = or disjoint i24 [[UPPER_SHL]], [[LOWER_ZEXT]]180; CHECK-NEXT: [[MASK_BIT:%.*]] = and i24 [[MASK]], 16181; CHECK-NEXT: [[SEL:%.*]] = lshr i24 [[PACK]], [[MASK_BIT]]182; CHECK-NEXT: [[TRUNC:%.*]] = trunc i24 [[SEL]] to i16183; CHECK-NEXT: ret i16 [[TRUNC]]184;185 %upper.zext = zext i16 %upper to i24186 %upper.shl = shl i24 %upper.zext, 16187 %lower.zext = zext i16 %lower to i24188 %pack = or disjoint i24 %upper.shl, %lower.zext189 %mask.bit = and i24 %mask, 16190 %sel = lshr i24 %pack, %mask.bit191 %trunc = trunc i24 %sel to i16192 ret i16 %trunc193}194 195; %lower's upper bits block fold196define i16 @selective_shift_16_norange(i32 %mask, i32 %upper, i32 %lower) {197; CHECK-LABEL: define i16 @selective_shift_16_norange(198; CHECK-SAME: i32 [[MASK:%.*]], i32 [[UPPER:%.*]], i32 [[LOWER:%.*]]) {199; CHECK-NEXT: [[UPPER_SHL:%.*]] = shl nuw i32 [[UPPER]], 16200; CHECK-NEXT: [[PACK:%.*]] = or i32 [[UPPER_SHL]], [[LOWER]]201; CHECK-NEXT: [[MASK_BIT:%.*]] = and i32 [[MASK]], 16202; CHECK-NEXT: [[SEL:%.*]] = lshr i32 [[PACK]], [[MASK_BIT]]203; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SEL]] to i16204; CHECK-NEXT: ret i16 [[TRUNC]]205;206 %upper.shl = shl nuw i32 %upper, 16207 %pack = or i32 %upper.shl, %lower208 %mask.bit = and i32 %mask, 16209 %sel = lshr i32 %pack, %mask.bit210 %trunc = trunc i32 %sel to i16211 ret i16 %trunc212}213 214define i16 @selective_shift_16.mu.0(i32 %mask, i16 %upper, i16 %lower) {215; CHECK-LABEL: define i16 @selective_shift_16.mu.0(216; CHECK-SAME: i32 [[MASK:%.*]], i16 [[UPPER:%.*]], i16 [[LOWER:%.*]]) {217; CHECK-NEXT: [[UPPER_ZEXT:%.*]] = zext i16 [[UPPER]] to i32218; CHECK-NEXT: call void @clobber.i32(i32 [[UPPER_ZEXT]])219; CHECK-NEXT: [[LOWER_ZEXT:%.*]] = zext i16 [[LOWER]] to i32220; CHECK-NEXT: call void @clobber.i32(i32 [[LOWER_ZEXT]])221; CHECK-NEXT: [[MASK_BIT:%.*]] = and i32 [[MASK]], 16222; CHECK-NEXT: [[MASK_BIT_Z:%.*]] = icmp eq i32 [[MASK_BIT]], 0223; CHECK-NEXT: [[TRUNC:%.*]] = select i1 [[MASK_BIT_Z]], i16 [[LOWER]], i16 [[UPPER]]224; CHECK-NEXT: ret i16 [[TRUNC]]225;226 %upper.zext = zext i16 %upper to i32227 call void @clobber.i32(i32 %upper.zext)228 %upper.shl = shl nuw i32 %upper.zext, 16229 %lower.zext = zext i16 %lower to i32230 call void @clobber.i32(i32 %lower.zext)231 %pack = or disjoint i32 %upper.shl, %lower.zext232 %mask.bit = and i32 %mask, 16233 %sel = lshr i32 %pack, %mask.bit234 %trunc = trunc i32 %sel to i16235 ret i16 %trunc236}237 238; multi-use of %pack blocks fold239define i16 @selective_shift_16.mu.1(i32 %mask, i16 %upper, i16 %lower) {240; CHECK-LABEL: define i16 @selective_shift_16.mu.1(241; CHECK-SAME: i32 [[MASK:%.*]], i16 [[UPPER:%.*]], i16 [[LOWER:%.*]]) {242; CHECK-NEXT: [[UPPER_ZEXT:%.*]] = zext i16 [[UPPER]] to i32243; CHECK-NEXT: [[UPPER_SHL:%.*]] = shl nuw i32 [[UPPER_ZEXT]], 16244; CHECK-NEXT: [[LOWER_ZEXT:%.*]] = zext i16 [[LOWER]] to i32245; CHECK-NEXT: [[PACK:%.*]] = or disjoint i32 [[UPPER_SHL]], [[LOWER_ZEXT]]246; CHECK-NEXT: call void @clobber.i32(i32 [[PACK]])247; CHECK-NEXT: [[MASK_BIT:%.*]] = and i32 [[MASK]], 16248; CHECK-NEXT: [[SEL:%.*]] = lshr i32 [[PACK]], [[MASK_BIT]]249; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SEL]] to i16250; CHECK-NEXT: ret i16 [[TRUNC]]251;252 %upper.zext = zext i16 %upper to i32253 %upper.shl = shl nuw i32 %upper.zext, 16254 %lower.zext = zext i16 %lower to i32255 %pack = or disjoint i32 %upper.shl, %lower.zext256 call void @clobber.i32(i32 %pack)257 %mask.bit = and i32 %mask, 16258 %sel = lshr i32 %pack, %mask.bit259 %trunc = trunc i32 %sel to i16260 ret i16 %trunc261}262 263; non-truncated use of %sel blocks fold264define i16 @selective_shift_16.mu.2(i32 %mask, i16 %upper, i16 %lower) {265; CHECK-LABEL: define i16 @selective_shift_16.mu.2(266; CHECK-SAME: i32 [[MASK:%.*]], i16 [[UPPER:%.*]], i16 [[LOWER:%.*]]) {267; CHECK-NEXT: [[UPPER_ZEXT:%.*]] = zext i16 [[UPPER]] to i32268; CHECK-NEXT: [[UPPER_SHL:%.*]] = shl nuw i32 [[UPPER_ZEXT]], 16269; CHECK-NEXT: [[LOWER_ZEXT:%.*]] = zext i16 [[LOWER]] to i32270; CHECK-NEXT: [[PACK:%.*]] = or disjoint i32 [[UPPER_SHL]], [[LOWER_ZEXT]]271; CHECK-NEXT: [[MASK_BIT:%.*]] = and i32 [[MASK]], 16272; CHECK-NEXT: [[SEL:%.*]] = lshr i32 [[PACK]], [[MASK_BIT]]273; CHECK-NEXT: call void @clobber.i32(i32 [[SEL]])274; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SEL]] to i16275; CHECK-NEXT: ret i16 [[TRUNC]]276;277 %upper.zext = zext i16 %upper to i32278 %upper.shl = shl nuw i32 %upper.zext, 16279 %lower.zext = zext i16 %lower to i32280 %pack = or disjoint i32 %upper.shl, %lower.zext281 %mask.bit = and i32 %mask, 16282 %sel = lshr i32 %pack, %mask.bit283 call void @clobber.i32(i32 %sel)284 %trunc = trunc i32 %sel to i16285 ret i16 %trunc286}287 288; bitwidth must be a power of 2 to fold289define i24 @selective_shift_24(i48 %mask, i24 %upper, i24 %lower) {290; CHECK-LABEL: define i24 @selective_shift_24(291; CHECK-SAME: i48 [[MASK:%.*]], i24 [[UPPER:%.*]], i24 [[LOWER:%.*]]) {292; CHECK-NEXT: [[UPPER_ZEXT:%.*]] = zext i24 [[UPPER]] to i48293; CHECK-NEXT: [[UPPER_SHL:%.*]] = shl nuw i48 [[UPPER_ZEXT]], 24294; CHECK-NEXT: [[LOWER_ZEXT:%.*]] = zext i24 [[LOWER]] to i48295; CHECK-NEXT: [[PACK:%.*]] = or disjoint i48 [[UPPER_SHL]], [[LOWER_ZEXT]]296; CHECK-NEXT: [[MASK_BIT:%.*]] = and i48 [[MASK]], 24297; CHECK-NEXT: [[SEL:%.*]] = lshr i48 [[PACK]], [[MASK_BIT]]298; CHECK-NEXT: [[TRUNC:%.*]] = trunc i48 [[SEL]] to i24299; CHECK-NEXT: ret i24 [[TRUNC]]300;301 %upper.zext = zext i24 %upper to i48302 %upper.shl = shl nuw i48 %upper.zext, 24303 %lower.zext = zext i24 %lower to i48304 %pack = or disjoint i48 %upper.shl, %lower.zext305 %mask.bit = and i48 %mask, 24306 %sel = lshr i48 %pack, %mask.bit307 %trunc = trunc i48 %sel to i24308 ret i24 %trunc309}310 311define i32 @selective_shift_32(i64 %mask, i32 %upper, i32 %lower) {312; CHECK-LABEL: define i32 @selective_shift_32(313; CHECK-SAME: i64 [[MASK:%.*]], i32 [[UPPER:%.*]], i32 [[LOWER:%.*]]) {314; CHECK-NEXT: [[MASK_BIT:%.*]] = and i64 [[MASK]], 32315; CHECK-NEXT: [[MASK_BIT_Z:%.*]] = icmp eq i64 [[MASK_BIT]], 0316; CHECK-NEXT: [[SEL_V:%.*]] = select i1 [[MASK_BIT_Z]], i32 [[LOWER]], i32 [[UPPER]]317; CHECK-NEXT: ret i32 [[SEL_V]]318;319 %upper.zext = zext i32 %upper to i64320 %upper.shl = shl nuw i64 %upper.zext, 32321 %lower.zext = zext i32 %lower to i64322 %pack = or disjoint i64 %upper.shl, %lower.zext323 %mask.bit = and i64 %mask, 32324 %sel = lshr i64 %pack, %mask.bit325 %trunc = trunc i64 %sel to i32326 ret i32 %trunc327}328 329define i32 @selective_shift_32.commute(i64 %mask, i32 %upper, i32 %lower) {330; CHECK-LABEL: define i32 @selective_shift_32.commute(331; CHECK-SAME: i64 [[MASK:%.*]], i32 [[UPPER:%.*]], i32 [[LOWER:%.*]]) {332; CHECK-NEXT: [[MASK_BIT:%.*]] = and i64 [[MASK]], 32333; CHECK-NEXT: [[MASK_BIT_Z:%.*]] = icmp eq i64 [[MASK_BIT]], 0334; CHECK-NEXT: [[SEL_V:%.*]] = select i1 [[MASK_BIT_Z]], i32 [[LOWER]], i32 [[UPPER]]335; CHECK-NEXT: ret i32 [[SEL_V]]336;337 %upper.zext = zext i32 %upper to i64338 %upper.shl = shl nuw i64 %upper.zext, 32339 %lower.zext = zext i32 %lower to i64340 %pack = or disjoint i64 %lower.zext, %upper.shl341 %mask.bit = and i64 %mask, 32342 %sel = lshr i64 %pack, %mask.bit343 %trunc = trunc i64 %sel to i32344 ret i32 %trunc345}346