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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -passes=instcombine -S -o - %s | FileCheck %s3 4; Issue #548565 6; ((X u< 0x8000000) & ((X & 0x60000000) != 0x60000000)) -> X u< 0x600000007define i1 @icmp_power2_and_icmp_shifted_mask_2147483648_1610612736(i32 %x) {8; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_2147483648_1610612736(9; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 161061273610; CHECK-NEXT: ret i1 [[T4]]11;12 %t1 = icmp ult i32 %x, 214748364813 %t2 = and i32 %x, 161061273614 %t3 = icmp ne i32 %t2, 161061273615 %t4 = and i1 %t1, %t316 ret i1 %t417}18 19define i1 @icmp_power2_and_icmp_shifted_mask_swapped_2147483648_1610612736(i32 %x) {20; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_swapped_2147483648_1610612736(21; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 161061273622; CHECK-NEXT: ret i1 [[T4]]23;24 %t1 = icmp ult i32 %x, 214748364825 %t2 = and i32 %x, 161061273626 %t3 = icmp ne i32 %t2, 161061273627 %t4 = and i1 %t3, %t128 ret i1 %t429}30 31; ((X u< 0x8000000) & ((X & 0x7FFFFFFF) != 0x7FFFFFFF)) -> X u< 0x7FFFFFFF32define i1 @icmp_power2_and_icmp_shifted_mask_2147483648_2147483647(i32 %x) {33; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_2147483648_2147483647(34; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 214748364735; CHECK-NEXT: ret i1 [[T4]]36;37 %t1 = icmp ult i32 %x, 214748364838 %t2 = and i32 %x, 214748364739 %t3 = icmp ne i32 %t2, 214748364740 %t4 = and i1 %t1, %t341 ret i1 %t442}43 44define i1 @icmp_power2_and_icmp_shifted_mask_swapped_2147483648_2147483647(i32 %x) {45; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_swapped_2147483648_2147483647(46; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 214748364747; CHECK-NEXT: ret i1 [[T4]]48;49 %t1 = icmp ult i32 %x, 214748364850 %t2 = and i32 %x, 214748364751 %t3 = icmp ne i32 %t2, 214748364752 %t4 = and i1 %t3, %t153 ret i1 %t454}55 56; ((X u< 0x4000000) & ((X & 0x30000000) != 0x30000000)) -> X u< 0x3000000057define i1 @icmp_power2_and_icmp_shifted_mask_2147483648_805306368(i32 %x) {58; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_2147483648_805306368(59; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 80530636860; CHECK-NEXT: ret i1 [[T4]]61;62 %t1 = icmp ult i32 %x, 107374182463 %t2 = and i32 %x, 80530636864 %t3 = icmp ne i32 %t2, 80530636865 %t4 = and i1 %t1, %t366 ret i1 %t467}68 69define i1 @icmp_power2_and_icmp_shifted_mask_swapped_2147483648_805306368(i32 %x) {70; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_swapped_2147483648_805306368(71; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 80530636872; CHECK-NEXT: ret i1 [[T4]]73;74 %t1 = icmp ult i32 %x, 107374182475 %t2 = and i32 %x, 80530636876 %t3 = icmp ne i32 %t2, 80530636877 %t4 = and i1 %t3, %t178 ret i1 %t479}80 81; ((X u< 0x40000000) & ((X & 0x3FFFFFFF) != 0x3FFFFFFF)) -> X u< 0x3FFFFFFF82define i1 @icmp_power2_and_icmp_shifted_mask_1073741824_1073741823(i32 %x) {83; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_1073741824_1073741823(84; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 107374182385; CHECK-NEXT: ret i1 [[T4]]86;87 %t1 = icmp ult i32 %x, 107374182488 %t2 = and i32 %x, 107374182389 %t3 = icmp ne i32 %t2, 107374182390 %t4 = and i1 %t1, %t391 ret i1 %t492}93 94define i1 @icmp_power2_and_icmp_shifted_mask_swapped_1073741824_1073741823(i32 %x) {95; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_swapped_1073741824_1073741823(96; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 107374182397; CHECK-NEXT: ret i1 [[T4]]98;99 %t1 = icmp ult i32 %x, 1073741824100 %t2 = and i32 %x, 1073741823101 %t3 = icmp ne i32 %t2, 1073741823102 %t4 = and i1 %t3, %t1103 ret i1 %t4104}105 106; ((X u< 8) & ((X & 7) != 7)) -> X u< 7107define i1 @icmp_power2_and_icmp_shifted_mask_8_7(i32 %x) {108; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_8_7(109; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 7110; CHECK-NEXT: ret i1 [[T4]]111;112 %t1 = icmp ult i32 %x, 8113 %t2 = and i32 %x, 7114 %t3 = icmp ne i32 %t2, 7115 %t4 = and i1 %t1, %t3116 ret i1 %t4117}118 119define i1 @icmp_power2_and_icmp_shifted_mask_swapped_8_7(i32 %x) {120; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_swapped_8_7(121; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 7122; CHECK-NEXT: ret i1 [[T4]]123;124 %t1 = icmp ult i32 %x, 8125 %t2 = and i32 %x, 7126 %t3 = icmp ne i32 %t2, 7127 %t4 = and i1 %t3, %t1128 ret i1 %t4129}130 131; ((X u< 8) & ((X & 6) != 6)) -> X u< 6132define i1 @icmp_power2_and_icmp_shifted_mask_8_6(i32 %x) {133; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_8_6(134; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 6135; CHECK-NEXT: ret i1 [[T4]]136;137 %t1 = icmp ult i32 %x, 8138 %t2 = and i32 %x, 6139 %t3 = icmp ne i32 %t2, 6140 %t4 = and i1 %t1, %t3141 ret i1 %t4142}143 144define i1 @icmp_power2_and_icmp_shifted_mask_swapped_8_6(i32 %x) {145; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_swapped_8_6(146; CHECK-NEXT: [[T4:%.*]] = icmp ult i32 [[X:%.*]], 6147; CHECK-NEXT: ret i1 [[T4]]148;149 %t1 = icmp ult i32 %x, 8150 %t2 = and i32 %x, 6151 %t3 = icmp ne i32 %t2, 6152 %t4 = and i1 %t3, %t1153 ret i1 %t4154}155 156; ((X u< 8) & ((X & 5) != 5)) -> no change157define i1 @icmp_power2_and_icmp_shifted_mask_8_5_gap_in_mask_fail(i32 %x) {158; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_8_5_gap_in_mask_fail(159; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8160; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 5161; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 5162; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]163; CHECK-NEXT: ret i1 [[T4]]164;165 %t1 = icmp ult i32 %x, 8166 %t2 = and i32 %x, 5167 %t3 = icmp ne i32 %t2, 5168 %t4 = and i1 %t1, %t3169 ret i1 %t4170}171 172define i1 @icmp_power2_and_icmp_shifted_mask_swapped_8_5_gap_in_mask_fail(i32 %x) {173; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_swapped_8_5_gap_in_mask_fail(174; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8175; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 5176; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 5177; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]]178; CHECK-NEXT: ret i1 [[T4]]179;180 %t1 = icmp ult i32 %x, 8181 %t2 = and i32 %x, 5182 %t3 = icmp ne i32 %t2, 5183 %t4 = and i1 %t3, %t1184 ret i1 %t4185}186 187; ((X u< 8) & ((X & 3) != 3)) -> no change188define i1 @icmp_power2_and_icmp_shifted_mask_8_3_gap_between_masks_fail(i32 %x) {189; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_8_3_gap_between_masks_fail(190; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8191; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 3192; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 3193; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]194; CHECK-NEXT: ret i1 [[T4]]195;196 %t1 = icmp ult i32 %x, 8197 %t2 = and i32 %x, 3198 %t3 = icmp ne i32 %t2, 3199 %t4 = and i1 %t1, %t3200 ret i1 %t4201}202 203define i1 @icmp_power2_and_icmp_shifted_mask_swapped_8_3_gap_between_masks_fail(i32 %x) {204; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_swapped_8_3_gap_between_masks_fail(205; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8206; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 3207; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 3208; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]]209; CHECK-NEXT: ret i1 [[T4]]210;211 %t1 = icmp ult i32 %x, 8212 %t2 = and i32 %x, 3213 %t3 = icmp ne i32 %t2, 3214 %t4 = and i1 %t3, %t1215 ret i1 %t4216}217 218; ((X u< 0x100) & ((X & 0x0EF) != 0x0EF)) -> no change219define i1 @icmp_power2_and_icmp_shifted_mask_256_239_gap_in_mask_fail(i32 %x) {220; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_256_239_gap_in_mask_fail(221; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 256222; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 239223; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 239224; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]225; CHECK-NEXT: ret i1 [[T4]]226;227 %t1 = icmp ult i32 %x, 256228 %t2 = and i32 %x, 239229 %t3 = icmp ne i32 %t2, 239230 %t4 = and i1 %t1, %t3231 ret i1 %t4232}233 234define i1 @icmp_power2_and_icmp_shifted_mask_swapped_256_239_gap_in_mask_fail(i32 %x) {235; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_swapped_256_239_gap_in_mask_fail(236; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 256237; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 239238; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 239239; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]]240; CHECK-NEXT: ret i1 [[T4]]241;242 %t1 = icmp ult i32 %x, 256243 %t2 = and i32 %x, 239244 %t3 = icmp ne i32 %t2, 239245 %t4 = and i1 %t3, %t1246 ret i1 %t4247}248 249; ((X u< 0x08) & ((X & 0x70) != 0x70)) -> no change250define i1 @icmp_power2_and_icmp_shifted_mask_8_112_mask_to_left_fail(i32 %x) {251; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_8_112_mask_to_left_fail(252; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8253; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 112254; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 112255; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]256; CHECK-NEXT: ret i1 [[T4]]257;258 %t1 = icmp ult i32 %x, 8259 %t2 = and i32 %x, 112260 %t3 = icmp ne i32 %t2, 112261 %t4 = and i1 %t1, %t3262 ret i1 %t4263}264 265define i1 @icmp_power2_and_icmp_shifted_mask_swapped_8_112_mask_to_left_fail(i32 %x) {266; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_swapped_8_112_mask_to_left_fail(267; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8268; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 112269; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 112270; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]]271; CHECK-NEXT: ret i1 [[T4]]272;273 %t1 = icmp ult i32 %x, 8274 %t2 = and i32 %x, 112275 %t3 = icmp ne i32 %t2, 112276 %t4 = and i1 %t3, %t1277 ret i1 %t4278}279 280; ((X u< 0x08) & ((X & 0x38) != 0x38))) -> no change281define i1 @icmp_power2_and_icmp_shifted_mask_8_56_mask_overlap_fail(i32 %x) {282; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_8_56_mask_overlap_fail(283; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8284; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 56285; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 56286; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]287; CHECK-NEXT: ret i1 [[T4]]288;289 %t1 = icmp ult i32 %x, 8290 %t2 = and i32 %x, 56291 %t3 = icmp ne i32 %t2, 56292 %t4 = and i1 %t1, %t3293 ret i1 %t4294}295 296define i1 @icmp_power2_and_icmp_shifted_mask_swapped_8_56_mask_overlap_fail(i32 %x) {297; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_swapped_8_56_mask_overlap_fail(298; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8299; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 56300; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 56301; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]]302; CHECK-NEXT: ret i1 [[T4]]303;304 %t1 = icmp ult i32 %x, 8305 %t2 = and i32 %x, 56306 %t3 = icmp ne i32 %t2, 56307 %t4 = and i1 %t3, %t1308 ret i1 %t4309}310 311; ((X u< 0x08) & ((X & 0x18) != 0x18)) -> no change312define i1 @icmp_power2_and_icmp_shifted_mask_8_24_mask_overlap_fail(i32 %x) {313; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_8_24_mask_overlap_fail(314; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8315; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 24316; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 24317; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]318; CHECK-NEXT: ret i1 [[T4]]319;320 %t1 = icmp ult i32 %x, 8321 %t2 = and i32 %x, 24322 %t3 = icmp ne i32 %t2, 24323 %t4 = and i1 %t1, %t3324 ret i1 %t4325}326 327define i1 @icmp_power2_and_icmp_shifted_mask_swapped_8_24_mask_overlap_fail(i32 %x) {328; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_swapped_8_24_mask_overlap_fail(329; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8330; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 24331; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 24332; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]]333; CHECK-NEXT: ret i1 [[T4]]334;335 %t1 = icmp ult i32 %x, 8336 %t2 = and i32 %x, 24337 %t3 = icmp ne i32 %t2, 24338 %t4 = and i1 %t3, %t1339 ret i1 %t4340}341 342; ((X u< 0x8) & ((X & 0xC) != 0xC)) -> no change343define i1 @icmp_power2_and_icmp_shifted_mask_8_12_mask_overlap_fail(i32 %x) {344; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_8_12_mask_overlap_fail(345; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8346; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 12347; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 12348; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[T3]]349; CHECK-NEXT: ret i1 [[T4]]350;351 %t1 = icmp ult i32 %x, 8352 %t2 = and i32 %x, 12353 %t3 = icmp ne i32 %t2, 12354 %t4 = and i1 %t1, %t3355 ret i1 %t4356}357 358define i1 @icmp_power2_and_icmp_shifted_mask_swapped_8_12_mask_overlap_fail(i32 %x) {359; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_swapped_8_12_mask_overlap_fail(360; CHECK-NEXT: [[T1:%.*]] = icmp ult i32 [[X:%.*]], 8361; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], 12362; CHECK-NEXT: [[T3:%.*]] = icmp ne i32 [[T2]], 12363; CHECK-NEXT: [[T4:%.*]] = and i1 [[T3]], [[T1]]364; CHECK-NEXT: ret i1 [[T4]]365;366 %t1 = icmp ult i32 %x, 8367 %t2 = and i32 %x, 12368 %t3 = icmp ne i32 %t2, 12369 %t4 = and i1 %t3, %t1370 ret i1 %t4371}372 373; Vector of 1 reduction374define <1 x i1> @icmp_power2_and_icmp_shifted_mask_vector_2147483648_2147483647(<1 x i32> %x) {375; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_2147483648_2147483647(376; CHECK-NEXT: [[T4:%.*]] = icmp ult <1 x i32> [[X:%.*]], splat (i32 2147483647)377; CHECK-NEXT: ret <1 x i1> [[T4]]378;379 %t1 = icmp ult <1 x i32> %x, <i32 2147483648>380 %t2 = and <1 x i32> %x, <i32 2147483647>381 %t3 = icmp ne <1 x i32> %t2, <i32 2147483647>382 %t4 = and <1 x i1> %t1, %t3383 ret <1 x i1> %t4384}385 386define <1 x i1> @icmp_power2_and_icmp_shifted_mask_vector_swapped_2147483648_2147483647(<1 x i32> %x) {387; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_swapped_2147483648_2147483647(388; CHECK-NEXT: [[T4:%.*]] = icmp ult <1 x i32> [[X:%.*]], splat (i32 2147483647)389; CHECK-NEXT: ret <1 x i1> [[T4]]390;391 %t1 = icmp ult <1 x i32> %x, <i32 2147483648>392 %t2 = and <1 x i32> %x, <i32 2147483647>393 %t3 = icmp ne <1 x i32> %t2, <i32 2147483647>394 %t4 = and <1 x i1> %t3, %t1395 ret <1 x i1> %t4396}397 398; Vector of 2 reduction399define <2 x i1> @icmp_power2_and_icmp_shifted_mask_vector_2147483648_1610612736_2147483647(<2 x i32> %x) {400; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_2147483648_1610612736_2147483647(401; CHECK-NEXT: [[T4:%.*]] = icmp ult <2 x i32> [[X:%.*]], <i32 1610612736, i32 2147483647>402; CHECK-NEXT: ret <2 x i1> [[T4]]403;404 %t1 = icmp ult <2 x i32> %x, <i32 2147483648, i32 2147483648>405 %t2 = and <2 x i32> %x, <i32 1610612736, i32 2147483647>406 %t3 = icmp ne <2 x i32> %t2, <i32 1610612736, i32 2147483647>407 %t4 = and <2 x i1> %t1, %t3408 ret <2 x i1> %t4409}410 411define <2 x i1> @icmp_power2_and_icmp_shifted_mask_vector_swapped_2147483648_1610612736_2147483647(<2 x i32> %x) {412; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_swapped_2147483648_1610612736_2147483647(413; CHECK-NEXT: [[T4:%.*]] = icmp ult <2 x i32> [[X:%.*]], <i32 1610612736, i32 2147483647>414; CHECK-NEXT: ret <2 x i1> [[T4]]415;416 %t1 = icmp ult <2 x i32> %x, <i32 2147483648, i32 2147483648>417 %t2 = and <2 x i32> %x, <i32 1610612736, i32 2147483647>418 %t3 = icmp ne <2 x i32> %t2, <i32 1610612736, i32 2147483647>419 %t4 = and <2 x i1> %t3, %t1420 ret <2 x i1> %t4421}422 423; Vector of 2 reduction with splat containing poison424define <2 x i1> @icmp_power2_and_icmp_shifted_mask_vector_splat_poison_2147483648_1610612736_2147483647(<2 x i32> %x) {425; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_splat_poison_2147483648_1610612736_2147483647(426; CHECK-NEXT: [[T4:%.*]] = icmp ult <2 x i32> [[X:%.*]], <i32 1610612736, i32 2147483647>427; CHECK-NEXT: ret <2 x i1> [[T4]]428;429 %t1 = icmp ult <2 x i32> %x, <i32 2147483648, i32 poison>430 %t2 = and <2 x i32> %x, <i32 1610612736, i32 2147483647>431 %t3 = icmp ne <2 x i32> %t2, <i32 1610612736, i32 2147483647>432 %t4 = and <2 x i1> %t1, %t3433 ret <2 x i1> %t4434}435 436define <2 x i1> @icmp_power2_and_icmp_shifted_mask_vector_swapped_splat_poison_2147483648_1610612736_2147483647(<2 x i32> %x) {437; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_swapped_splat_poison_2147483648_1610612736_2147483647(438; CHECK-NEXT: [[T4:%.*]] = icmp ult <2 x i32> [[X:%.*]], <i32 1610612736, i32 2147483647>439; CHECK-NEXT: ret <2 x i1> [[T4]]440;441 %t1 = icmp ult <2 x i32> %x, <i32 2147483648, i32 poison>442 %t2 = and <2 x i32> %x, <i32 1610612736, i32 2147483647>443 %t3 = icmp ne <2 x i32> %t2, <i32 1610612736, i32 2147483647>444 %t4 = and <2 x i1> %t3, %t1445 ret <2 x i1> %t4446}447 448; Vector of 2 reduction with splat containing undef449define <2 x i1> @icmp_power2_and_icmp_shifted_mask_vector_splat_undef_2147483648_1610612736_2147483647(<2 x i32> %x) {450; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_splat_undef_2147483648_1610612736_2147483647(451; CHECK-NEXT: [[T1:%.*]] = icmp ult <2 x i32> [[X:%.*]], <i32 -2147483648, i32 undef>452; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[X]], <i32 1610612736, i32 2147483647>453; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], <i32 1610612736, i32 2147483647>454; CHECK-NEXT: [[T4:%.*]] = and <2 x i1> [[T1]], [[T3]]455; CHECK-NEXT: ret <2 x i1> [[T4]]456;457 %t1 = icmp ult <2 x i32> %x, <i32 2147483648, i32 undef>458 %t2 = and <2 x i32> %x, <i32 1610612736, i32 2147483647>459 %t3 = icmp ne <2 x i32> %t2, <i32 1610612736, i32 2147483647>460 %t4 = and <2 x i1> %t1, %t3461 ret <2 x i1> %t4462}463 464define <2 x i1> @icmp_power2_and_icmp_shifted_mask_vector_swapped_splat_undef_2147483648_1610612736_2147483647(<2 x i32> %x) {465; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_swapped_splat_undef_2147483648_1610612736_2147483647(466; CHECK-NEXT: [[T1:%.*]] = icmp ult <2 x i32> [[X:%.*]], <i32 -2147483648, i32 undef>467; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[X]], <i32 1610612736, i32 2147483647>468; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], <i32 1610612736, i32 2147483647>469; CHECK-NEXT: [[T4:%.*]] = and <2 x i1> [[T3]], [[T1]]470; CHECK-NEXT: ret <2 x i1> [[T4]]471;472 %t1 = icmp ult <2 x i32> %x, <i32 2147483648, i32 undef>473 %t2 = and <2 x i32> %x, <i32 1610612736, i32 2147483647>474 %t3 = icmp ne <2 x i32> %t2, <i32 1610612736, i32 2147483647>475 %t4 = and <2 x i1> %t3, %t1476 ret <2 x i1> %t4477}478 479; Vector of 7 reduction480define <7 x i1> @icmp_power2_and_icmp_shifted_mask_vector_128_others(<7 x i8> %x) {481; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_128_others(482; CHECK-NEXT: [[T4:%.*]] = icmp ult <7 x i8> [[X:%.*]], <i8 127, i8 126, i8 124, i8 120, i8 112, i8 96, i8 64>483; CHECK-NEXT: ret <7 x i1> [[T4]]484;485 %t1 = icmp ult <7 x i8> %x, <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>486 %t2 = and <7 x i8> %x, <i8 127, i8 126, i8 124, i8 120, i8 112, i8 96, i8 64>487 %t3 = icmp ne <7 x i8> %t2, <i8 127, i8 126, i8 124, i8 120, i8 112, i8 96, i8 64>488 %t4 = and <7 x i1> %t1, %t3489 ret <7 x i1> %t4490}491 492define <7 x i1> @icmp_power2_and_icmp_shifted_mask_vector_swapped_128_others(<7 x i8> %x) {493; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_swapped_128_others(494; CHECK-NEXT: [[T4:%.*]] = icmp ult <7 x i8> [[X:%.*]], <i8 127, i8 126, i8 124, i8 120, i8 112, i8 96, i8 64>495; CHECK-NEXT: ret <7 x i1> [[T4]]496;497 %t1 = icmp ult <7 x i8> %x, <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>498 %t2 = and <7 x i8> %x, <i8 127, i8 126, i8 124, i8 120, i8 112, i8 96, i8 64>499 %t3 = icmp ne <7 x i8> %t2, <i8 127, i8 126, i8 124, i8 120, i8 112, i8 96, i8 64>500 %t4 = and <7 x i1> %t3, %t1501 ret <7 x i1> %t4502}503 504; Vector of 6 reduction505define <6 x i1> @icmp_power2_and_icmp_shifted_mask_vector_64_others(<6 x i8> %x) {506; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_64_others(507; CHECK-NEXT: [[T4:%.*]] = icmp ult <6 x i8> [[X:%.*]], <i8 63, i8 62, i8 60, i8 56, i8 48, i8 32>508; CHECK-NEXT: ret <6 x i1> [[T4]]509;510 %t1 = icmp ult <6 x i8> %x, <i8 64, i8 64, i8 64, i8 64, i8 64, i8 64>511 %t2 = and <6 x i8> %x, <i8 63, i8 62, i8 60, i8 56, i8 48, i8 32>512 %t3 = icmp ne <6 x i8> %t2, <i8 63, i8 62, i8 60, i8 56, i8 48, i8 32>513 %t4 = and <6 x i1> %t1, %t3514 ret <6 x i1> %t4515}516 517define <6 x i1> @icmp_power2_and_icmp_shifted_mask_vector_swapped_64_others(<6 x i8> %x) {518; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_swapped_64_others(519; CHECK-NEXT: [[T4:%.*]] = icmp ult <6 x i8> [[X:%.*]], <i8 63, i8 62, i8 60, i8 56, i8 48, i8 32>520; CHECK-NEXT: ret <6 x i1> [[T4]]521;522 %t1 = icmp ult <6 x i8> %x, <i8 64, i8 64, i8 64, i8 64, i8 64, i8 64>523 %t2 = and <6 x i8> %x, <i8 63, i8 62, i8 60, i8 56, i8 48, i8 32>524 %t3 = icmp ne <6 x i8> %t2, <i8 63, i8 62, i8 60, i8 56, i8 48, i8 32>525 %t4 = and <6 x i1> %t1, %t3526 ret <6 x i1> %t4527}528 529; Vector of 0 of 1 compatible, no change530define <1 x i1> @icmp_power2_and_icmp_shifted_mask_vector_2147483648_2147482647_gap_in_mask_fail(<1 x i32> %x) {531; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_2147483648_2147482647_gap_in_mask_fail(532; CHECK-NEXT: [[T1:%.*]] = icmp sgt <1 x i32> [[X:%.*]], splat (i32 -1)533; CHECK-NEXT: [[T2:%.*]] = and <1 x i32> [[X]], splat (i32 2147482647)534; CHECK-NEXT: [[T3:%.*]] = icmp ne <1 x i32> [[T2]], splat (i32 2147482647)535; CHECK-NEXT: [[T4:%.*]] = and <1 x i1> [[T1]], [[T3]]536; CHECK-NEXT: ret <1 x i1> [[T4]]537;538 %t1 = icmp ult <1 x i32> %x, <i32 2147483648>539 %t2 = and <1 x i32> %x, <i32 2147482647>540 %t3 = icmp ne <1 x i32> %t2, <i32 2147482647>541 %t4 = and <1 x i1> %t1, %t3542 ret <1 x i1> %t4543}544 545define <1 x i1> @icmp_power2_and_icmp_shifted_mask_vector_swapped_2147483648_2147482647_gap_in_mask_fail(<1 x i32> %x) {546; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_swapped_2147483648_2147482647_gap_in_mask_fail(547; CHECK-NEXT: [[T1:%.*]] = icmp sgt <1 x i32> [[X:%.*]], splat (i32 -1)548; CHECK-NEXT: [[T2:%.*]] = and <1 x i32> [[X]], splat (i32 2147482647)549; CHECK-NEXT: [[T3:%.*]] = icmp ne <1 x i32> [[T2]], splat (i32 2147482647)550; CHECK-NEXT: [[T4:%.*]] = and <1 x i1> [[T3]], [[T1]]551; CHECK-NEXT: ret <1 x i1> [[T4]]552;553 %t1 = icmp ult <1 x i32> %x, <i32 2147483648>554 %t2 = and <1 x i32> %x, <i32 2147482647>555 %t3 = icmp ne <1 x i32> %t2, <i32 2147482647>556 %t4 = and <1 x i1> %t3, %t1557 ret <1 x i1> %t4558}559 560; Vector 1 of 2 compatible, no change561define <2 x i1> @icmp_power2_and_icmp_shifted_mask_vector_2147483648_1073741823_gap_between_masks_fail(<2 x i32> %x) {562; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_2147483648_1073741823_gap_between_masks_fail(563; CHECK-NEXT: [[T1:%.*]] = icmp sgt <2 x i32> [[X:%.*]], splat (i32 -1)564; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[X]], <i32 1610612736, i32 1073741823>565; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], <i32 1610612736, i32 1073741823>566; CHECK-NEXT: [[T4:%.*]] = and <2 x i1> [[T1]], [[T3]]567; CHECK-NEXT: ret <2 x i1> [[T4]]568;569 %t1 = icmp ult <2 x i32> %x, <i32 2147483648, i32 2147483648>570 %t2 = and <2 x i32> %x, <i32 1610612736, i32 1073741823>571 %t3 = icmp ne <2 x i32> %t2, <i32 1610612736, i32 1073741823>572 %t4 = and <2 x i1> %t1, %t3573 ret <2 x i1> %t4574}575 576define <2 x i1> @icmp_power2_and_icmp_shifted_mask_vector_swapped_2147483648_1073741823_gap_between_masks_fail(<2 x i32> %x) {577; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_swapped_2147483648_1073741823_gap_between_masks_fail(578; CHECK-NEXT: [[T1:%.*]] = icmp sgt <2 x i32> [[X:%.*]], splat (i32 -1)579; CHECK-NEXT: [[T2:%.*]] = and <2 x i32> [[X]], <i32 1610612736, i32 1073741823>580; CHECK-NEXT: [[T3:%.*]] = icmp ne <2 x i32> [[T2]], <i32 1610612736, i32 1073741823>581; CHECK-NEXT: [[T4:%.*]] = and <2 x i1> [[T3]], [[T1]]582; CHECK-NEXT: ret <2 x i1> [[T4]]583;584 %t1 = icmp ult <2 x i32> %x, <i32 2147483648, i32 2147483648>585 %t2 = and <2 x i32> %x, <i32 1610612736, i32 1073741823>586 %t3 = icmp ne <2 x i32> %t2, <i32 1610612736, i32 1073741823>587 %t4 = and <2 x i1> %t3, %t1588 ret <2 x i1> %t4589}590 591; Vector 1 of 7 compatible, no change592define <7 x i1> @icmp_power2_and_icmp_shifted_mask_vector_128_1_of_7_fail(<7 x i8> %x) {593; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_128_1_of_7_fail(594; CHECK-NEXT: [[T1:%.*]] = icmp sgt <7 x i8> [[X:%.*]], splat (i8 -1)595; CHECK-NEXT: [[T2:%.*]] = and <7 x i8> [[X]], <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32, i8 64>596; CHECK-NEXT: [[T3:%.*]] = icmp ne <7 x i8> [[T2]], <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32, i8 64>597; CHECK-NEXT: [[T4:%.*]] = and <7 x i1> [[T1]], [[T3]]598; CHECK-NEXT: ret <7 x i1> [[T4]]599;600 %t1 = icmp ult <7 x i8> %x, <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>601 %t2 = and <7 x i8> %x, <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32, i8 64>602 %t3 = icmp ne <7 x i8> %t2, <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32, i8 64>603 %t4 = and <7 x i1> %t1, %t3604 ret <7 x i1> %t4605}606 607define <7 x i1> @icmp_power2_and_icmp_shifted_mask_vector_swapped_128_1_of_7_fail(<7 x i8> %x) {608; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_swapped_128_1_of_7_fail(609; CHECK-NEXT: [[T1:%.*]] = icmp sgt <7 x i8> [[X:%.*]], splat (i8 -1)610; CHECK-NEXT: [[T2:%.*]] = and <7 x i8> [[X]], <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32, i8 64>611; CHECK-NEXT: [[T3:%.*]] = icmp ne <7 x i8> [[T2]], <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32, i8 64>612; CHECK-NEXT: [[T4:%.*]] = and <7 x i1> [[T3]], [[T1]]613; CHECK-NEXT: ret <7 x i1> [[T4]]614;615 %t1 = icmp ult <7 x i8> %x, <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>616 %t2 = and <7 x i8> %x, <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32, i8 64>617 %t3 = icmp ne <7 x i8> %t2, <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32, i8 64>618 %t4 = and <7 x i1> %t3, %t1619 ret <7 x i1> %t4620}621 622; Vector 0 of 6 compatible, no change623define <6 x i1> @icmp_power2_and_icmp_shifted_mask_vector_128_0_of_6_fail(<6 x i8> %x) {624; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_128_0_of_6_fail(625; CHECK-NEXT: [[T1:%.*]] = icmp sgt <6 x i8> [[X:%.*]], splat (i8 -1)626; CHECK-NEXT: [[T2:%.*]] = and <6 x i8> [[X]], <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32>627; CHECK-NEXT: [[T3:%.*]] = icmp ne <6 x i8> [[T2]], <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32>628; CHECK-NEXT: [[T4:%.*]] = and <6 x i1> [[T1]], [[T3]]629; CHECK-NEXT: ret <6 x i1> [[T4]]630;631 %t1 = icmp ult <6 x i8> %x, <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>632 %t2 = and <6 x i8> %x, <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32>633 %t3 = icmp ne <6 x i8> %t2, <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32>634 %t4 = and <6 x i1> %t1, %t3635 ret <6 x i1> %t4636}637 638define <6 x i1> @icmp_power2_and_icmp_shifted_mask_vector_swapped_128_0_of_6_fail(<6 x i8> %x) {639; CHECK-LABEL: @icmp_power2_and_icmp_shifted_mask_vector_swapped_128_0_of_6_fail(640; CHECK-NEXT: [[T1:%.*]] = icmp sgt <6 x i8> [[X:%.*]], splat (i8 -1)641; CHECK-NEXT: [[T2:%.*]] = and <6 x i8> [[X]], <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32>642; CHECK-NEXT: [[T3:%.*]] = icmp ne <6 x i8> [[T2]], <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32>643; CHECK-NEXT: [[T4:%.*]] = and <6 x i1> [[T3]], [[T1]]644; CHECK-NEXT: ret <6 x i1> [[T4]]645;646 %t1 = icmp ult <6 x i8> %x, <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>647 %t2 = and <6 x i8> %x, <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32>648 %t3 = icmp ne <6 x i8> %t2, <i8 125, i8 122, i8 116, i8 104, i8 80, i8 32>649 %t4 = and <6 x i1> %t3, %t1650 ret <6 x i1> %t4651}652