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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 22; RUN: opt < %s -S -passes=instcombine | FileCheck %s3 4define i1 @vector_reduce_maximum_signbit(<4 x double> nofpclass(nan nzero) %x) {5; CHECK-LABEL: define i1 @vector_reduce_maximum_signbit6; CHECK-SAME: (<4 x double> nofpclass(nan nzero) [[X:%.*]]) {7; CHECK-NEXT: ret i1 true8;9 %x.abs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %x)10 %op = call double @llvm.vector.reduce.fmaximum.v4f64(<4 x double> %x.abs)11 %cmp = fcmp oge double %op, 0.012 ret i1 %cmp13}14 15define i1 @vector_reduce_maximum_signbit_fail_maybe_nan(<4 x double> nofpclass(nzero) %x) {16; CHECK-LABEL: define i1 @vector_reduce_maximum_signbit_fail_maybe_nan17; CHECK-SAME: (<4 x double> nofpclass(nzero) [[X:%.*]]) {18; CHECK-NEXT: [[X_ABS:%.*]] = call <4 x double> @llvm.fabs.v4f64(<4 x double> [[X]])19; CHECK-NEXT: [[OP:%.*]] = call double @llvm.vector.reduce.fmaximum.v4f64(<4 x double> [[X_ABS]])20; CHECK-NEXT: [[CMP:%.*]] = fcmp oge double [[OP]], 0.000000e+0021; CHECK-NEXT: ret i1 [[CMP]]22;23 %x.abs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %x)24 %op = call double @llvm.vector.reduce.fmaximum.v4f64(<4 x double> %x.abs)25 %cmp = fcmp oge double %op, 0.026 ret i1 %cmp27}28 29 30define i1 @vector_reduce_minimum_signbit(<4 x double> nofpclass(nan nzero) %x) {31; CHECK-LABEL: define i1 @vector_reduce_minimum_signbit32; CHECK-SAME: (<4 x double> nofpclass(nan nzero) [[X:%.*]]) {33; CHECK-NEXT: ret i1 true34;35 %x.abs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %x)36 %op = call double @llvm.vector.reduce.fminimum.v4f64(<4 x double> %x.abs)37 %cmp = fcmp oge double %op, 0.038 ret i1 %cmp39}40 41define i1 @vector_reduce_minimum_signbit_fail_maybe_nan(<4 x double> nofpclass(nzero) %x) {42; CHECK-LABEL: define i1 @vector_reduce_minimum_signbit_fail_maybe_nan43; CHECK-SAME: (<4 x double> nofpclass(nzero) [[X:%.*]]) {44; CHECK-NEXT: [[X_ABS:%.*]] = call <4 x double> @llvm.fabs.v4f64(<4 x double> [[X]])45; CHECK-NEXT: [[OP:%.*]] = call double @llvm.vector.reduce.fminimum.v4f64(<4 x double> [[X_ABS]])46; CHECK-NEXT: [[CMP:%.*]] = fcmp oge double [[OP]], 0.000000e+0047; CHECK-NEXT: ret i1 [[CMP]]48;49 %x.abs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %x)50 %op = call double @llvm.vector.reduce.fminimum.v4f64(<4 x double> %x.abs)51 %cmp = fcmp oge double %op, 0.052 ret i1 %cmp53}54 55define i1 @vector_reduce_max_signbit(<4 x double> nofpclass(nan nzero) %x) {56; CHECK-LABEL: define i1 @vector_reduce_max_signbit57; CHECK-SAME: (<4 x double> nofpclass(nan nzero) [[X:%.*]]) {58; CHECK-NEXT: ret i1 true59;60 %x.abs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %x)61 %op = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %x.abs)62 %cmp = fcmp oge double %op, 0.063 ret i1 %cmp64}65 66define i1 @vector_reduce_max_signbit_fail_maybe_nan(<4 x double> nofpclass(nzero) %x) {67; CHECK-LABEL: define i1 @vector_reduce_max_signbit_fail_maybe_nan68; CHECK-SAME: (<4 x double> nofpclass(nzero) [[X:%.*]]) {69; CHECK-NEXT: [[X_ABS:%.*]] = call <4 x double> @llvm.fabs.v4f64(<4 x double> [[X]])70; CHECK-NEXT: [[OP:%.*]] = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> [[X_ABS]])71; CHECK-NEXT: [[CMP:%.*]] = fcmp oge double [[OP]], 0.000000e+0072; CHECK-NEXT: ret i1 [[CMP]]73;74 %x.abs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %x)75 %op = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %x.abs)76 %cmp = fcmp oge double %op, 0.077 ret i1 %cmp78}79 80 81define i1 @vector_reduce_min_signbit(<4 x double> nofpclass(nan nzero) %x) {82; CHECK-LABEL: define i1 @vector_reduce_min_signbit83; CHECK-SAME: (<4 x double> nofpclass(nan nzero) [[X:%.*]]) {84; CHECK-NEXT: ret i1 true85;86 %x.abs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %x)87 %op = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %x.abs)88 %cmp = fcmp oge double %op, 0.089 ret i1 %cmp90}91 92define i1 @vector_reduce_min_signbit_fail_maybe_nan(<4 x double> nofpclass(nzero) %x) {93; CHECK-LABEL: define i1 @vector_reduce_min_signbit_fail_maybe_nan94; CHECK-SAME: (<4 x double> nofpclass(nzero) [[X:%.*]]) {95; CHECK-NEXT: [[X_ABS:%.*]] = call <4 x double> @llvm.fabs.v4f64(<4 x double> [[X]])96; CHECK-NEXT: [[OP:%.*]] = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> [[X_ABS]])97; CHECK-NEXT: [[CMP:%.*]] = fcmp oge double [[OP]], 0.000000e+0098; CHECK-NEXT: ret i1 [[CMP]]99;100 %x.abs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %x)101 %op = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %x.abs)102 %cmp = fcmp oge double %op, 0.0103 ret i1 %cmp104}105 106 107 108define i1 @vector_reduce_min_signbit_nnan_from_fmf(<4 x double> nofpclass(nzero) %x) {109; CHECK-LABEL: define i1 @vector_reduce_min_signbit_nnan_from_fmf110; CHECK-SAME: (<4 x double> nofpclass(nzero) [[X:%.*]]) {111; CHECK-NEXT: ret i1 true112;113 %x.abs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %x)114 %op = call nnan double @llvm.vector.reduce.fmin.v4f64(<4 x double> %x.abs)115 %cmp = fcmp oge double %op, 0.0116 ret i1 %cmp117}118 119 120