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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 62; RUN: opt < %s -passes=instcombine -S | FileCheck %s3 4define i32 @test_smin(i32 %arg0, i32 %arg1) {5; CHECK-LABEL: define i32 @test_smin(6; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) {7; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[ARG0]], [[ARG1]]8; CHECK-NEXT: [[V3:%.*]] = zext i1 [[TMP1]] to i329; CHECK-NEXT: ret i32 [[V3]]10;11 %v0 = tail call i32 @llvm.smin.i32(i32 %arg0, i32 %arg1)12 %v1 = add nsw i32 %arg0, 113 %v2 = tail call i32 @llvm.smin.i32(i32 %v1, i32 %arg1)14 %v3 = sub i32 %v2, %v015 ret i32 %v316}17 18define i32 @test_umin(i32 %arg0, i32 %arg1) {19; CHECK-LABEL: define i32 @test_umin(20; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) {21; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[ARG0]], [[ARG1]]22; CHECK-NEXT: [[V3:%.*]] = zext i1 [[TMP1]] to i3223; CHECK-NEXT: ret i32 [[V3]]24;25 %v0 = tail call i32 @llvm.umin.i32(i32 %arg0, i32 %arg1)26 %v1 = add nuw i32 %arg0, 127 %v2 = tail call i32 @llvm.umin.i32(i32 %v1, i32 %arg1)28 %v3 = sub i32 %v2, %v029 ret i32 %v330}31 32define i1 @test_smin_i1(i1 %arg0, i1 %arg1) {33; CHECK-LABEL: define i1 @test_smin_i1(34; CHECK-SAME: i1 [[ARG0:%.*]], i1 [[ARG1:%.*]]) {35; CHECK-NEXT: [[V0:%.*]] = or i1 [[ARG0]], [[ARG1]]36; CHECK-NEXT: [[V3:%.*]] = xor i1 [[V0]], true37; CHECK-NEXT: ret i1 [[V3]]38;39 %v0 = tail call i1 @llvm.smin.i1(i1 %arg0, i1 %arg1)40 %v1 = add nsw i1 %arg0, 141 %v2 = tail call i1 @llvm.smin.i1(i1 %v1, i1 %arg1)42 %v3 = sub i1 %v2, %v043 ret i1 %v344}45 46declare void @use(i2)47 48define i2 @test_smin_use_operands(i2 %arg0, i2 %arg1) {49; CHECK-LABEL: define i2 @test_smin_use_operands(50; CHECK-SAME: i2 [[ARG0:%.*]], i2 [[ARG1:%.*]]) {51; CHECK-NEXT: [[V0:%.*]] = tail call i2 @llvm.smin.i2(i2 [[ARG0]], i2 [[ARG1]])52; CHECK-NEXT: [[V1:%.*]] = add nsw i2 [[ARG0]], 153; CHECK-NEXT: [[V2:%.*]] = tail call i2 @llvm.smin.i2(i2 [[V1]], i2 [[ARG1]])54; CHECK-NEXT: [[V3:%.*]] = sub i2 [[V2]], [[V0]]55; CHECK-NEXT: call void @use(i2 [[V2]])56; CHECK-NEXT: call void @use(i2 [[V0]])57; CHECK-NEXT: ret i2 [[V3]]58;59 %v0 = tail call i2 @llvm.smin.i2(i2 %arg0, i2 %arg1)60 %v1 = add nsw i2 %arg0, 161 %v2 = tail call i2 @llvm.smin.i2(i2 %v1, i2 %arg1)62 %v3 = sub i2 %v2, %v063 call void @use(i2 %v2)64 call void @use(i2 %v0)65 ret i2 %v366}67 68define i2 @test_smin_use_operand(i2 %arg0, i2 %arg1) {69; CHECK-LABEL: define i2 @test_smin_use_operand(70; CHECK-SAME: i2 [[ARG0:%.*]], i2 [[ARG1:%.*]]) {71; CHECK-NEXT: [[V1:%.*]] = add nsw i2 [[ARG0]], 172; CHECK-NEXT: [[V2:%.*]] = tail call i2 @llvm.smin.i2(i2 [[V1]], i2 [[ARG1]])73; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i2 [[ARG0]], [[ARG1]]74; CHECK-NEXT: [[V3:%.*]] = zext i1 [[TMP1]] to i275; CHECK-NEXT: call void @use(i2 [[V2]])76; CHECK-NEXT: ret i2 [[V3]]77;78 %v0 = tail call i2 @llvm.smin.i2(i2 %arg0, i2 %arg1)79 %v1 = add nsw i2 %arg0, 180 %v2 = tail call i2 @llvm.smin.i2(i2 %v1, i2 %arg1)81 %v3 = sub i2 %v2, %v082 call void @use(i2 %v2)83 ret i2 %v384}85 86define i32 @test_smin_missing_nsw(i32 %arg0, i32 %arg1) {87; CHECK-LABEL: define i32 @test_smin_missing_nsw(88; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) {89; CHECK-NEXT: [[V0:%.*]] = tail call i32 @llvm.smin.i32(i32 [[ARG0]], i32 [[ARG1]])90; CHECK-NEXT: [[V1:%.*]] = add i32 [[ARG0]], 191; CHECK-NEXT: [[V2:%.*]] = tail call i32 @llvm.smin.i32(i32 [[V1]], i32 [[ARG1]])92; CHECK-NEXT: [[V3:%.*]] = sub i32 [[V2]], [[V0]]93; CHECK-NEXT: ret i32 [[V3]]94;95 %v0 = tail call i32 @llvm.smin.i32(i32 %arg0, i32 %arg1)96 %v1 = add i32 %arg0, 197 %v2 = tail call i32 @llvm.smin.i32(i32 %v1, i32 %arg1)98 %v3 = sub i32 %v2, %v099 ret i32 %v3100}101 102define i32 @test_umin_missing_nuw(i32 %arg0, i32 %arg1) {103; CHECK-LABEL: define i32 @test_umin_missing_nuw(104; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) {105; CHECK-NEXT: [[V0:%.*]] = tail call i32 @llvm.umin.i32(i32 [[ARG0]], i32 [[ARG1]])106; CHECK-NEXT: [[V1:%.*]] = add i32 [[ARG0]], 1107; CHECK-NEXT: [[V2:%.*]] = tail call i32 @llvm.umin.i32(i32 [[V1]], i32 [[ARG1]])108; CHECK-NEXT: [[V3:%.*]] = sub i32 [[V2]], [[V0]]109; CHECK-NEXT: ret i32 [[V3]]110;111 %v0 = tail call i32 @llvm.umin.i32(i32 %arg0, i32 %arg1)112 %v1 = add i32 %arg0, 1113 %v2 = tail call i32 @llvm.umin.i32(i32 %v1, i32 %arg1)114 %v3 = sub i32 %v2, %v0115 ret i32 %v3116}117 118@tmp = external global i32119 120define i32 @test_mismatched_operands(i32 %arg0, i32 %arg1) {121; CHECK-LABEL: define i32 @test_mismatched_operands(122; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) {123; CHECK-NEXT: [[TMP:%.*]] = load i32, ptr @tmp, align 4124; CHECK-NEXT: [[V0:%.*]] = tail call i32 @llvm.smin.i32(i32 [[ARG0]], i32 [[TMP]])125; CHECK-NEXT: [[V1:%.*]] = add nsw i32 [[ARG0]], 1126; CHECK-NEXT: [[V2:%.*]] = tail call i32 @llvm.smin.i32(i32 [[V1]], i32 [[ARG1]])127; CHECK-NEXT: [[V3:%.*]] = sub i32 [[V2]], [[V0]]128; CHECK-NEXT: ret i32 [[V3]]129;130 %tmp = load i32, ptr @tmp, align 4131 %v0 = tail call i32 @llvm.smin.i32(i32 %arg0, i32 %tmp)132 %v1 = add nsw i32 %arg0, 1133 %v2 = tail call i32 @llvm.smin.i32(i32 %v1, i32 %arg1)134 %v3 = sub i32 %v2, %v0135 ret i32 %v3136}137 138define i32 @test_disjoint_or(i32 %arg0, i32 %arg1) {139; CHECK-LABEL: define i32 @test_disjoint_or(140; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) {141; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[ARG0]], [[ARG1]]142; CHECK-NEXT: [[V3:%.*]] = zext i1 [[TMP1]] to i32143; CHECK-NEXT: ret i32 [[V3]]144;145 %v0 = tail call i32 @llvm.smin.i32(i32 %arg0, i32 %arg1)146 %v1 = or disjoint i32 %arg0, 1147 %v2 = tail call i32 @llvm.smin.i32(i32 %v1, i32 %arg1)148 %v3 = sub i32 %v2, %v0149 ret i32 %v3150}151