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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=instcombine -S | FileCheck %s3 4define i32 @foo(i32 %x, i32 %y) {5; CHECK-LABEL: @foo(6; CHECK-NEXT: [[A:%.*]] = and i32 [[X:%.*]], 77; CHECK-NEXT: [[B:%.*]] = and i32 [[Y:%.*]], 78; CHECK-NEXT: [[C:%.*]] = mul nuw nsw i32 [[A]], [[B]]9; CHECK-NEXT: [[D:%.*]] = shl nuw i32 [[C]], 2610; CHECK-NEXT: [[E:%.*]] = ashr exact i32 [[D]], 2611; CHECK-NEXT: ret i32 [[E]]12;13 %a = and i32 %x, 714 %b = and i32 %y, 715 %c = mul i32 %a, %b16 %d = shl i32 %c, 2617 %e = ashr i32 %d, 2618 ret i32 %e19}20 21; PR48683 'Quadratic Reciprocity' - and(mul(x,x),2) -> 022 23define i1 @PR48683(i32 %x) {24; CHECK-LABEL: @PR48683(25; CHECK-NEXT: ret i1 false26;27 %a = mul i32 %x, %x28 %b = and i32 %a, 229 %c = icmp ne i32 %b, 030 ret i1 %c31}32 33define <4 x i1> @PR48683_vec(<4 x i32> %x) {34; CHECK-LABEL: @PR48683_vec(35; CHECK-NEXT: ret <4 x i1> zeroinitializer36;37 %a = mul <4 x i32> %x, %x38 %b = and <4 x i32> %a, <i32 2, i32 2, i32 2, i32 2>39 %c = icmp ne <4 x i32> %b, zeroinitializer40 ret <4 x i1> %c41}42 43define <4 x i1> @PR48683_vec_undef(<4 x i32> %x) {44; CHECK-LABEL: @PR48683_vec_undef(45; CHECK-NEXT: [[A:%.*]] = mul <4 x i32> [[X:%.*]], [[X]]46; CHECK-NEXT: [[B:%.*]] = and <4 x i32> [[A]], <i32 2, i32 2, i32 2, i32 undef>47; CHECK-NEXT: [[C:%.*]] = icmp ne <4 x i32> [[B]], zeroinitializer48; CHECK-NEXT: ret <4 x i1> [[C]]49;50 %a = mul <4 x i32> %x, %x51 %b = and <4 x i32> %a, <i32 2, i32 2, i32 2, i32 undef>52 %c = icmp ne <4 x i32> %b, zeroinitializer53 ret <4 x i1> %c54}55 56; mul(x,x) - bit[1] is 0, but if demanding the other bits the source must not be undef57 58define i64 @combine_mul_self_demandedbits(i64 %x) {59; CHECK-LABEL: @combine_mul_self_demandedbits(60; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[X:%.*]], [[X]]61; CHECK-NEXT: [[TMP2:%.*]] = and i64 [[TMP1]], -362; CHECK-NEXT: ret i64 [[TMP2]]63;64 %1 = mul i64 %x, %x65 %2 = and i64 %1, -366 ret i64 %267}68 69define <4 x i32> @combine_mul_self_demandedbits_vector(<4 x i32> %x) {70; CHECK-LABEL: @combine_mul_self_demandedbits_vector(71; CHECK-NEXT: [[TMP1:%.*]] = freeze <4 x i32> [[X:%.*]]72; CHECK-NEXT: [[TMP2:%.*]] = mul <4 x i32> [[TMP1]], [[TMP1]]73; CHECK-NEXT: ret <4 x i32> [[TMP2]]74;75 %1 = freeze <4 x i32> %x76 %2 = mul <4 x i32> %1, %177 %3 = and <4 x i32> %2, <i32 -3, i32 -3, i32 -3, i32 -3>78 ret <4 x i32> %379}80 81define <vscale x 2 x i32> @combine_mul_self_demandedbits_vector2(<vscale x 2 x i32> %x) {82; CHECK-LABEL: @combine_mul_self_demandedbits_vector2(83; CHECK-NEXT: [[TMP1:%.*]] = freeze <vscale x 2 x i32> [[X:%.*]]84; CHECK-NEXT: [[TMP2:%.*]] = mul <vscale x 2 x i32> [[TMP1]], [[TMP1]]85; CHECK-NEXT: ret <vscale x 2 x i32> [[TMP2]]86;87 %1 = freeze <vscale x 2 x i32> %x88 %2 = mul <vscale x 2 x i32> %1, %189 %3 = and <vscale x 2 x i32> %2, splat (i32 -3)90 ret <vscale x 2 x i32> %391}92 93define i8 @one_demanded_bit(i8 %x) {94; CHECK-LABEL: @one_demanded_bit(95; CHECK-NEXT: [[M:%.*]] = shl i8 [[X:%.*]], 696; CHECK-NEXT: [[R:%.*]] = or i8 [[M]], -6597; CHECK-NEXT: ret i8 [[R]]98;99 %m = mul i8 %x, 192 ; 0b1100_0000100 %r = or i8 %m, 191 ; 0b1011_1111101 ret i8 %r102}103 104define <2 x i8> @one_demanded_bit_splat(<2 x i8> %x) {105; CHECK-LABEL: @one_demanded_bit_splat(106; CHECK-NEXT: [[M:%.*]] = shl <2 x i8> [[X:%.*]], splat (i8 5)107; CHECK-NEXT: [[R:%.*]] = and <2 x i8> [[M]], splat (i8 32)108; CHECK-NEXT: ret <2 x i8> [[R]]109;110 %m = mul <2 x i8> %x, <i8 160, i8 160> ; 0b1010_0000111 %r = and <2 x i8> %m, <i8 32, i8 32> ; 0b0010_0000112 ret <2 x i8> %r113}114 115define i67 @one_demanded_low_bit(i67 %x) {116; CHECK-LABEL: @one_demanded_low_bit(117; CHECK-NEXT: [[R:%.*]] = and i67 [[X:%.*]], 1118; CHECK-NEXT: ret i67 [[R]]119;120 %m = mul i67 %x, -63 ; any odd number will do121 %r = and i67 %m, 1122 ret i67 %r123}124 125define i33 @squared_one_demanded_low_bit(i33 %x) {126; CHECK-LABEL: @squared_one_demanded_low_bit(127; CHECK-NEXT: [[TMP1:%.*]] = and i33 [[X:%.*]], 1128; CHECK-NEXT: ret i33 [[TMP1]]129;130 %mul = mul i33 %x, %x131 %and = and i33 %mul, 1132 ret i33 %and133}134 135define <2 x i8> @squared_one_demanded_low_bit_splat(<2 x i8> %x) {136; CHECK-LABEL: @squared_one_demanded_low_bit_splat(137; CHECK-NEXT: [[AND:%.*]] = or <2 x i8> [[X:%.*]], splat (i8 -2)138; CHECK-NEXT: ret <2 x i8> [[AND]]139;140 %mul = mul <2 x i8> %x, %x141 %and = or <2 x i8> %mul, <i8 254, i8 254>142 ret <2 x i8> %and143}144 145define i33 @squared_demanded_2_low_bits(i33 %x) {146; CHECK-LABEL: @squared_demanded_2_low_bits(147; CHECK-NEXT: [[TMP1:%.*]] = and i33 [[X:%.*]], 1148; CHECK-NEXT: ret i33 [[TMP1]]149;150 %mul = mul i33 %x, %x151 %and = and i33 %mul, 3152 ret i33 %and153}154 155define <2 x i8> @squared_demanded_2_low_bits_splat(<2 x i8> %x) {156; CHECK-LABEL: @squared_demanded_2_low_bits_splat(157; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i8> [[X:%.*]], splat (i8 1)158; CHECK-NEXT: [[AND:%.*]] = or disjoint <2 x i8> [[TMP1]], splat (i8 -4)159; CHECK-NEXT: ret <2 x i8> [[AND]]160;161 %mul = mul <2 x i8> %x, %x162 %and = or <2 x i8> %mul, <i8 252, i8 252>163 ret <2 x i8> %and164}165 166; negative test167 168define i33 @squared_demanded_3_low_bits(i33 %x) {169; CHECK-LABEL: @squared_demanded_3_low_bits(170; CHECK-NEXT: [[MUL:%.*]] = mul i33 [[X:%.*]], [[X]]171; CHECK-NEXT: [[AND:%.*]] = and i33 [[MUL]], 7172; CHECK-NEXT: ret i33 [[AND]]173;174 %mul = mul i33 %x, %x175 %and = and i33 %mul, 7176 ret i33 %and177}178 179; Instcombine should be able to simplify mul operator.180 181; Scalar tests182define i64 @scalar_mul_bit_x0_y0(i64 %x, i64 %y) {183; CHECK-LABEL: @scalar_mul_bit_x0_y0(184; CHECK-NEXT: [[AND2:%.*]] = and i64 [[Y:%.*]], 1185; CHECK-NEXT: [[MUL:%.*]] = and i64 [[X:%.*]], [[AND2]]186; CHECK-NEXT: ret i64 [[MUL]]187;188 %and1 = and i64 %x, 1189 %and2 = and i64 %y, 1190 %mul = mul i64 %and1, %and2191 ret i64 %mul192}193 194declare void @use(i64)195 196define i64 @scalar_mul_bit_x0_y0_uses(i64 %x, i64 %y) {197; CHECK-LABEL: @scalar_mul_bit_x0_y0_uses(198; CHECK-NEXT: [[AND1:%.*]] = and i64 [[X:%.*]], 1199; CHECK-NEXT: call void @use(i64 [[AND1]])200; CHECK-NEXT: [[AND2:%.*]] = and i64 [[Y:%.*]], 1201; CHECK-NEXT: call void @use(i64 [[AND2]])202; CHECK-NEXT: [[MUL:%.*]] = and i64 [[X]], [[AND2]]203; CHECK-NEXT: ret i64 [[MUL]]204;205 %and1 = and i64 %x, 1206 call void @use(i64 %and1)207 %and2 = and i64 %y, 1208 call void @use(i64 %and2)209 %mul = mul i64 %and1, %and2210 ret i64 %mul211}212 213; Negative test214define i64 @scalar_mul_bit_x0_y1(i64 %x, i64 %y) {215; CHECK-LABEL: @scalar_mul_bit_x0_y1(216; CHECK-NEXT: [[AND2:%.*]] = and i64 [[Y:%.*]], 2217; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[X:%.*]] to i1218; CHECK-NEXT: [[MUL:%.*]] = select i1 [[TMP1]], i64 [[AND2]], i64 0219; CHECK-NEXT: ret i64 [[MUL]]220;221 %and1 = and i64 %x, 1222 %and2 = and i64 %y, 2223 %mul = mul i64 %and1, %and2224 ret i64 %mul225}226 227define i64 @scalar_mul_bit_x0_yC(i64 %x, i64 %y, i64 %c) {228; CHECK-LABEL: @scalar_mul_bit_x0_yC(229; CHECK-NEXT: [[AND2:%.*]] = and i64 [[Y:%.*]], [[C:%.*]]230; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[X:%.*]] to i1231; CHECK-NEXT: [[MUL:%.*]] = select i1 [[TMP1]], i64 [[AND2]], i64 0232; CHECK-NEXT: ret i64 [[MUL]]233;234 %and1 = and i64 %x, 1235 %and2 = and i64 %y, %c236 %mul = mul i64 %and1, %and2237 ret i64 %mul238}239 240; Vector tests241define <2 x i64> @vector_mul_bit_x0_y0(<2 x i64> %x, <2 x i64> %y) {242; CHECK-LABEL: @vector_mul_bit_x0_y0(243; CHECK-NEXT: [[AND2:%.*]] = and <2 x i64> [[Y:%.*]], splat (i64 1)244; CHECK-NEXT: [[MUL:%.*]] = and <2 x i64> [[X:%.*]], [[AND2]]245; CHECK-NEXT: ret <2 x i64> [[MUL]]246;247 %and1 = and <2 x i64> %x, <i64 1, i64 1>248 %and2 = and <2 x i64> %y, <i64 1, i64 1>249 %mul = mul <2 x i64> %and1, %and2250 ret <2 x i64> %mul251}252