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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=instcombine -S | FileCheck %s3 4; PR53610 - sub(0,and(lshr(X,C1),1)) --> ashr(shl(X,(BW-1)-C1),BW-1)5; PR53610 - sub(C2,and(lshr(X,C1),1)) --> add(ashr(shl(X,(BW-1)-C1),BW-1),C2)6 7define i8 @neg_mask1_lshr(i8 %a0) {8; CHECK-LABEL: @neg_mask1_lshr(9; CHECK-NEXT: [[TMP1:%.*]] = shl i8 [[A0:%.*]], 410; CHECK-NEXT: [[TMP2:%.*]] = ashr i8 [[TMP1]], 711; CHECK-NEXT: ret i8 [[TMP2]]12;13 %shift = lshr i8 %a0, 314 %mask = and i8 %shift, 115 %neg = sub i8 0, %mask16 ret i8 %neg17}18 19define i8 @sub_mask1_lshr(i8 %a0) {20; CHECK-LABEL: @sub_mask1_lshr(21; CHECK-NEXT: [[TMP1:%.*]] = shl i8 [[A0:%.*]], 622; CHECK-NEXT: [[TMP2:%.*]] = ashr i8 [[TMP1]], 723; CHECK-NEXT: [[NEG:%.*]] = add nsw i8 [[TMP2]], 1024; CHECK-NEXT: ret i8 [[NEG]]25;26 %shift = lshr i8 %a0, 127 %mask = and i8 %shift, 128 %neg = sub i8 10, %mask29 ret i8 %neg30}31 32define <4 x i32> @neg_mask1_lshr_vector_uniform(<4 x i32> %a0) {33; CHECK-LABEL: @neg_mask1_lshr_vector_uniform(34; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i32> [[A0:%.*]], splat (i32 28)35; CHECK-NEXT: [[TMP2:%.*]] = ashr <4 x i32> [[TMP1]], splat (i32 31)36; CHECK-NEXT: ret <4 x i32> [[TMP2]]37;38 %shift = lshr <4 x i32> %a0, <i32 3, i32 3, i32 3, i32 3>39 %mask = and <4 x i32> %shift, <i32 1, i32 1, i32 1, i32 1>40 %neg = sub <4 x i32> zeroinitializer, %mask41 ret <4 x i32> %neg42}43 44define <4 x i32> @neg_mask1_lshr_vector_nonuniform(<4 x i32> %a0) {45; CHECK-LABEL: @neg_mask1_lshr_vector_nonuniform(46; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i32> [[A0:%.*]], <i32 28, i32 27, i32 26, i32 25>47; CHECK-NEXT: [[TMP2:%.*]] = ashr <4 x i32> [[TMP1]], splat (i32 31)48; CHECK-NEXT: ret <4 x i32> [[TMP2]]49;50 %shift = lshr <4 x i32> %a0, <i32 3, i32 4, i32 5, i32 6>51 %mask = and <4 x i32> %shift, <i32 1, i32 1, i32 1, i32 1>52 %neg = sub <4 x i32> zeroinitializer, %mask53 ret <4 x i32> %neg54}55 56define <4 x i32> @sub_mask1_lshr_vector_nonuniform(<4 x i32> %a0) {57; CHECK-LABEL: @sub_mask1_lshr_vector_nonuniform(58; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i32> [[A0:%.*]], <i32 28, i32 27, i32 26, i32 25>59; CHECK-NEXT: [[TMP2:%.*]] = ashr <4 x i32> [[TMP1]], splat (i32 31)60; CHECK-NEXT: [[NEG:%.*]] = add nsw <4 x i32> [[TMP2]], <i32 5, i32 0, i32 -1, i32 65556>61; CHECK-NEXT: ret <4 x i32> [[NEG]]62;63 %shift = lshr <4 x i32> %a0, <i32 3, i32 4, i32 5, i32 6>64 %mask = and <4 x i32> %shift, <i32 1, i32 1, i32 1, i32 1>65 %neg = sub <4 x i32> <i32 5, i32 0, i32 -1, i32 65556>, %mask66 ret <4 x i32> %neg67}68 69define i8 @sub_mask1_trunc_lshr(i64 %a0) {70; CHECK-LABEL: @sub_mask1_trunc_lshr(71; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[A0:%.*]], 4872; CHECK-NEXT: [[TMP2:%.*]] = ashr i64 [[TMP1]], 6373; CHECK-NEXT: [[TMP3:%.*]] = trunc nsw i64 [[TMP2]] to i874; CHECK-NEXT: [[NEG:%.*]] = add nsw i8 [[TMP3]], 1075; CHECK-NEXT: ret i8 [[NEG]]76;77 %shift = lshr i64 %a0, 1578 %trunc = trunc i64 %shift to i879 %mask = and i8 %trunc, 180 %neg = sub i8 10, %mask81 ret i8 %neg82}83 84define i32 @sub_sext_mask1_trunc_lshr(i64 %a0) {85; CHECK-LABEL: @sub_sext_mask1_trunc_lshr(86; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[A0:%.*]], 4887; CHECK-NEXT: [[TMP2:%.*]] = ashr i64 [[TMP1]], 6388; CHECK-NEXT: [[TMP3:%.*]] = trunc nsw i64 [[TMP2]] to i889; CHECK-NEXT: [[NARROW:%.*]] = add nsw i8 [[TMP3]], 1090; CHECK-NEXT: [[NEG:%.*]] = zext i8 [[NARROW]] to i3291; CHECK-NEXT: ret i32 [[NEG]]92;93 %shift = lshr i64 %a0, 1594 %trunc = trunc i64 %shift to i895 %mask = and i8 %trunc, 196 %sext = sext i8 %mask to i3297 %neg = sub i32 10, %sext98 ret i32 %neg99}100 101define i32 @sub_zext_trunc_lshr(i64 %a0) {102; CHECK-LABEL: @sub_zext_trunc_lshr(103; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[A0:%.*]] to i32104; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], 16105; CHECK-NEXT: [[TMP3:%.*]] = ashr i32 [[TMP2]], 31106; CHECK-NEXT: [[NEG:%.*]] = add nsw i32 [[TMP3]], 10107; CHECK-NEXT: ret i32 [[NEG]]108;109 %shift = lshr i64 %a0, 15110 %trunc = trunc i64 %shift to i1111 %sext = zext i1 %trunc to i32112 %neg = sub i32 10, %sext113 ret i32 %neg114}115 116; Negative Test - wrong mask117define i8 @neg_mask2_lshr(i8 %a0) {118; CHECK-LABEL: @neg_mask2_lshr(119; CHECK-NEXT: [[SHIFT:%.*]] = lshr i8 [[A0:%.*]], 3120; CHECK-NEXT: [[MASK:%.*]] = and i8 [[SHIFT]], 2121; CHECK-NEXT: [[NEG:%.*]] = sub nsw i8 0, [[MASK]]122; CHECK-NEXT: ret i8 [[NEG]]123;124 %shift = lshr i8 %a0, 3125 %mask = and i8 %shift, 2126 %neg = sub i8 0, %mask127 ret i8 %neg128}129 130; Negative Test - bad shift amount131define i8 @neg_mask2_lshr_outofbounds(i8 %a0) {132; CHECK-LABEL: @neg_mask2_lshr_outofbounds(133; CHECK-NEXT: ret i8 poison134;135 %shift = lshr i8 %a0, 8136 %mask = and i8 %shift, 2137 %neg = sub i8 0, %mask138 ret i8 %neg139}140 141; Negative Test - non-constant shift amount142define <2 x i32> @neg_mask1_lshr_vector_var(<2 x i32> %a0, <2 x i32> %a1) {143; CHECK-LABEL: @neg_mask1_lshr_vector_var(144; CHECK-NEXT: [[SHIFT:%.*]] = lshr <2 x i32> [[A0:%.*]], [[A1:%.*]]145; CHECK-NEXT: [[MASK:%.*]] = and <2 x i32> [[SHIFT]], splat (i32 1)146; CHECK-NEXT: [[NEG:%.*]] = sub nsw <2 x i32> zeroinitializer, [[MASK]]147; CHECK-NEXT: ret <2 x i32> [[NEG]]148;149 %shift = lshr <2 x i32> %a0, %a1150 %mask = and <2 x i32> %shift, <i32 1, i32 1>151 %neg = sub <2 x i32> zeroinitializer, %mask152 ret <2 x i32> %neg153}154 155; Extra Use - mask156define i8 @neg_mask1_lshr_extrause_mask(i8 %a0) {157; CHECK-LABEL: @neg_mask1_lshr_extrause_mask(158; CHECK-NEXT: [[SHIFT:%.*]] = lshr i8 [[A0:%.*]], 3159; CHECK-NEXT: [[MASK:%.*]] = and i8 [[SHIFT]], 1160; CHECK-NEXT: [[NEG:%.*]] = sub nsw i8 0, [[MASK]]161; CHECK-NEXT: call void @usei8(i8 [[MASK]])162; CHECK-NEXT: ret i8 [[NEG]]163;164 %shift = lshr i8 %a0, 3165 %mask = and i8 %shift, 1166 %neg = sub i8 0, %mask167 call void @usei8(i8 %mask)168 ret i8 %neg169}170 171; Extra Use - shift172define <2 x i32> @neg_mask1_lshr_extrause_lshr(<2 x i32> %a0) {173; CHECK-LABEL: @neg_mask1_lshr_extrause_lshr(174; CHECK-NEXT: [[SHIFT:%.*]] = lshr <2 x i32> [[A0:%.*]], splat (i32 3)175; CHECK-NEXT: [[MASK:%.*]] = and <2 x i32> [[SHIFT]], splat (i32 1)176; CHECK-NEXT: [[NEG:%.*]] = sub nsw <2 x i32> zeroinitializer, [[MASK]]177; CHECK-NEXT: call void @usev2i32(<2 x i32> [[SHIFT]])178; CHECK-NEXT: ret <2 x i32> [[NEG]]179;180 %shift = lshr <2 x i32> %a0, <i32 3, i32 3>181 %mask = and <2 x i32> %shift, <i32 1, i32 1>182 %neg = sub <2 x i32> zeroinitializer, %mask183 call void @usev2i32(<2 x i32> %shift)184 ret <2 x i32> %neg185}186 187define i32 @neg_signbit(i8 %x) {188; CHECK-LABEL: @neg_signbit(189; CHECK-NEXT: [[TMP1:%.*]] = ashr i8 [[X:%.*]], 7190; CHECK-NEXT: [[TMP2:%.*]] = sext i8 [[TMP1]] to i32191; CHECK-NEXT: ret i32 [[TMP2]]192;193 %s = lshr i8 %x, 7194 %z = zext i8 %s to i32195 %r = sub i32 0, %z196 ret i32 %r197}198 199define <2 x i64> @neg_signbit_use1(<2 x i32> %x) {200; CHECK-LABEL: @neg_signbit_use1(201; CHECK-NEXT: [[S:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 31, i32 poison>202; CHECK-NEXT: call void @usev2i32(<2 x i32> [[S]])203; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i32> [[X]], splat (i32 31)204; CHECK-NEXT: [[TMP2:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>205; CHECK-NEXT: ret <2 x i64> [[TMP2]]206;207 %s = lshr <2 x i32> %x, <i32 31, i32 poison>208 call void @usev2i32(<2 x i32> %s)209 %z = zext <2 x i32> %s to <2 x i64>210 %r = sub <2 x i64> zeroinitializer, %z211 ret <2 x i64> %r212}213 214; negative test - extra use215 216define i8 @neg_signbit_use2(i5 %x) {217; CHECK-LABEL: @neg_signbit_use2(218; CHECK-NEXT: [[S:%.*]] = lshr i5 [[X:%.*]], 4219; CHECK-NEXT: [[Z:%.*]] = zext nneg i5 [[S]] to i8220; CHECK-NEXT: call void @usei8(i8 [[Z]])221; CHECK-NEXT: [[R:%.*]] = sub nsw i8 0, [[Z]]222; CHECK-NEXT: ret i8 [[R]]223;224 %s = lshr i5 %x, 4225 %z = zext i5 %s to i8226 call void @usei8(i8 %z)227 %r = sub i8 0, %z228 ret i8 %r229}230 231; negative test - not negation232; TODO: reduce to zext(x s> -1)233 234define i32 @neg_not_signbit1(i8 %x) {235; CHECK-LABEL: @neg_not_signbit1(236; CHECK-NEXT: [[ISNOTNEG:%.*]] = icmp sgt i8 [[X:%.*]], -1237; CHECK-NEXT: [[R:%.*]] = zext i1 [[ISNOTNEG]] to i32238; CHECK-NEXT: ret i32 [[R]]239;240 %s = lshr i8 %x, 7241 %z = zext i8 %s to i32242 %r = sub i32 1, %z243 ret i32 %r244}245 246; negative test - wrong shift amount247 248define i32 @neg_not_signbit2(i8 %x) {249; CHECK-LABEL: @neg_not_signbit2(250; CHECK-NEXT: [[S:%.*]] = lshr i8 [[X:%.*]], 6251; CHECK-NEXT: [[Z:%.*]] = zext nneg i8 [[S]] to i32252; CHECK-NEXT: [[R:%.*]] = sub nsw i32 0, [[Z]]253; CHECK-NEXT: ret i32 [[R]]254;255 %s = lshr i8 %x, 6256 %z = zext i8 %s to i32257 %r = sub i32 0, %z258 ret i32 %r259}260 261; negative test - wrong shift opcode262 263define i32 @neg_not_signbit3(i8 %x) {264; CHECK-LABEL: @neg_not_signbit3(265; CHECK-NEXT: [[S:%.*]] = ashr i8 [[X:%.*]], 7266; CHECK-NEXT: [[Z:%.*]] = zext i8 [[S]] to i32267; CHECK-NEXT: [[R:%.*]] = sub nsw i32 0, [[Z]]268; CHECK-NEXT: ret i32 [[R]]269;270 %s = ashr i8 %x, 7271 %z = zext i8 %s to i32272 %r = sub i32 0, %z273 ret i32 %r274}275 276define i32 @neg_mask(i32 %x, i16 %y) {277; CHECK-LABEL: @neg_mask(278; CHECK-NEXT: [[S:%.*]] = sext i16 [[Y:%.*]] to i32279; CHECK-NEXT: [[SUB1:%.*]] = sub nsw i32 [[X:%.*]], [[S]]280; CHECK-NEXT: [[ISNEG:%.*]] = icmp slt i16 [[Y]], 0281; CHECK-NEXT: [[R:%.*]] = select i1 [[ISNEG]], i32 [[SUB1]], i32 0282; CHECK-NEXT: ret i32 [[R]]283;284 %s = sext i16 %y to i32285 %sub1 = sub nsw i32 %x, %s286 %sh = lshr i16 %y, 15287 %z = zext i16 %sh to i32288 %sub2 = sub nsw i32 0, %z289 %r = and i32 %sub1, %sub2290 ret i32 %r291}292 293define i32 @neg_mask_const(i16 %x) {294; CHECK-LABEL: @neg_mask_const(295; CHECK-NEXT: [[S:%.*]] = sext i16 [[X:%.*]] to i32296; CHECK-NEXT: [[SUB1:%.*]] = sub nsw i32 1000, [[S]]297; CHECK-NEXT: [[ISNEG:%.*]] = icmp slt i16 [[X]], 0298; CHECK-NEXT: [[R:%.*]] = select i1 [[ISNEG]], i32 [[SUB1]], i32 0299; CHECK-NEXT: ret i32 [[R]]300;301 %s = sext i16 %x to i32302 %sub1 = sub nsw i32 1000, %s303 %sh = lshr i16 %x, 15304 %z = zext i16 %sh to i32305 %sub2 = sub nsw i32 0, %z306 %r = and i32 %sub1, %sub2307 ret i32 %r308}309 310declare void @usei8(i8)311declare void @usev2i32(<2 x i32>)312