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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=instcombine -S | FileCheck %s3 4define i1 @and_consts(i32 %k, i32 %c1, i32 %c2) {5; CHECK-LABEL: @and_consts(6; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[K:%.*]], 127; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP1]], 128; CHECK-NEXT: ret i1 [[OR]]9;10 %t1 = and i32 4, %k11 %t2 = icmp eq i32 %t1, 012 %t5 = and i32 8, %k13 %t6 = icmp eq i32 %t5, 014 %or = or i1 %t2, %t615 ret i1 %or16}17 18define i1 @and_consts_logical(i32 %k, i32 %c1, i32 %c2) {19; CHECK-LABEL: @and_consts_logical(20; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[K:%.*]], 1221; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP1]], 1222; CHECK-NEXT: ret i1 [[OR]]23;24 %t1 = and i32 4, %k25 %t2 = icmp eq i32 %t1, 026 %t5 = and i32 8, %k27 %t6 = icmp eq i32 %t5, 028 %or = select i1 %t2, i1 true, i1 %t629 ret i1 %or30}31 32define <2 x i1> @and_consts_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32> %c2) {33; CHECK-LABEL: @and_consts_vector(34; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[K:%.*]], splat (i32 12)35; CHECK-NEXT: [[OR:%.*]] = icmp ne <2 x i32> [[TMP1]], splat (i32 12)36; CHECK-NEXT: ret <2 x i1> [[OR]]37;38 %t1 = and <2 x i32> <i32 4, i32 4>, %k39 %t2 = icmp eq <2 x i32> %t1, zeroinitializer40 %t5 = and <2 x i32> <i32 8, i32 8>, %k41 %t6 = icmp eq <2 x i32> %t5, zeroinitializer42 %or = or <2 x i1> %t2, %t643 ret <2 x i1> %or44}45 46define i1 @foo1_and(i32 %k, i32 %c1, i32 %c2) {47; CHECK-LABEL: @foo1_and(48; CHECK-NEXT: [[T:%.*]] = shl nuw i32 1, [[C1:%.*]]49; CHECK-NEXT: [[T4:%.*]] = shl nuw i32 1, [[C2:%.*]]50; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]]51; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[K:%.*]], [[TMP1]]52; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]53; CHECK-NEXT: ret i1 [[OR]]54;55 %t = shl i32 1, %c156 %t4 = shl i32 1, %c257 %t1 = and i32 %t, %k58 %t2 = icmp eq i32 %t1, 059 %t5 = and i32 %t4, %k60 %t6 = icmp eq i32 %t5, 061 %or = or i1 %t2, %t662 ret i1 %or63}64 65define i1 @foo1_and_logical(i32 %k, i32 %c1, i32 %c2) {66; CHECK-LABEL: @foo1_and_logical(67; CHECK-NEXT: [[T:%.*]] = shl nuw i32 1, [[C1:%.*]]68; CHECK-NEXT: [[T4:%.*]] = shl nuw i32 1, [[C2:%.*]]69; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T4]]70; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T]], [[TMP1]]71; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[K:%.*]], [[TMP2]]72; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]73; CHECK-NEXT: ret i1 [[OR]]74;75 %t = shl i32 1, %c176 %t4 = shl i32 1, %c277 %t1 = and i32 %t, %k78 %t2 = icmp eq i32 %t1, 079 %t5 = and i32 %t4, %k80 %t6 = icmp eq i32 %t5, 081 %or = select i1 %t2, i1 true, i1 %t682 ret i1 %or83}84 85define <2 x i1> @foo1_and_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32> %c2) {86; CHECK-LABEL: @foo1_and_vector(87; CHECK-NEXT: [[T:%.*]] = shl nuw <2 x i32> splat (i32 1), [[C1:%.*]]88; CHECK-NEXT: [[T4:%.*]] = shl nuw <2 x i32> splat (i32 1), [[C2:%.*]]89; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[T]], [[T4]]90; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[K:%.*]], [[TMP1]]91; CHECK-NEXT: [[OR:%.*]] = icmp ne <2 x i32> [[TMP2]], [[TMP1]]92; CHECK-NEXT: ret <2 x i1> [[OR]]93;94 %t = shl <2 x i32> <i32 1, i32 1>, %c195 %t4 = shl <2 x i32> <i32 1, i32 1>, %c296 %t1 = and <2 x i32> %t, %k97 %t2 = icmp eq <2 x i32> %t1, zeroinitializer98 %t5 = and <2 x i32> %t4, %k99 %t6 = icmp eq <2 x i32> %t5, zeroinitializer100 %or = or <2 x i1> %t2, %t6101 ret <2 x i1> %or102}103 104; Same as above but with operands commuted one of the ands, but not the other.105define i1 @foo1_and_commuted(i32 %k, i32 %c1, i32 %c2) {106; CHECK-LABEL: @foo1_and_commuted(107; CHECK-NEXT: [[K2:%.*]] = mul i32 [[K:%.*]], [[K]]108; CHECK-NEXT: [[T:%.*]] = shl nuw i32 1, [[C1:%.*]]109; CHECK-NEXT: [[T4:%.*]] = shl nuw i32 1, [[C2:%.*]]110; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]]111; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[K2]], [[TMP1]]112; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]113; CHECK-NEXT: ret i1 [[OR]]114;115 %k2 = mul i32 %k, %k ; to trick the complexity sorting116 %t = shl i32 1, %c1117 %t4 = shl i32 1, %c2118 %t1 = and i32 %k2, %t119 %t2 = icmp eq i32 %t1, 0120 %t5 = and i32 %t4, %k2121 %t6 = icmp eq i32 %t5, 0122 %or = or i1 %t2, %t6123 ret i1 %or124}125 126define i1 @foo1_and_commuted_logical(i32 %k, i32 %c1, i32 %c2) {127; CHECK-LABEL: @foo1_and_commuted_logical(128; CHECK-NEXT: [[K2:%.*]] = mul i32 [[K:%.*]], [[K]]129; CHECK-NEXT: [[T:%.*]] = shl nuw i32 1, [[C1:%.*]]130; CHECK-NEXT: [[T4:%.*]] = shl nuw i32 1, [[C2:%.*]]131; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T4]]132; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T]], [[TMP1]]133; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[K2]], [[TMP2]]134; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]135; CHECK-NEXT: ret i1 [[OR]]136;137 %k2 = mul i32 %k, %k ; to trick the complexity sorting138 %t = shl i32 1, %c1139 %t4 = shl i32 1, %c2140 %t1 = and i32 %k2, %t141 %t2 = icmp eq i32 %t1, 0142 %t5 = and i32 %t4, %k2143 %t6 = icmp eq i32 %t5, 0144 %or = select i1 %t2, i1 true, i1 %t6145 ret i1 %or146}147 148define <2 x i1> @foo1_and_commuted_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32> %c2) {149; CHECK-LABEL: @foo1_and_commuted_vector(150; CHECK-NEXT: [[K2:%.*]] = mul <2 x i32> [[K:%.*]], [[K]]151; CHECK-NEXT: [[T:%.*]] = shl nuw <2 x i32> splat (i32 1), [[C1:%.*]]152; CHECK-NEXT: [[T4:%.*]] = shl nuw <2 x i32> splat (i32 1), [[C2:%.*]]153; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[T]], [[T4]]154; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[K2]], [[TMP1]]155; CHECK-NEXT: [[OR:%.*]] = icmp ne <2 x i32> [[TMP2]], [[TMP1]]156; CHECK-NEXT: ret <2 x i1> [[OR]]157;158 %k2 = mul <2 x i32> %k, %k ; to trick the complexity sorting159 %t = shl <2 x i32> <i32 1, i32 1>, %c1160 %t4 = shl <2 x i32> <i32 1, i32 1>, %c2161 %t1 = and <2 x i32> %k2, %t162 %t2 = icmp eq <2 x i32> %t1, zeroinitializer163 %t5 = and <2 x i32> %t4, %k2164 %t6 = icmp eq <2 x i32> %t5, zeroinitializer165 %or = or <2 x i1> %t2, %t6166 ret <2 x i1> %or167}168 169define i1 @or_consts(i32 %k, i32 %c1, i32 %c2) {170; CHECK-LABEL: @or_consts(171; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[K:%.*]], 12172; CHECK-NEXT: [[OR:%.*]] = icmp eq i32 [[TMP1]], 12173; CHECK-NEXT: ret i1 [[OR]]174;175 %t1 = and i32 4, %k176 %t2 = icmp ne i32 %t1, 0177 %t5 = and i32 8, %k178 %t6 = icmp ne i32 %t5, 0179 %or = and i1 %t2, %t6180 ret i1 %or181}182 183define i1 @or_consts_logical(i32 %k, i32 %c1, i32 %c2) {184; CHECK-LABEL: @or_consts_logical(185; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[K:%.*]], 12186; CHECK-NEXT: [[OR:%.*]] = icmp eq i32 [[TMP1]], 12187; CHECK-NEXT: ret i1 [[OR]]188;189 %t1 = and i32 4, %k190 %t2 = icmp ne i32 %t1, 0191 %t5 = and i32 8, %k192 %t6 = icmp ne i32 %t5, 0193 %or = select i1 %t2, i1 %t6, i1 false194 ret i1 %or195}196 197define <2 x i1> @or_consts_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32> %c2) {198; CHECK-LABEL: @or_consts_vector(199; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[K:%.*]], splat (i32 12)200; CHECK-NEXT: [[OR:%.*]] = icmp eq <2 x i32> [[TMP1]], splat (i32 12)201; CHECK-NEXT: ret <2 x i1> [[OR]]202;203 %t1 = and <2 x i32> <i32 4, i32 4>, %k204 %t2 = icmp ne <2 x i32> %t1, zeroinitializer205 %t5 = and <2 x i32> <i32 8, i32 8>, %k206 %t6 = icmp ne <2 x i32> %t5, zeroinitializer207 %or = and <2 x i1> %t2, %t6208 ret <2 x i1> %or209}210 211define i1 @foo1_or(i32 %k, i32 %c1, i32 %c2) {212; CHECK-LABEL: @foo1_or(213; CHECK-NEXT: [[T:%.*]] = shl nuw i32 1, [[C1:%.*]]214; CHECK-NEXT: [[T4:%.*]] = shl nuw i32 1, [[C2:%.*]]215; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]]216; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[K:%.*]], [[TMP1]]217; CHECK-NEXT: [[OR:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]]218; CHECK-NEXT: ret i1 [[OR]]219;220 %t = shl i32 1, %c1221 %t4 = shl i32 1, %c2222 %t1 = and i32 %t, %k223 %t2 = icmp ne i32 %t1, 0224 %t5 = and i32 %t4, %k225 %t6 = icmp ne i32 %t5, 0226 %or = and i1 %t2, %t6227 ret i1 %or228}229 230define i1 @foo1_or_logical(i32 %k, i32 %c1, i32 %c2) {231; CHECK-LABEL: @foo1_or_logical(232; CHECK-NEXT: [[T:%.*]] = shl nuw i32 1, [[C1:%.*]]233; CHECK-NEXT: [[T4:%.*]] = shl nuw i32 1, [[C2:%.*]]234; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T4]]235; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T]], [[TMP1]]236; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[K:%.*]], [[TMP2]]237; CHECK-NEXT: [[OR:%.*]] = icmp eq i32 [[TMP3]], [[TMP2]]238; CHECK-NEXT: ret i1 [[OR]]239;240 %t = shl i32 1, %c1241 %t4 = shl i32 1, %c2242 %t1 = and i32 %t, %k243 %t2 = icmp ne i32 %t1, 0244 %t5 = and i32 %t4, %k245 %t6 = icmp ne i32 %t5, 0246 %or = select i1 %t2, i1 %t6, i1 false247 ret i1 %or248}249 250define <2 x i1> @foo1_or_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32> %c2) {251; CHECK-LABEL: @foo1_or_vector(252; CHECK-NEXT: [[T:%.*]] = shl nuw <2 x i32> splat (i32 1), [[C1:%.*]]253; CHECK-NEXT: [[T4:%.*]] = shl nuw <2 x i32> splat (i32 1), [[C2:%.*]]254; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[T]], [[T4]]255; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[K:%.*]], [[TMP1]]256; CHECK-NEXT: [[OR:%.*]] = icmp eq <2 x i32> [[TMP2]], [[TMP1]]257; CHECK-NEXT: ret <2 x i1> [[OR]]258;259 %t = shl <2 x i32> <i32 1, i32 1>, %c1260 %t4 = shl <2 x i32> <i32 1, i32 1>, %c2261 %t1 = and <2 x i32> %t, %k262 %t2 = icmp ne <2 x i32> %t1, zeroinitializer263 %t5 = and <2 x i32> %t4, %k264 %t6 = icmp ne <2 x i32> %t5, zeroinitializer265 %or = and <2 x i1> %t2, %t6266 ret <2 x i1> %or267}268 269; Same as above but with operands commuted one of the ors, but not the other.270define i1 @foo1_or_commuted(i32 %k, i32 %c1, i32 %c2) {271; CHECK-LABEL: @foo1_or_commuted(272; CHECK-NEXT: [[K2:%.*]] = mul i32 [[K:%.*]], [[K]]273; CHECK-NEXT: [[T:%.*]] = shl nuw i32 1, [[C1:%.*]]274; CHECK-NEXT: [[T4:%.*]] = shl nuw i32 1, [[C2:%.*]]275; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]]276; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[K2]], [[TMP1]]277; CHECK-NEXT: [[OR:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]]278; CHECK-NEXT: ret i1 [[OR]]279;280 %k2 = mul i32 %k, %k ; to trick the complexity sorting281 %t = shl i32 1, %c1282 %t4 = shl i32 1, %c2283 %t1 = and i32 %k2, %t284 %t2 = icmp ne i32 %t1, 0285 %t5 = and i32 %t4, %k2286 %t6 = icmp ne i32 %t5, 0287 %or = and i1 %t2, %t6288 ret i1 %or289}290 291define i1 @foo1_or_commuted_logical(i32 %k, i32 %c1, i32 %c2) {292; CHECK-LABEL: @foo1_or_commuted_logical(293; CHECK-NEXT: [[K2:%.*]] = mul i32 [[K:%.*]], [[K]]294; CHECK-NEXT: [[T:%.*]] = shl nuw i32 1, [[C1:%.*]]295; CHECK-NEXT: [[T4:%.*]] = shl nuw i32 1, [[C2:%.*]]296; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T4]]297; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T]], [[TMP1]]298; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[K2]], [[TMP2]]299; CHECK-NEXT: [[OR:%.*]] = icmp eq i32 [[TMP3]], [[TMP2]]300; CHECK-NEXT: ret i1 [[OR]]301;302 %k2 = mul i32 %k, %k ; to trick the complexity sorting303 %t = shl i32 1, %c1304 %t4 = shl i32 1, %c2305 %t1 = and i32 %k2, %t306 %t2 = icmp ne i32 %t1, 0307 %t5 = and i32 %t4, %k2308 %t6 = icmp ne i32 %t5, 0309 %or = select i1 %t2, i1 %t6, i1 false310 ret i1 %or311}312 313define <2 x i1> @foo1_or_commuted_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32> %c2) {314; CHECK-LABEL: @foo1_or_commuted_vector(315; CHECK-NEXT: [[K2:%.*]] = mul <2 x i32> [[K:%.*]], [[K]]316; CHECK-NEXT: [[T:%.*]] = shl nuw <2 x i32> splat (i32 1), [[C1:%.*]]317; CHECK-NEXT: [[T4:%.*]] = shl nuw <2 x i32> splat (i32 1), [[C2:%.*]]318; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[T]], [[T4]]319; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[K2]], [[TMP1]]320; CHECK-NEXT: [[OR:%.*]] = icmp eq <2 x i32> [[TMP2]], [[TMP1]]321; CHECK-NEXT: ret <2 x i1> [[OR]]322;323 %k2 = mul <2 x i32> %k, %k ; to trick the complexity sorting324 %t = shl <2 x i32> <i32 1, i32 1>, %c1325 %t4 = shl <2 x i32> <i32 1, i32 1>, %c2326 %t1 = and <2 x i32> %k2, %t327 %t2 = icmp ne <2 x i32> %t1, zeroinitializer328 %t5 = and <2 x i32> %t4, %k2329 %t6 = icmp ne <2 x i32> %t5, zeroinitializer330 %or = and <2 x i1> %t2, %t6331 ret <2 x i1> %or332}333 334define i1 @foo1_and_signbit_lshr(i32 %k, i32 %c1, i32 %c2) {335; CHECK-LABEL: @foo1_and_signbit_lshr(336; CHECK-NEXT: [[T:%.*]] = shl nuw i32 1, [[C1:%.*]]337; CHECK-NEXT: [[T4:%.*]] = lshr exact i32 -2147483648, [[C2:%.*]]338; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]]339; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[K:%.*]], [[TMP1]]340; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]341; CHECK-NEXT: ret i1 [[OR]]342;343 %t = shl i32 1, %c1344 %t4 = lshr i32 -2147483648, %c2345 %t1 = and i32 %t, %k346 %t2 = icmp eq i32 %t1, 0347 %t5 = and i32 %t4, %k348 %t6 = icmp eq i32 %t5, 0349 %or = or i1 %t2, %t6350 ret i1 %or351}352 353define i1 @foo1_and_signbit_lshr_logical(i32 %k, i32 %c1, i32 %c2) {354; CHECK-LABEL: @foo1_and_signbit_lshr_logical(355; CHECK-NEXT: [[T:%.*]] = shl nuw i32 1, [[C1:%.*]]356; CHECK-NEXT: [[T4:%.*]] = lshr exact i32 -2147483648, [[C2:%.*]]357; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T4]]358; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T]], [[TMP1]]359; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[K:%.*]], [[TMP2]]360; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]361; CHECK-NEXT: ret i1 [[OR]]362;363 %t = shl i32 1, %c1364 %t4 = lshr i32 -2147483648, %c2365 %t1 = and i32 %t, %k366 %t2 = icmp eq i32 %t1, 0367 %t5 = and i32 %t4, %k368 %t6 = icmp eq i32 %t5, 0369 %or = select i1 %t2, i1 true, i1 %t6370 ret i1 %or371}372 373define <2 x i1> @foo1_and_signbit_lshr_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32> %c2) {374; CHECK-LABEL: @foo1_and_signbit_lshr_vector(375; CHECK-NEXT: [[T:%.*]] = shl nuw <2 x i32> splat (i32 1), [[C1:%.*]]376; CHECK-NEXT: [[T4:%.*]] = lshr exact <2 x i32> splat (i32 -2147483648), [[C2:%.*]]377; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[T]], [[T4]]378; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[K:%.*]], [[TMP1]]379; CHECK-NEXT: [[OR:%.*]] = icmp ne <2 x i32> [[TMP2]], [[TMP1]]380; CHECK-NEXT: ret <2 x i1> [[OR]]381;382 %t = shl <2 x i32> <i32 1, i32 1>, %c1383 %t4 = lshr <2 x i32> <i32 -2147483648, i32 -2147483648>, %c2384 %t1 = and <2 x i32> %t, %k385 %t2 = icmp eq <2 x i32> %t1, zeroinitializer386 %t5 = and <2 x i32> %t4, %k387 %t6 = icmp eq <2 x i32> %t5, zeroinitializer388 %or = or <2 x i1> %t2, %t6389 ret <2 x i1> %or390}391 392define i1 @foo1_or_signbit_lshr(i32 %k, i32 %c1, i32 %c2) {393; CHECK-LABEL: @foo1_or_signbit_lshr(394; CHECK-NEXT: [[T:%.*]] = shl nuw i32 1, [[C1:%.*]]395; CHECK-NEXT: [[T4:%.*]] = lshr exact i32 -2147483648, [[C2:%.*]]396; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]]397; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[K:%.*]], [[TMP1]]398; CHECK-NEXT: [[OR:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]]399; CHECK-NEXT: ret i1 [[OR]]400;401 %t = shl i32 1, %c1402 %t4 = lshr i32 -2147483648, %c2403 %t1 = and i32 %t, %k404 %t2 = icmp ne i32 %t1, 0405 %t5 = and i32 %t4, %k406 %t6 = icmp ne i32 %t5, 0407 %or = and i1 %t2, %t6408 ret i1 %or409}410 411define i1 @foo1_or_signbit_lshr_logical(i32 %k, i32 %c1, i32 %c2) {412; CHECK-LABEL: @foo1_or_signbit_lshr_logical(413; CHECK-NEXT: [[T:%.*]] = shl nuw i32 1, [[C1:%.*]]414; CHECK-NEXT: [[T4:%.*]] = lshr exact i32 -2147483648, [[C2:%.*]]415; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T4]]416; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T]], [[TMP1]]417; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[K:%.*]], [[TMP2]]418; CHECK-NEXT: [[OR:%.*]] = icmp eq i32 [[TMP3]], [[TMP2]]419; CHECK-NEXT: ret i1 [[OR]]420;421 %t = shl i32 1, %c1422 %t4 = lshr i32 -2147483648, %c2423 %t1 = and i32 %t, %k424 %t2 = icmp ne i32 %t1, 0425 %t5 = and i32 %t4, %k426 %t6 = icmp ne i32 %t5, 0427 %or = select i1 %t2, i1 %t6, i1 false428 ret i1 %or429}430 431define <2 x i1> @foo1_or_signbit_lshr_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32> %c2) {432; CHECK-LABEL: @foo1_or_signbit_lshr_vector(433; CHECK-NEXT: [[T:%.*]] = shl nuw <2 x i32> splat (i32 1), [[C1:%.*]]434; CHECK-NEXT: [[T4:%.*]] = lshr exact <2 x i32> splat (i32 -2147483648), [[C2:%.*]]435; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[T]], [[T4]]436; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[K:%.*]], [[TMP1]]437; CHECK-NEXT: [[OR:%.*]] = icmp eq <2 x i32> [[TMP2]], [[TMP1]]438; CHECK-NEXT: ret <2 x i1> [[OR]]439;440 %t = shl <2 x i32> <i32 1, i32 1>, %c1441 %t4 = lshr <2 x i32> <i32 -2147483648, i32 -2147483648>, %c2442 %t1 = and <2 x i32> %t, %k443 %t2 = icmp ne <2 x i32> %t1, zeroinitializer444 %t5 = and <2 x i32> %t4, %k445 %t6 = icmp ne <2 x i32> %t5, zeroinitializer446 %or = and <2 x i1> %t2, %t6447 ret <2 x i1> %or448}449 450; Same as last two, but shift-of-signbit replaced with 'icmp s*'451define i1 @foo1_and_signbit_lshr_without_shifting_signbit(i32 %k, i32 %c1, i32 %c2) {452; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit(453; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]454; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]]455; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0456; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]]457; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -1458; CHECK-NEXT: [[OR:%.*]] = or i1 [[T2]], [[T4]]459; CHECK-NEXT: ret i1 [[OR]]460;461 %t0 = shl i32 1, %c1462 %t1 = and i32 %t0, %k463 %t2 = icmp eq i32 %t1, 0464 %t3 = shl i32 %k, %c2465 %t4 = icmp sgt i32 %t3, -1466 %or = or i1 %t2, %t4467 ret i1 %or468}469 470define i1 @foo1_and_signbit_lshr_without_shifting_signbit_logical(i32 %k, i32 %c1, i32 %c2) {471; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_logical(472; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]473; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]]474; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0475; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]]476; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -1477; CHECK-NEXT: [[OR:%.*]] = select i1 [[T2]], i1 true, i1 [[T4]]478; CHECK-NEXT: ret i1 [[OR]]479;480 %t0 = shl i32 1, %c1481 %t1 = and i32 %t0, %k482 %t2 = icmp eq i32 %t1, 0483 %t3 = shl i32 %k, %c2484 %t4 = icmp sgt i32 %t3, -1485 %or = select i1 %t2, i1 true, i1 %t4486 ret i1 %or487}488 489define i1 @foo1_or_signbit_lshr_without_shifting_signbit(i32 %k, i32 %c1, i32 %c2) {490; CHECK-LABEL: @foo1_or_signbit_lshr_without_shifting_signbit(491; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]492; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]]493; CHECK-NEXT: [[T2:%.*]] = icmp ne i32 [[T1]], 0494; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]]495; CHECK-NEXT: [[T4:%.*]] = icmp slt i32 [[T3]], 0496; CHECK-NEXT: [[OR:%.*]] = and i1 [[T2]], [[T4]]497; CHECK-NEXT: ret i1 [[OR]]498;499 %t0 = shl i32 1, %c1500 %t1 = and i32 %t0, %k501 %t2 = icmp ne i32 %t1, 0502 %t3 = shl i32 %k, %c2503 %t4 = icmp slt i32 %t3, 0504 %or = and i1 %t2, %t4505 ret i1 %or506}507 508define i1 @foo1_or_signbit_lshr_without_shifting_signbit_logical(i32 %k, i32 %c1, i32 %c2) {509; CHECK-LABEL: @foo1_or_signbit_lshr_without_shifting_signbit_logical(510; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]511; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]]512; CHECK-NEXT: [[T2:%.*]] = icmp ne i32 [[T1]], 0513; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]]514; CHECK-NEXT: [[T4:%.*]] = icmp slt i32 [[T3]], 0515; CHECK-NEXT: [[OR:%.*]] = select i1 [[T2]], i1 [[T4]], i1 false516; CHECK-NEXT: ret i1 [[OR]]517;518 %t0 = shl i32 1, %c1519 %t1 = and i32 %t0, %k520 %t2 = icmp ne i32 %t1, 0521 %t3 = shl i32 %k, %c2522 %t4 = icmp slt i32 %t3, 0523 %or = select i1 %t2, i1 %t4, i1 false524 ret i1 %or525}526 527; Shift-of-signbit replaced with 'icmp s*' for both sides528define i1 @foo1_and_signbit_lshr_without_shifting_signbit_both_sides(i32 %k, i32 %c1, i32 %c2) {529; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_both_sides(530; CHECK-NEXT: [[T0:%.*]] = shl i32 [[K:%.*]], [[C1:%.*]]531; CHECK-NEXT: [[T2:%.*]] = shl i32 [[K]], [[C2:%.*]]532; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[T0]], [[T2]]533; CHECK-NEXT: [[OR:%.*]] = icmp sgt i32 [[TMP1]], -1534; CHECK-NEXT: ret i1 [[OR]]535;536 %t0 = shl i32 %k, %c1537 %t1 = icmp sgt i32 %t0, -1538 %t2 = shl i32 %k, %c2539 %t3 = icmp sgt i32 %t2, -1540 %or = or i1 %t1, %t3541 ret i1 %or542}543 544; %t2 can be poison where as %t0 isn't; merging these two is unsafe.545define i1 @foo1_and_signbit_lshr_without_shifting_signbit_both_sides_logical(i32 %k, i32 %c1, i32 %c2) {546; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_both_sides_logical(547; CHECK-NEXT: [[T0:%.*]] = shl i32 [[K:%.*]], [[C1:%.*]]548; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[T0]], -1549; CHECK-NEXT: [[T2:%.*]] = shl i32 [[K]], [[C2:%.*]]550; CHECK-NEXT: [[T3:%.*]] = icmp sgt i32 [[T2]], -1551; CHECK-NEXT: [[OR:%.*]] = select i1 [[T1]], i1 true, i1 [[T3]]552; CHECK-NEXT: ret i1 [[OR]]553;554 %t0 = shl i32 %k, %c1555 %t1 = icmp sgt i32 %t0, -1556 %t2 = shl i32 %k, %c2557 %t3 = icmp sgt i32 %t2, -1558 %or = select i1 %t1, i1 true, i1 %t3559 ret i1 %or560}561 562define i1 @foo1_or_signbit_lshr_without_shifting_signbit_both_sides(i32 %k, i32 %c1, i32 %c2) {563; CHECK-LABEL: @foo1_or_signbit_lshr_without_shifting_signbit_both_sides(564; CHECK-NEXT: [[T0:%.*]] = shl i32 [[K:%.*]], [[C1:%.*]]565; CHECK-NEXT: [[T2:%.*]] = shl i32 [[K]], [[C2:%.*]]566; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[T0]], [[T2]]567; CHECK-NEXT: [[OR:%.*]] = icmp slt i32 [[TMP1]], 0568; CHECK-NEXT: ret i1 [[OR]]569;570 %t0 = shl i32 %k, %c1571 %t1 = icmp slt i32 %t0, 0572 %t2 = shl i32 %k, %c2573 %t3 = icmp slt i32 %t2, 0574 %or = and i1 %t1, %t3575 ret i1 %or576}577 578define <2 x i1> @foo1_or_signbit_lshr_without_shifting_signbit_both_sides_splat(<2 x i32> %k, <2 x i32> %c1, <2 x i32> %c2) {579; CHECK-LABEL: @foo1_or_signbit_lshr_without_shifting_signbit_both_sides_splat(580; CHECK-NEXT: [[T0:%.*]] = shl <2 x i32> [[K:%.*]], [[C1:%.*]]581; CHECK-NEXT: [[T2:%.*]] = shl <2 x i32> [[K]], [[C2:%.*]]582; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[T0]], [[T2]]583; CHECK-NEXT: [[OR:%.*]] = icmp slt <2 x i32> [[TMP1]], zeroinitializer584; CHECK-NEXT: ret <2 x i1> [[OR]]585;586 %t0 = shl <2 x i32> %k, %c1587 %t1 = icmp slt <2 x i32> %t0, zeroinitializer588 %t2 = shl <2 x i32> %k, %c2589 %t3 = icmp slt <2 x i32> %t2, zeroinitializer590 %or = and <2 x i1> %t1, %t3591 ret <2 x i1> %or592}593 594; %t2 can be poison where as %t0 isn't; merging these two is unsafe.595define i1 @foo1_or_signbit_lshr_without_shifting_signbit_both_sides_logical(i32 %k, i32 %c1, i32 %c2) {596; CHECK-LABEL: @foo1_or_signbit_lshr_without_shifting_signbit_both_sides_logical(597; CHECK-NEXT: [[T0:%.*]] = shl i32 [[K:%.*]], [[C1:%.*]]598; CHECK-NEXT: [[T1:%.*]] = icmp slt i32 [[T0]], 0599; CHECK-NEXT: [[T2:%.*]] = shl i32 [[K]], [[C2:%.*]]600; CHECK-NEXT: [[T3:%.*]] = icmp slt i32 [[T2]], 0601; CHECK-NEXT: [[OR:%.*]] = select i1 [[T1]], i1 [[T3]], i1 false602; CHECK-NEXT: ret i1 [[OR]]603;604 %t0 = shl i32 %k, %c1605 %t1 = icmp slt i32 %t0, 0606 %t2 = shl i32 %k, %c2607 %t3 = icmp slt i32 %t2, 0608 %or = select i1 %t1, i1 %t3, i1 false609 ret i1 %or610}611 612; Extra use613 614; Expect to fold615define i1 @foo1_and_extra_use_shl(i32 %k, i32 %c1, i32 %c2, ptr %p) {616; CHECK-LABEL: @foo1_and_extra_use_shl(617; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]618; CHECK-NEXT: store i32 [[T0]], ptr [[P:%.*]], align 4619; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]]620; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T0]], [[T1]]621; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[K:%.*]], [[TMP1]]622; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]623; CHECK-NEXT: ret i1 [[OR]]624;625 %t0 = shl i32 1, %c1626 store i32 %t0, ptr %p ; extra use of shl627 %t1 = shl i32 1, %c2628 %t2 = and i32 %t0, %k629 %t3 = icmp eq i32 %t2, 0630 %t4 = and i32 %t1, %k631 %t5 = icmp eq i32 %t4, 0632 %or = or i1 %t3, %t5633 ret i1 %or634}635 636define i1 @foo1_and_extra_use_shl_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) {637; CHECK-LABEL: @foo1_and_extra_use_shl_logical(638; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]639; CHECK-NEXT: store i32 [[T0]], ptr [[P:%.*]], align 4640; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]]641; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T1]]642; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T0]], [[TMP1]]643; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[K:%.*]], [[TMP2]]644; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]645; CHECK-NEXT: ret i1 [[OR]]646;647 %t0 = shl i32 1, %c1648 store i32 %t0, ptr %p ; extra use of shl649 %t1 = shl i32 1, %c2650 %t2 = and i32 %t0, %k651 %t3 = icmp eq i32 %t2, 0652 %t4 = and i32 %t1, %k653 %t5 = icmp eq i32 %t4, 0654 %or = select i1 %t3, i1 true, i1 %t5655 ret i1 %or656}657 658; Should not fold659define i1 @foo1_and_extra_use_and(i32 %k, i32 %c1, i32 %c2, ptr %p) {660; CHECK-LABEL: @foo1_and_extra_use_and(661; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]662; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]]663; CHECK-NEXT: [[T2:%.*]] = and i32 [[T0]], [[K:%.*]]664; CHECK-NEXT: store i32 [[T2]], ptr [[P:%.*]], align 4665; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T0]], [[T1]]666; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[K]], [[TMP1]]667; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]668; CHECK-NEXT: ret i1 [[OR]]669;670 %t0 = shl i32 1, %c1671 %t1 = shl i32 1, %c2672 %t2 = and i32 %t0, %k673 store i32 %t2, ptr %p ; extra use of and674 %t3 = icmp eq i32 %t2, 0675 %t4 = and i32 %t1, %k676 %t5 = icmp eq i32 %t4, 0677 %or = or i1 %t3, %t5678 ret i1 %or679}680 681define i1 @foo1_and_extra_use_and_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) {682; CHECK-LABEL: @foo1_and_extra_use_and_logical(683; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]684; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]]685; CHECK-NEXT: [[T2:%.*]] = and i32 [[T0]], [[K:%.*]]686; CHECK-NEXT: store i32 [[T2]], ptr [[P:%.*]], align 4687; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T1]]688; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T0]], [[TMP1]]689; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[K]], [[TMP2]]690; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]691; CHECK-NEXT: ret i1 [[OR]]692;693 %t0 = shl i32 1, %c1694 %t1 = shl i32 1, %c2695 %t2 = and i32 %t0, %k696 store i32 %t2, ptr %p ; extra use of and697 %t3 = icmp eq i32 %t2, 0698 %t4 = and i32 %t1, %k699 %t5 = icmp eq i32 %t4, 0700 %or = select i1 %t3, i1 true, i1 %t5701 ret i1 %or702}703 704; Should not fold705define i1 @foo1_and_extra_use_cmp(i32 %k, i32 %c1, i32 %c2, ptr %p) {706; CHECK-LABEL: @foo1_and_extra_use_cmp(707; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]708; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]]709; CHECK-NEXT: [[T2:%.*]] = and i32 [[T0]], [[K:%.*]]710; CHECK-NEXT: [[T3:%.*]] = icmp eq i32 [[T2]], 0711; CHECK-NEXT: store i1 [[T3]], ptr [[P:%.*]], align 1712; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T0]], [[T1]]713; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[K]], [[TMP1]]714; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]715; CHECK-NEXT: ret i1 [[OR]]716;717 %t0 = shl i32 1, %c1718 %t1 = shl i32 1, %c2719 %t2 = and i32 %t0, %k720 %t3 = icmp eq i32 %t2, 0721 store i1 %t3, ptr %p ; extra use of cmp722 %t4 = and i32 %t1, %k723 %t5 = icmp eq i32 %t4, 0724 %or = or i1 %t3, %t5725 ret i1 %or726}727 728define i1 @foo1_and_extra_use_cmp_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) {729; CHECK-LABEL: @foo1_and_extra_use_cmp_logical(730; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]731; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]]732; CHECK-NEXT: [[T2:%.*]] = and i32 [[T0]], [[K:%.*]]733; CHECK-NEXT: [[T3:%.*]] = icmp eq i32 [[T2]], 0734; CHECK-NEXT: store i1 [[T3]], ptr [[P:%.*]], align 1735; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T1]]736; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T0]], [[TMP1]]737; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[K]], [[TMP2]]738; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]739; CHECK-NEXT: ret i1 [[OR]]740;741 %t0 = shl i32 1, %c1742 %t1 = shl i32 1, %c2743 %t2 = and i32 %t0, %k744 %t3 = icmp eq i32 %t2, 0745 store i1 %t3, ptr %p ; extra use of cmp746 %t4 = and i32 %t1, %k747 %t5 = icmp eq i32 %t4, 0748 %or = select i1 %t3, i1 true, i1 %t5749 ret i1 %or750}751 752; Expect to fold753define i1 @foo1_and_extra_use_shl2(i32 %k, i32 %c1, i32 %c2, ptr %p) {754; CHECK-LABEL: @foo1_and_extra_use_shl2(755; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]756; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]]757; CHECK-NEXT: store i32 [[T1]], ptr [[P:%.*]], align 4758; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T0]], [[T1]]759; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[K:%.*]], [[TMP1]]760; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]761; CHECK-NEXT: ret i1 [[OR]]762;763 %t0 = shl i32 1, %c1764 %t1 = shl i32 1, %c2765 store i32 %t1, ptr %p ; extra use of shl766 %t2 = and i32 %t0, %k767 %t3 = icmp eq i32 %t2, 0768 %t4 = and i32 %t1, %k769 %t5 = icmp eq i32 %t4, 0770 %or = or i1 %t3, %t5771 ret i1 %or772}773 774define i1 @foo1_and_extra_use_shl2_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) {775; CHECK-LABEL: @foo1_and_extra_use_shl2_logical(776; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]777; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]]778; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T1]]779; CHECK-NEXT: store i32 [[TMP1]], ptr [[P:%.*]], align 4780; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T0]], [[TMP1]]781; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[K:%.*]], [[TMP2]]782; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]783; CHECK-NEXT: ret i1 [[OR]]784;785 %t0 = shl i32 1, %c1786 %t1 = shl i32 1, %c2787 store i32 %t1, ptr %p ; extra use of shl788 %t2 = and i32 %t0, %k789 %t3 = icmp eq i32 %t2, 0790 %t4 = and i32 %t1, %k791 %t5 = icmp eq i32 %t4, 0792 %or = select i1 %t3, i1 true, i1 %t5793 ret i1 %or794}795 796; Should not fold797define i1 @foo1_and_extra_use_and2(i32 %k, i32 %c1, i32 %c2, ptr %p) {798; CHECK-LABEL: @foo1_and_extra_use_and2(799; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]800; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]]801; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[K:%.*]]802; CHECK-NEXT: store i32 [[T4]], ptr [[P:%.*]], align 4803; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T0]], [[T1]]804; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[K]], [[TMP1]]805; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]806; CHECK-NEXT: ret i1 [[OR]]807;808 %t0 = shl i32 1, %c1809 %t1 = shl i32 1, %c2810 %t2 = and i32 %t0, %k811 %t3 = icmp eq i32 %t2, 0812 %t4 = and i32 %t1, %k813 store i32 %t4, ptr %p ; extra use of and814 %t5 = icmp eq i32 %t4, 0815 %or = or i1 %t3, %t5816 ret i1 %or817}818 819define i1 @foo1_and_extra_use_and2_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) {820; CHECK-LABEL: @foo1_and_extra_use_and2_logical(821; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]822; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]]823; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T1]]824; CHECK-NEXT: [[T4:%.*]] = and i32 [[TMP1]], [[K:%.*]]825; CHECK-NEXT: store i32 [[T4]], ptr [[P:%.*]], align 4826; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T0]], [[TMP1]]827; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[K]], [[TMP2]]828; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]829; CHECK-NEXT: ret i1 [[OR]]830;831 %t0 = shl i32 1, %c1832 %t1 = shl i32 1, %c2833 %t2 = and i32 %t0, %k834 %t3 = icmp eq i32 %t2, 0835 %t4 = and i32 %t1, %k836 store i32 %t4, ptr %p ; extra use of and837 %t5 = icmp eq i32 %t4, 0838 %or = select i1 %t3, i1 true, i1 %t5839 ret i1 %or840}841 842; Should not fold843define i1 @foo1_and_extra_use_cmp2(i32 %k, i32 %c1, i32 %c2, ptr %p) {844; CHECK-LABEL: @foo1_and_extra_use_cmp2(845; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]846; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]]847; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[K:%.*]]848; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[T4]], 0849; CHECK-NEXT: store i1 [[T5]], ptr [[P:%.*]], align 1850; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T0]], [[T1]]851; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[K]], [[TMP1]]852; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]]853; CHECK-NEXT: ret i1 [[OR]]854;855 %t0 = shl i32 1, %c1856 %t1 = shl i32 1, %c2857 %t2 = and i32 %t0, %k858 %t3 = icmp eq i32 %t2, 0859 %t4 = and i32 %t1, %k860 %t5 = icmp eq i32 %t4, 0861 store i1 %t5, ptr %p ; extra use of cmp862 %or = or i1 %t3, %t5863 ret i1 %or864}865 866define i1 @foo1_and_extra_use_cmp2_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) {867; CHECK-LABEL: @foo1_and_extra_use_cmp2_logical(868; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]869; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]]870; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T1]]871; CHECK-NEXT: [[T4:%.*]] = and i32 [[TMP1]], [[K:%.*]]872; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[T4]], 0873; CHECK-NEXT: store i1 [[T5]], ptr [[P:%.*]], align 1874; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T0]], [[TMP1]]875; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[K]], [[TMP2]]876; CHECK-NEXT: [[OR:%.*]] = icmp ne i32 [[TMP3]], [[TMP2]]877; CHECK-NEXT: ret i1 [[OR]]878;879 %t0 = shl i32 1, %c1880 %t1 = shl i32 1, %c2881 %t2 = and i32 %t0, %k882 %t3 = icmp eq i32 %t2, 0883 %t4 = and i32 %t1, %k884 %t5 = icmp eq i32 %t4, 0885 store i1 %t5, ptr %p ; extra use of cmp886 %or = select i1 %t3, i1 true, i1 %t5887 ret i1 %or888}889 890; Shift-of-signbit replaced with 'icmp s*'891; Expect to fold892define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl1(i32 %k, i32 %c1, i32 %c2, ptr %p) {893; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl1(894; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]895; CHECK-NEXT: store i32 [[T0]], ptr [[P:%.*]], align 4896; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]]897; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0898; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]]899; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -1900; CHECK-NEXT: [[OR:%.*]] = or i1 [[T2]], [[T4]]901; CHECK-NEXT: ret i1 [[OR]]902;903 %t0 = shl i32 1, %c1904 store i32 %t0, ptr %p ; extra use of shl905 %t1 = and i32 %t0, %k906 %t2 = icmp eq i32 %t1, 0907 %t3 = shl i32 %k, %c2908 %t4 = icmp sgt i32 %t3, -1909 %or = or i1 %t2, %t4910 ret i1 %or911}912 913define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl1_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) {914; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl1_logical(915; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]916; CHECK-NEXT: store i32 [[T0]], ptr [[P:%.*]], align 4917; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]]918; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0919; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]]920; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -1921; CHECK-NEXT: [[OR:%.*]] = select i1 [[T2]], i1 true, i1 [[T4]]922; CHECK-NEXT: ret i1 [[OR]]923;924 %t0 = shl i32 1, %c1925 store i32 %t0, ptr %p ; extra use of shl926 %t1 = and i32 %t0, %k927 %t2 = icmp eq i32 %t1, 0928 %t3 = shl i32 %k, %c2929 %t4 = icmp sgt i32 %t3, -1930 %or = select i1 %t2, i1 true, i1 %t4931 ret i1 %or932}933 934; Not fold935define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_and(i32 %k, i32 %c1, i32 %c2, ptr %p) {936; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_and(937; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]938; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]]939; CHECK-NEXT: store i32 [[T1]], ptr [[P:%.*]], align 4940; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0941; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]]942; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -1943; CHECK-NEXT: [[OR:%.*]] = or i1 [[T2]], [[T4]]944; CHECK-NEXT: ret i1 [[OR]]945;946 %t0 = shl i32 1, %c1947 %t1 = and i32 %t0, %k948 store i32 %t1, ptr %p ; extra use of and949 %t2 = icmp eq i32 %t1, 0950 %t3 = shl i32 %k, %c2951 %t4 = icmp sgt i32 %t3, -1952 %or = or i1 %t2, %t4953 ret i1 %or954}955 956define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_and_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) {957; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_and_logical(958; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]959; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]]960; CHECK-NEXT: store i32 [[T1]], ptr [[P:%.*]], align 4961; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0962; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]]963; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -1964; CHECK-NEXT: [[OR:%.*]] = select i1 [[T2]], i1 true, i1 [[T4]]965; CHECK-NEXT: ret i1 [[OR]]966;967 %t0 = shl i32 1, %c1968 %t1 = and i32 %t0, %k969 store i32 %t1, ptr %p ; extra use of and970 %t2 = icmp eq i32 %t1, 0971 %t3 = shl i32 %k, %c2972 %t4 = icmp sgt i32 %t3, -1973 %or = select i1 %t2, i1 true, i1 %t4974 ret i1 %or975}976 977; Not fold978define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp1(i32 %k, i32 %c1, i32 %c2, ptr %p) {979; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp1(980; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]981; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]]982; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0983; CHECK-NEXT: store i1 [[T2]], ptr [[P:%.*]], align 1984; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]]985; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -1986; CHECK-NEXT: [[OR:%.*]] = or i1 [[T2]], [[T4]]987; CHECK-NEXT: ret i1 [[OR]]988;989 %t0 = shl i32 1, %c1990 %t1 = and i32 %t0, %k991 %t2 = icmp eq i32 %t1, 0992 store i1 %t2, ptr %p ; extra use of cmp993 %t3 = shl i32 %k, %c2994 %t4 = icmp sgt i32 %t3, -1995 %or = or i1 %t2, %t4996 ret i1 %or997}998 999define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp1_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) {1000; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp1_logical(1001; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]1002; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]]1003; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 01004; CHECK-NEXT: store i1 [[T2]], ptr [[P:%.*]], align 11005; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]]1006; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -11007; CHECK-NEXT: [[OR:%.*]] = select i1 [[T2]], i1 true, i1 [[T4]]1008; CHECK-NEXT: ret i1 [[OR]]1009;1010 %t0 = shl i32 1, %c11011 %t1 = and i32 %t0, %k1012 %t2 = icmp eq i32 %t1, 01013 store i1 %t2, ptr %p ; extra use of cmp1014 %t3 = shl i32 %k, %c21015 %t4 = icmp sgt i32 %t3, -11016 %or = select i1 %t2, i1 true, i1 %t41017 ret i1 %or1018}1019 1020; Not fold1021define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl2(i32 %k, i32 %c1, i32 %c2, ptr %p) {1022; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl2(1023; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]1024; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]]1025; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 01026; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]]1027; CHECK-NEXT: store i32 [[T3]], ptr [[P:%.*]], align 41028; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -11029; CHECK-NEXT: [[OR:%.*]] = or i1 [[T2]], [[T4]]1030; CHECK-NEXT: ret i1 [[OR]]1031;1032 %t0 = shl i32 1, %c11033 %t1 = and i32 %t0, %k1034 %t2 = icmp eq i32 %t1, 01035 %t3 = shl i32 %k, %c21036 store i32 %t3, ptr %p ; extra use of shl1037 %t4 = icmp sgt i32 %t3, -11038 %or = or i1 %t2, %t41039 ret i1 %or1040}1041 1042define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl2_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) {1043; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl2_logical(1044; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]1045; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]]1046; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 01047; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]]1048; CHECK-NEXT: store i32 [[T3]], ptr [[P:%.*]], align 41049; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -11050; CHECK-NEXT: [[OR:%.*]] = select i1 [[T2]], i1 true, i1 [[T4]]1051; CHECK-NEXT: ret i1 [[OR]]1052;1053 %t0 = shl i32 1, %c11054 %t1 = and i32 %t0, %k1055 %t2 = icmp eq i32 %t1, 01056 %t3 = shl i32 %k, %c21057 store i32 %t3, ptr %p ; extra use of shl1058 %t4 = icmp sgt i32 %t3, -11059 %or = select i1 %t2, i1 true, i1 %t41060 ret i1 %or1061}1062 1063; Not fold1064define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp2(i32 %k, i32 %c1, i32 %c2, ptr %p) {1065; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp2(1066; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]1067; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]]1068; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 01069; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]]1070; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -11071; CHECK-NEXT: store i1 [[T4]], ptr [[P:%.*]], align 11072; CHECK-NEXT: [[OR:%.*]] = or i1 [[T2]], [[T4]]1073; CHECK-NEXT: ret i1 [[OR]]1074;1075 %t0 = shl i32 1, %c11076 %t1 = and i32 %t0, %k1077 %t2 = icmp eq i32 %t1, 01078 %t3 = shl i32 %k, %c21079 %t4 = icmp sgt i32 %t3, -11080 store i1 %t4, ptr %p ; extra use of cmp1081 %or = or i1 %t2, %t41082 ret i1 %or1083}1084 1085define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp2_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) {1086; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp2_logical(1087; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]]1088; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]]1089; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 01090; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]]1091; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -11092; CHECK-NEXT: store i1 [[T4]], ptr [[P:%.*]], align 11093; CHECK-NEXT: [[OR:%.*]] = select i1 [[T2]], i1 true, i1 [[T4]]1094; CHECK-NEXT: ret i1 [[OR]]1095;1096 %t0 = shl i32 1, %c11097 %t1 = and i32 %t0, %k1098 %t2 = icmp eq i32 %t1, 01099 %t3 = shl i32 %k, %c21100 %t4 = icmp sgt i32 %t3, -11101 store i1 %t4, ptr %p ; extra use of cmp1102 %or = select i1 %t2, i1 true, i1 %t41103 ret i1 %or1104}1105 1106; Negative tests1107 1108; This test checks that we are not creating additional shift instruction when fold fails.1109define i1 @foo1_and_signbit_lshr_without_shifting_signbit_not_pwr2(i32 %k, i32 %c1, i32 %c2) {1110; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_not_pwr2(1111; CHECK-NEXT: [[T0:%.*]] = shl i32 3, [[C1:%.*]]1112; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]]1113; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 01114; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]]1115; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -11116; CHECK-NEXT: [[OR:%.*]] = or i1 [[T2]], [[T4]]1117; CHECK-NEXT: ret i1 [[OR]]1118;1119 %t0 = shl i32 3, %c11120 %t1 = and i32 %t0, %k1121 %t2 = icmp eq i32 %t1, 01122 %t3 = shl i32 %k, %c21123 %t4 = icmp sgt i32 %t3, -11124 %or = or i1 %t2, %t41125 ret i1 %or1126}1127 1128define i1 @foo1_and_signbit_lshr_without_shifting_signbit_not_pwr2_logical(i32 %k, i32 %c1, i32 %c2) {1129; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_not_pwr2_logical(1130; CHECK-NEXT: [[T0:%.*]] = shl i32 3, [[C1:%.*]]1131; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]]1132; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 01133; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]]1134; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T3]], -11135; CHECK-NEXT: [[OR:%.*]] = select i1 [[T2]], i1 true, i1 [[T4]]1136; CHECK-NEXT: ret i1 [[OR]]1137;1138 %t0 = shl i32 3, %c11139 %t1 = and i32 %t0, %k1140 %t2 = icmp eq i32 %t1, 01141 %t3 = shl i32 %k, %c21142 %t4 = icmp sgt i32 %t3, -11143 %or = select i1 %t2, i1 true, i1 %t41144 ret i1 %or1145}1146 1147define i1 @two_types_of_bittest(i8 %x, i8 %c) {1148; CHECK-LABEL: @two_types_of_bittest(1149; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[C:%.*]]1150; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[T0]], -1281151; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[X:%.*]], [[TMP1]]1152; CHECK-NEXT: [[RET:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]]1153; CHECK-NEXT: ret i1 [[RET]]1154;1155 %t0 = shl i8 1, %c1156 %icmp1 = icmp slt i8 %x, 01157 %and = and i8 %x, %t01158 %icmp2 = icmp ne i8 %and, 01159 %ret = and i1 %icmp1, %icmp21160 ret i1 %ret1161}1162 1163define i1 @trunc_bittest_and_icmp_bittest(i8 %x, i8 %c) {1164; CHECK-LABEL: @trunc_bittest_and_icmp_bittest(1165; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[C:%.*]]1166; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[T0]], 11167; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[X:%.*]], [[TMP1]]1168; CHECK-NEXT: [[RET:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]]1169; CHECK-NEXT: ret i1 [[RET]]1170;1171 %t0 = shl i8 1, %c1172 %trunc = trunc i8 %x to i11173 %and = and i8 %x, %t01174 %icmp2 = icmp ne i8 %and, 01175 %ret = and i1 %trunc, %icmp21176 ret i1 %ret1177}1178 1179define i1 @trunc_bittest_or_icmp_bittest(i8 %x, i8 %c) {1180; CHECK-LABEL: @trunc_bittest_or_icmp_bittest(1181; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[C:%.*]]1182; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[T0]], 11183; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[X:%.*]], [[TMP1]]1184; CHECK-NEXT: [[RET:%.*]] = icmp ne i8 [[TMP2]], [[TMP1]]1185; CHECK-NEXT: ret i1 [[RET]]1186;1187 %t0 = shl i8 1, %c1188 %trunc = trunc i8 %x to i11189 %and = and i8 %x, %t01190 %icmp2 = icmp eq i8 %and, 01191 %not = xor i1 %trunc, true1192 %ret = or i1 %not, %icmp21193 ret i1 %ret1194}1195