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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -passes=instcombine < %s | FileCheck %s3; <rdar://problem/8558713>4 5declare void @throwAnExceptionOrWhatever()6 7define i32 @test1(i32 %a, i32 %b) nounwind ssp {8; CHECK-LABEL: @test1(9; CHECK-NEXT:  entry:10; CHECK-NEXT:    [[SADD:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[B:%.*]], i32 [[A:%.*]])11; CHECK-NEXT:    [[TMP0:%.*]] = extractvalue { i32, i1 } [[SADD]], 112; CHECK-NEXT:    br i1 [[TMP0]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]13; CHECK:       if.then:14; CHECK-NEXT:    tail call void @throwAnExceptionOrWhatever() #[[ATTR3:[0-9]+]]15; CHECK-NEXT:    br label [[IF_END]]16; CHECK:       if.end:17; CHECK-NEXT:    [[SADD_RESULT:%.*]] = extractvalue { i32, i1 } [[SADD]], 018; CHECK-NEXT:    ret i32 [[SADD_RESULT]]19;20entry:21  %conv = sext i32 %a to i6422  %conv2 = sext i32 %b to i6423  %add = add nsw i64 %conv2, %conv24  %add.off = add i64 %add, 214748364825  %0 = icmp ugt i64 %add.off, 429496729526  br i1 %0, label %if.then, label %if.end27 28if.then:29  tail call void @throwAnExceptionOrWhatever() nounwind30  br label %if.end31 32if.end:33  %conv9 = trunc i64 %add to i3234  ret i32 %conv935}36 37; This form should not be promoted for two reasons: 1) it is unprofitable to38; promote it since the add.off instruction has another use, and 2) it is unsafe39; because the add-with-off makes the high bits of the original add live.40 41define i32 @test2(i32 %a, i32 %b, ptr %P) nounwind ssp {42; CHECK-LABEL: @test2(43; CHECK-NEXT:  entry:44; CHECK-NEXT:    [[CONV:%.*]] = sext i32 [[A:%.*]] to i6445; CHECK-NEXT:    [[CONV2:%.*]] = sext i32 [[B:%.*]] to i6446; CHECK-NEXT:    [[ADD:%.*]] = add nsw i64 [[CONV2]], [[CONV]]47; CHECK-NEXT:    [[ADD_OFF:%.*]] = add nsw i64 [[ADD]], 214748364848; CHECK-NEXT:    store i64 [[ADD_OFF]], ptr [[P:%.*]], align 449; CHECK-NEXT:    [[TMP0:%.*]] = icmp ugt i64 [[ADD_OFF]], 429496729550; CHECK-NEXT:    br i1 [[TMP0]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]51; CHECK:       if.then:52; CHECK-NEXT:    tail call void @throwAnExceptionOrWhatever() #[[ATTR3]]53; CHECK-NEXT:    br label [[IF_END]]54; CHECK:       if.end:55; CHECK-NEXT:    [[CONV9:%.*]] = trunc i64 [[ADD]] to i3256; CHECK-NEXT:    ret i32 [[CONV9]]57;58entry:59  %conv = sext i32 %a to i6460  %conv2 = sext i32 %b to i6461  %add = add nsw i64 %conv2, %conv62  %add.off = add i64 %add, 214748364863  store i64 %add.off, ptr %P64  %0 = icmp ugt i64 %add.off, 429496729565  br i1 %0, label %if.then, label %if.end66 67if.then:68  tail call void @throwAnExceptionOrWhatever() nounwind69  br label %if.end70 71if.end:72  %conv9 = trunc i64 %add to i3273  ret i32 %conv974}75 76; PR881677; This is illegal to transform because the high bits of the original add are78; live out.79define i64 @test3(i32 %a, i32 %b) nounwind ssp {80; CHECK-LABEL: @test3(81; CHECK-NEXT:  entry:82; CHECK-NEXT:    [[CONV:%.*]] = sext i32 [[A:%.*]] to i6483; CHECK-NEXT:    [[CONV2:%.*]] = sext i32 [[B:%.*]] to i6484; CHECK-NEXT:    [[ADD:%.*]] = add nsw i64 [[CONV2]], [[CONV]]85; CHECK-NEXT:    [[TMP0:%.*]] = add nsw i64 [[ADD]], -214748364886; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i64 [[TMP0]], -429496729687; CHECK-NEXT:    br i1 [[TMP1]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]88; CHECK:       if.then:89; CHECK-NEXT:    tail call void @throwAnExceptionOrWhatever() #[[ATTR3]]90; CHECK-NEXT:    br label [[IF_END]]91; CHECK:       if.end:92; CHECK-NEXT:    ret i64 [[ADD]]93;94entry:95  %conv = sext i32 %a to i6496  %conv2 = sext i32 %b to i6497  %add = add nsw i64 %conv2, %conv98  %add.off = add i64 %add, 214748364899  %0 = icmp ugt i64 %add.off, 4294967295100  br i1 %0, label %if.then, label %if.end101 102if.then:103  tail call void @throwAnExceptionOrWhatever() nounwind104  br label %if.end105 106if.end:107  ret i64 %add108}109 110; Should be able to form an i8 sadd computed in an i32.111 112define zeroext i8 @test4(i8 signext %a, i8 signext %b) nounwind ssp {113; CHECK-LABEL: @test4(114; CHECK-NEXT:  entry:115; CHECK-NEXT:    [[SADD:%.*]] = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 [[B:%.*]], i8 [[A:%.*]])116; CHECK-NEXT:    [[CMP:%.*]] = extractvalue { i8, i1 } [[SADD]], 1117; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]118; CHECK:       if.then:119; CHECK-NEXT:    tail call void @throwAnExceptionOrWhatever() #[[ATTR3]]120; CHECK-NEXT:    unreachable121; CHECK:       if.end:122; CHECK-NEXT:    [[SADD_RESULT:%.*]] = extractvalue { i8, i1 } [[SADD]], 0123; CHECK-NEXT:    ret i8 [[SADD_RESULT]]124;125entry:126  %conv = sext i8 %a to i32127  %conv2 = sext i8 %b to i32128  %add = add nsw i32 %conv2, %conv129  %add4 = add nsw i32 %add, 128130  %cmp = icmp ugt i32 %add4, 255131  br i1 %cmp, label %if.then, label %if.end132if.then:133  tail call void @throwAnExceptionOrWhatever() nounwind134  unreachable135 136if.end:137  %conv7 = trunc i32 %add to i8138  ret i8 %conv7139}140 141; PR11438142; This is @test1, but the operands are not sign-extended.  Make sure143; we don't transform this case.144 145define i32 @test8(i64 %a, i64 %b) nounwind ssp {146; CHECK-LABEL: @test8(147; CHECK-NEXT:  entry:148; CHECK-NEXT:    [[ADD:%.*]] = add i64 [[A:%.*]], [[B:%.*]]149; CHECK-NEXT:    [[TMP0:%.*]] = add i64 [[ADD]], -2147483648150; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i64 [[TMP0]], -4294967296151; CHECK-NEXT:    br i1 [[TMP1]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]152; CHECK:       if.then:153; CHECK-NEXT:    tail call void @throwAnExceptionOrWhatever() #[[ATTR3]]154; CHECK-NEXT:    br label [[IF_END]]155; CHECK:       if.end:156; CHECK-NEXT:    [[CONV9:%.*]] = trunc i64 [[ADD]] to i32157; CHECK-NEXT:    ret i32 [[CONV9]]158;159entry:160  %add = add i64 %a, %b161  %add.off = add i64 %add, 2147483648162  %0 = icmp ugt i64 %add.off, 4294967295163  br i1 %0, label %if.then, label %if.end164 165if.then:166  tail call void @throwAnExceptionOrWhatever() nounwind167  br label %if.end168 169if.end:170  %conv9 = trunc i64 %add to i32171  ret i32 %conv9172}173 174define i32 @uadd_no_overflow(i32 %a, i32 %b) {175; CHECK-LABEL: @uadd_no_overflow(176; CHECK-NEXT:    [[TMP1:%.*]] = add nuw i32 [[A:%.*]], [[B:%.*]]177; CHECK-NEXT:    ret i32 [[TMP1]]178;179  %val = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)180  %ov = extractvalue { i32, i1 } %val, 1181  %nowrap = xor i1 %ov, true182  tail call void @llvm.assume(i1 %nowrap)183  %res = extractvalue { i32, i1 } %val, 0184  ret i32 %res185}186 187define i32 @smul_no_overflow(i32 %a, i32 %b) {188; CHECK-LABEL: @smul_no_overflow(189; CHECK-NEXT:    [[TMP1:%.*]] = mul nsw i32 [[A:%.*]], [[B:%.*]]190; CHECK-NEXT:    ret i32 [[TMP1]]191;192  %val = tail call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %a, i32 %b)193  %ov = extractvalue { i32, i1 } %val, 1194  %nowrap = xor i1 %ov, true195  tail call void @llvm.assume(i1 %nowrap)196  %res = extractvalue { i32, i1 } %val, 0197  ret i32 %res198}199 200define i32 @smul_overflow(i32 %a, i32 %b) {201; CHECK-LABEL: @smul_overflow(202; CHECK-NEXT:    [[VAL:%.*]] = tail call { i32, i1 } @llvm.smul.with.overflow.i32(i32 [[A:%.*]], i32 [[B:%.*]])203; CHECK-NEXT:    [[OV:%.*]] = extractvalue { i32, i1 } [[VAL]], 1204; CHECK-NEXT:    tail call void @llvm.assume(i1 [[OV]])205; CHECK-NEXT:    [[RES:%.*]] = extractvalue { i32, i1 } [[VAL]], 0206; CHECK-NEXT:    ret i32 [[RES]]207;208  %val = tail call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %a, i32 %b)209  %ov = extractvalue { i32, i1 } %val, 1210  tail call void @llvm.assume(i1 %ov)211  %res = extractvalue { i32, i1 } %val, 0212  ret i32 %res213}214 215define i32 @uadd_no_overflow_invalid1(i32 %a, i32 %b, i1 %cond) {216; CHECK-LABEL: @uadd_no_overflow_invalid1(217; CHECK-NEXT:    [[VAL:%.*]] = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 [[A:%.*]], i32 [[B:%.*]])218; CHECK-NEXT:    [[RES:%.*]] = extractvalue { i32, i1 } [[VAL]], 0219; CHECK-NEXT:    call void @use(i32 [[RES]])220; CHECK-NEXT:    br i1 [[COND:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]221; CHECK:       if.then:222; CHECK-NEXT:    [[OV:%.*]] = extractvalue { i32, i1 } [[VAL]], 1223; CHECK-NEXT:    [[NOWRAP:%.*]] = xor i1 [[OV]], true224; CHECK-NEXT:    tail call void @llvm.assume(i1 [[NOWRAP]])225; CHECK-NEXT:    ret i32 [[RES]]226; CHECK:       if.else:227; CHECK-NEXT:    ret i32 0228;229  %val = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)230  %res = extractvalue { i32, i1 } %val, 0231  call void @use(i32 %res)232  br i1 %cond, label %if.then, label %if.else233if.then:234  %ov = extractvalue { i32, i1 } %val, 1235  %nowrap = xor i1 %ov, true236  tail call void @llvm.assume(i1 %nowrap)237  ret i32 %res238if.else:239  ret i32 0240}241 242define i32 @uadd_no_overflow_invalid2(i32 %a, i32 %b, i1 %cond) {243; CHECK-LABEL: @uadd_no_overflow_invalid2(244; CHECK-NEXT:    [[VAL:%.*]] = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 [[A:%.*]], i32 [[B:%.*]])245; CHECK-NEXT:    [[OV:%.*]] = extractvalue { i32, i1 } [[VAL]], 1246; CHECK-NEXT:    [[NOWRAP:%.*]] = xor i1 [[OV]], true247; CHECK-NEXT:    call void @use(i32 0)248; CHECK-NEXT:    tail call void @llvm.assume(i1 [[NOWRAP]])249; CHECK-NEXT:    [[RES:%.*]] = extractvalue { i32, i1 } [[VAL]], 0250; CHECK-NEXT:    ret i32 [[RES]]251;252  %val = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)253  %ov = extractvalue { i32, i1 } %val, 1254  %nowrap = xor i1 %ov, true255  call void @use(i32 0) ; It is not guaranteed to transfer execution to its successors256  tail call void @llvm.assume(i1 %nowrap)257  %res = extractvalue { i32, i1 } %val, 0258  ret i32 %res259}260 261declare void @use(i32)262