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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt -passes=instcombine -S < %s | FileCheck %s3 4define i32 @widget(i32 %arg, i32 %arg1) {5; CHECK-LABEL: define i32 @widget(6; CHECK-SAME: i32 [[ARG:%.*]], i32 [[ARG1:%.*]]) {7; CHECK-NEXT: bb:8; CHECK-NEXT: [[ICMP:%.*]] = icmp ne i32 [[ARG]], 09; CHECK-NEXT: [[TMP0:%.*]] = zext i1 [[ICMP]] to i3210; CHECK-NEXT: [[MUL:%.*]] = shl nuw nsw i32 20, [[TMP0]]11; CHECK-NEXT: [[XOR:%.*]] = zext i1 [[ICMP]] to i3212; CHECK-NEXT: [[ADD9:%.*]] = or disjoint i32 [[MUL]], [[XOR]]13; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[ICMP]] to i3214; CHECK-NEXT: [[MUL2:%.*]] = shl nuw nsw i32 [[ADD9]], [[TMP1]]15; CHECK-NEXT: ret i32 [[MUL2]]16;17bb:18 %icmp = icmp eq i32 %arg, 019 %zext = zext i1 %icmp to i3220 %sub = sub i32 2, %zext21 %mul = mul i32 20, %sub22 %zext8 = zext i1 %icmp to i3223 %xor = xor i32 %zext8, 124 %add9 = add i32 %mul, %xor25 %mul2 = mul i32 %add9, %sub26 ret i32 %mul227}28