87 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=instcombine -S | FileCheck %s3;4; This test makes sure that InstCombine does not replace the sequence of5; xor/sub instruction followed by cmp instruction into a single cmp instruction6; if there is more than one use of xor/sub.7 8define zeroext i1 @test1(i32 %lhs, i32 %rhs) {9; CHECK-LABEL: @test1(10; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[LHS:%.*]], 1511; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[LHS]], [[RHS:%.*]]12; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[TMP1]], 513; CHECK-NEXT: [[SEL:%.*]] = or i1 [[CMP1]], [[CMP2]]14; CHECK-NEXT: ret i1 [[SEL]]15;16 17 %xor = xor i32 %lhs, 518 %cmp1 = icmp eq i32 %xor, 1019 %cmp2 = icmp eq i32 %xor, %rhs20 %sel = or i1 %cmp1, %cmp221 ret i1 %sel22}23 24define zeroext i1 @test1_logical(i32 %lhs, i32 %rhs) {25; CHECK-LABEL: @test1_logical(26; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[LHS:%.*]], 1527; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[LHS]], [[RHS:%.*]]28; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[TMP1]], 529; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1]], i1 true, i1 [[CMP2]]30; CHECK-NEXT: ret i1 [[SEL]]31;32 33 %xor = xor i32 %lhs, 534 %cmp1 = icmp eq i32 %xor, 1035 %cmp2 = icmp eq i32 %xor, %rhs36 %sel = select i1 %cmp1, i1 true, i1 %cmp237 ret i1 %sel38}39 40define zeroext i1 @test2(i32 %lhs, i32 %rhs) {41; CHECK-LABEL: @test2(42; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[LHS:%.*]], [[RHS:%.*]]43; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[LHS]], [[RHS]]44; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[XOR]], 3245; CHECK-NEXT: [[SEL:%.*]] = xor i1 [[CMP1]], [[CMP2]]46; CHECK-NEXT: ret i1 [[SEL]]47;48 49 %xor = xor i32 %lhs, %rhs50 %cmp1 = icmp eq i32 %xor, 051 %cmp2 = icmp eq i32 %xor, 3252 %sel = xor i1 %cmp1, %cmp253 ret i1 %sel54}55 56define zeroext i1 @test3(i32 %lhs, i32 %rhs) {57; CHECK-LABEL: @test3(58; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[LHS:%.*]], [[RHS:%.*]]59; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[LHS]], [[RHS]]60; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[SUB]], 3161; CHECK-NEXT: [[SEL:%.*]] = or i1 [[CMP1]], [[CMP2]]62; CHECK-NEXT: ret i1 [[SEL]]63;64 65 %sub = sub nsw i32 %lhs, %rhs66 %cmp1 = icmp eq i32 %sub, 067 %cmp2 = icmp eq i32 %sub, 3168 %sel = or i1 %cmp1, %cmp269 ret i1 %sel70}71 72define zeroext i1 @test3_logical(i32 %lhs, i32 %rhs) {73; CHECK-LABEL: @test3_logical(74; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[LHS:%.*]], [[RHS:%.*]]75; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[LHS]], [[RHS]]76; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[SUB]], 3177; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP1]], i1 true, i1 [[CMP2]]78; CHECK-NEXT: ret i1 [[SEL]]79;80 81 %sub = sub nsw i32 %lhs, %rhs82 %cmp1 = icmp eq i32 %sub, 083 %cmp2 = icmp eq i32 %sub, 3184 %sel = select i1 %cmp1, i1 true, i1 %cmp285 ret i1 %sel86}87