107 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=instcombine -S | FileCheck %s3 4define i1 @reduce_add_self(<8 x i1> %x) {5; CHECK-LABEL: @reduce_add_self(6; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i87; CHECK-NEXT: [[TMP2:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[TMP1]])8; CHECK-NEXT: [[RES:%.*]] = trunc i8 [[TMP2]] to i19; CHECK-NEXT: ret i1 [[RES]]10;11 %res = call i1 @llvm.vector.reduce.add.v8i32(<8 x i1> %x)12 ret i1 %res13}14 15define i32 @reduce_add_sext(<4 x i1> %x) {16; CHECK-LABEL: @reduce_add_sext(17; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[X:%.*]] to i418; CHECK-NEXT: [[TMP2:%.*]] = call range(i4 0, 5) i4 @llvm.ctpop.i4(i4 [[TMP1]])19; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i4 [[TMP2]] to i3220; CHECK-NEXT: [[RES:%.*]] = sub nsw i32 0, [[TMP3]]21; CHECK-NEXT: ret i32 [[RES]]22;23 %sext = sext <4 x i1> %x to <4 x i32>24 %res = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %sext)25 ret i32 %res26}27 28define i64 @reduce_add_zext(<8 x i1> %x) {29; CHECK-LABEL: @reduce_add_zext(30; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i831; CHECK-NEXT: [[TMP2:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[TMP1]])32; CHECK-NEXT: [[RES:%.*]] = zext nneg i8 [[TMP2]] to i6433; CHECK-NEXT: ret i64 [[RES]]34;35 %zext = zext <8 x i1> %x to <8 x i64>36 %res = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %zext)37 ret i64 %res38}39 40define i16 @reduce_add_sext_same(<16 x i1> %x) {41; CHECK-LABEL: @reduce_add_sext_same(42; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i1> [[X:%.*]] to i1643; CHECK-NEXT: [[TMP2:%.*]] = call range(i16 0, 17) i16 @llvm.ctpop.i16(i16 [[TMP1]])44; CHECK-NEXT: [[RES:%.*]] = sub nsw i16 0, [[TMP2]]45; CHECK-NEXT: ret i16 [[RES]]46;47 %sext = sext <16 x i1> %x to <16 x i16>48 %res = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %sext)49 ret i16 %res50}51 52define i8 @reduce_add_zext_long(<128 x i1> %x) {53; CHECK-LABEL: @reduce_add_zext_long(54; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i12855; CHECK-NEXT: [[TMP2:%.*]] = call range(i128 0, 129) i128 @llvm.ctpop.i128(i128 [[TMP1]])56; CHECK-NEXT: [[TMP3:%.*]] = trunc nuw i128 [[TMP2]] to i857; CHECK-NEXT: [[RES:%.*]] = sub i8 0, [[TMP3]]58; CHECK-NEXT: ret i8 [[RES]]59;60 %sext = sext <128 x i1> %x to <128 x i8>61 %res = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> %sext)62 ret i8 %res63}64 65@glob = external global i8, align 166define i8 @reduce_add_zext_long_external_use(<128 x i1> %x) {67; CHECK-LABEL: @reduce_add_zext_long_external_use(68; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i12869; CHECK-NEXT: [[TMP2:%.*]] = call range(i128 0, 129) i128 @llvm.ctpop.i128(i128 [[TMP1]])70; CHECK-NEXT: [[TMP3:%.*]] = trunc nuw i128 [[TMP2]] to i871; CHECK-NEXT: [[RES:%.*]] = sub i8 0, [[TMP3]]72; CHECK-NEXT: [[TMP4:%.*]] = extractelement <128 x i1> [[X]], i64 073; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP4]] to i874; CHECK-NEXT: store i8 [[EXT]], ptr @glob, align 175; CHECK-NEXT: ret i8 [[RES]]76;77 %sext = sext <128 x i1> %x to <128 x i8>78 %res = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> %sext)79 %ext = extractelement <128 x i8> %sext, i32 080 store i8 %ext, ptr @glob, align 181 ret i8 %res82}83 84@glob1 = external global i64, align 885define i64 @reduce_add_zext_external_use(<8 x i1> %x) {86; CHECK-LABEL: @reduce_add_zext_external_use(87; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i888; CHECK-NEXT: [[TMP2:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[TMP1]])89; CHECK-NEXT: [[RES:%.*]] = zext nneg i8 [[TMP2]] to i6490; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i1> [[X]], i64 091; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP3]] to i6492; CHECK-NEXT: store i64 [[EXT]], ptr @glob1, align 893; CHECK-NEXT: ret i64 [[RES]]94;95 %zext = zext <8 x i1> %x to <8 x i64>96 %res = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %zext)97 %ext = extractelement <8 x i64> %zext, i32 098 store i64 %ext, ptr @glob1, align 899 ret i64 %res100}101 102declare i1 @llvm.vector.reduce.add.v8i32(<8 x i1> %a)103declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a)104declare i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %a)105declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %a)106declare i8 @llvm.vector.reduce.add.v128i8(<128 x i8> %a)107