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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=instcombine -S | FileCheck %s3 4define i1 @reduce_xor_self(<8 x i1> %x) {5; CHECK-LABEL: @reduce_xor_self(6; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i87; CHECK-NEXT: [[TMP2:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[TMP1]])8; CHECK-NEXT: [[RES:%.*]] = trunc i8 [[TMP2]] to i19; CHECK-NEXT: ret i1 [[RES]]10;11 %res = call i1 @llvm.vector.reduce.xor.v8i32(<8 x i1> %x)12 ret i1 %res13}14 15define i32 @reduce_xor_sext(<4 x i1> %x) {16; CHECK-LABEL: @reduce_xor_sext(17; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[X:%.*]] to i418; CHECK-NEXT: [[TMP2:%.*]] = call range(i4 0, 5) i4 @llvm.ctpop.i4(i4 [[TMP1]])19; CHECK-NEXT: [[TMP3:%.*]] = trunc i4 [[TMP2]] to i120; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP3]] to i3221; CHECK-NEXT: ret i32 [[RES]]22;23 %sext = sext <4 x i1> %x to <4 x i32>24 %res = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %sext)25 ret i32 %res26}27 28define i64 @reduce_xor_zext(<8 x i1> %x) {29; CHECK-LABEL: @reduce_xor_zext(30; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i831; CHECK-NEXT: [[TMP2:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[TMP1]])32; CHECK-NEXT: [[TMP3:%.*]] = and i8 [[TMP2]], 133; CHECK-NEXT: [[RES:%.*]] = zext nneg i8 [[TMP3]] to i6434; CHECK-NEXT: ret i64 [[RES]]35;36 %zext = zext <8 x i1> %x to <8 x i64>37 %res = call i64 @llvm.vector.reduce.xor.v8i64(<8 x i64> %zext)38 ret i64 %res39}40 41define i16 @reduce_xor_sext_same(<16 x i1> %x) {42; CHECK-LABEL: @reduce_xor_sext_same(43; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i1> [[X:%.*]] to i1644; CHECK-NEXT: [[TMP2:%.*]] = call range(i16 0, 17) i16 @llvm.ctpop.i16(i16 [[TMP1]])45; CHECK-NEXT: [[TMP3:%.*]] = and i16 [[TMP2]], 146; CHECK-NEXT: [[SEXT:%.*]] = sub nsw i16 0, [[TMP3]]47; CHECK-NEXT: ret i16 [[SEXT]]48;49 %sext = sext <16 x i1> %x to <16 x i16>50 %res = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %sext)51 ret i16 %res52}53 54define i8 @reduce_xor_zext_long(<128 x i1> %x) {55; CHECK-LABEL: @reduce_xor_zext_long(56; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i12857; CHECK-NEXT: [[TMP2:%.*]] = call range(i128 0, 129) i128 @llvm.ctpop.i128(i128 [[TMP1]])58; CHECK-NEXT: [[TMP3:%.*]] = trunc i128 [[TMP2]] to i159; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP3]] to i860; CHECK-NEXT: ret i8 [[RES]]61;62 %sext = sext <128 x i1> %x to <128 x i8>63 %res = call i8 @llvm.vector.reduce.xor.v128i8(<128 x i8> %sext)64 ret i8 %res65}66 67@glob = external global i8, align 168define i8 @reduce_xor_zext_long_external_use(<128 x i1> %x) {69; CHECK-LABEL: @reduce_xor_zext_long_external_use(70; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i12871; CHECK-NEXT: [[TMP2:%.*]] = call range(i128 0, 129) i128 @llvm.ctpop.i128(i128 [[TMP1]])72; CHECK-NEXT: [[TMP3:%.*]] = trunc i128 [[TMP2]] to i173; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP3]] to i874; CHECK-NEXT: [[TMP5:%.*]] = extractelement <128 x i1> [[X]], i64 075; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP5]] to i876; CHECK-NEXT: store i8 [[EXT]], ptr @glob, align 177; CHECK-NEXT: ret i8 [[RES]]78;79 %sext = sext <128 x i1> %x to <128 x i8>80 %res = call i8 @llvm.vector.reduce.xor.v128i8(<128 x i8> %sext)81 %ext = extractelement <128 x i8> %sext, i32 082 store i8 %ext, ptr @glob, align 183 ret i8 %res84}85 86@glob1 = external global i64, align 887define i64 @reduce_xor_zext_external_use(<8 x i1> %x) {88; CHECK-LABEL: @reduce_xor_zext_external_use(89; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i890; CHECK-NEXT: [[TMP2:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[TMP1]])91; CHECK-NEXT: [[TMP3:%.*]] = and i8 [[TMP2]], 192; CHECK-NEXT: [[RES:%.*]] = zext nneg i8 [[TMP3]] to i6493; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i1> [[X]], i64 094; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP4]] to i6495; CHECK-NEXT: store i64 [[EXT]], ptr @glob1, align 896; CHECK-NEXT: ret i64 [[RES]]97;98 %zext = zext <8 x i1> %x to <8 x i64>99 %res = call i64 @llvm.vector.reduce.xor.v8i64(<8 x i64> %zext)100 %ext = extractelement <8 x i64> %zext, i32 0101 store i64 %ext, ptr @glob1, align 8102 ret i64 %res103}104 105declare i1 @llvm.vector.reduce.xor.v8i32(<8 x i1> %a)106declare i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %a)107declare i64 @llvm.vector.reduce.xor.v8i64(<8 x i64> %a)108declare i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %a)109declare i8 @llvm.vector.reduce.xor.v128i8(<128 x i8> %a)110