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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=instcombine -S | FileCheck %s3declare void @use8(i8)4declare i64 @llvm.vscale.i64()5declare i32 @llvm.vscale.i32()6 7define i8 @srem_non_matching(i8 %X, i8 %Y) {8; CHECK-LABEL: @srem_non_matching(9; CHECK-NEXT: [[BO0:%.*]] = mul nuw nsw i8 [[X:%.*]], 1510; CHECK-NEXT: [[BO1:%.*]] = mul nuw nsw i8 [[Y:%.*]], 511; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]12; CHECK-NEXT: ret i8 [[R]]13;14 %BO0 = mul nsw nuw i8 %X, 1515 %BO1 = mul nsw nuw i8 %Y, 516 %r = srem i8 %BO0, %BO117 ret i8 %r18}19 20define i8 @urem_1_shl(i8 %X, i8 %Y) {21; CHECK-LABEL: @urem_1_shl(22; CHECK-NEXT: [[BO0:%.*]] = shl nuw nsw i8 1, [[X:%.*]]23; CHECK-NEXT: [[NOTMASK:%.*]] = shl nsw i8 -1, [[Y:%.*]]24; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[NOTMASK]], -125; CHECK-NEXT: [[R:%.*]] = and i8 [[BO0]], [[TMP1]]26; CHECK-NEXT: ret i8 [[R]]27;28 %BO0 = shl nsw nuw i8 1, %X29 %BO1 = shl nsw nuw i8 1, %Y30 %r = urem i8 %BO0, %BO131 ret i8 %r32}33 34define <vscale x 16 x i8> @urem_XY_XZ_with_CY_rem_CZ_eq_0_scalable(<vscale x 16 x i8> %X) {35; CHECK-LABEL: @urem_XY_XZ_with_CY_rem_CZ_eq_0_scalable(36; CHECK-NEXT: ret <vscale x 16 x i8> zeroinitializer37;38 %BO0 = mul nuw <vscale x 16 x i8> %X, splat (i8 15)39 %BO1 = mul <vscale x 16 x i8> %X, splat (i8 5)40 %r = urem <vscale x 16 x i8> %BO0, %BO141 ret <vscale x 16 x i8> %r42}43 44define i8 @urem_XY_XZ_with_CY_rem_CZ_eq_0(i8 %X) {45; CHECK-LABEL: @urem_XY_XZ_with_CY_rem_CZ_eq_0(46; CHECK-NEXT: ret i8 047;48 %BO0 = mul nuw i8 %X, 1549 %BO1 = mul i8 %X, 550 %r = urem i8 %BO0, %BO151 ret i8 %r52}53 54define i8 @urem_XY_XZ_with_CY_rem_CZ_eq_0_with_shl(i8 %X) {55; CHECK-LABEL: @urem_XY_XZ_with_CY_rem_CZ_eq_0_with_shl(56; CHECK-NEXT: ret i8 057;58 %BO0 = shl nuw i8 15, %X59 %BO1 = shl i8 5, %X60 %r = urem i8 %BO0, %BO161 ret i8 %r62}63 64define i8 @urem_XY_XZ_with_CY_rem_CZ_eq_0_fail_missing_flag(i8 %X) {65; CHECK-LABEL: @urem_XY_XZ_with_CY_rem_CZ_eq_0_fail_missing_flag(66; CHECK-NEXT: [[BO0:%.*]] = mul nsw i8 [[X:%.*]], 1567; CHECK-NEXT: [[BO1:%.*]] = mul nuw nsw i8 [[X]], 568; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]69; CHECK-NEXT: ret i8 [[R]]70;71 %BO0 = mul nsw i8 %X, 1572 %BO1 = mul nsw nuw i8 %X, 573 %r = urem i8 %BO0, %BO174 ret i8 %r75}76 77define i8 @urem_XY_XZ_with_CY_lt_CZ(i8 %X) {78; CHECK-LABEL: @urem_XY_XZ_with_CY_lt_CZ(79; CHECK-NEXT: [[R:%.*]] = mul nuw i8 [[X:%.*]], 380; CHECK-NEXT: ret i8 [[R]]81;82 %BO0 = mul i8 %X, 383 %BO1 = mul nuw i8 %X, 1284 %r = urem i8 %BO0, %BO185 ret i8 %r86}87 88define i8 @urem_XY_XZ_with_CY_lt_CZ_with_shl(i8 %X) {89; CHECK-LABEL: @urem_XY_XZ_with_CY_lt_CZ_with_shl(90; CHECK-NEXT: [[R:%.*]] = shl nuw i8 3, [[X:%.*]]91; CHECK-NEXT: ret i8 [[R]]92;93 %BO0 = shl i8 3, %X94 %BO1 = shl nuw i8 12, %X95 %r = urem i8 %BO0, %BO196 ret i8 %r97}98 99define <2 x i8> @urem_XY_XZ_with_CY_lt_CZ_with_nsw_out(<2 x i8> %X) {100; CHECK-LABEL: @urem_XY_XZ_with_CY_lt_CZ_with_nsw_out(101; CHECK-NEXT: [[R:%.*]] = shl nuw nsw <2 x i8> [[X:%.*]], splat (i8 2)102; CHECK-NEXT: ret <2 x i8> [[R]]103;104 %BO0 = shl nsw <2 x i8> %X, <i8 2, i8 2>105 %BO1 = mul nuw <2 x i8> %X, <i8 12, i8 12>106 %r = urem <2 x i8> %BO0, %BO1107 ret <2 x i8> %r108}109 110define i8 @urem_XY_XZ_with_CY_lt_CZ_no_nsw_out(i8 %X) {111; CHECK-LABEL: @urem_XY_XZ_with_CY_lt_CZ_no_nsw_out(112; CHECK-NEXT: [[R:%.*]] = mul nuw i8 [[X:%.*]], 3113; CHECK-NEXT: ret i8 [[R]]114;115 %BO0 = mul nuw i8 %X, 3116 %BO1 = shl nsw nuw i8 %X, 3117 %r = urem i8 %BO0, %BO1118 ret i8 %r119}120 121define i8 @urem_XY_XZ_with_CY_lt_CZ_fail_missing_flag(i8 %X) {122; CHECK-LABEL: @urem_XY_XZ_with_CY_lt_CZ_fail_missing_flag(123; CHECK-NEXT: [[BO0:%.*]] = mul nuw nsw i8 [[X:%.*]], 3124; CHECK-NEXT: [[BO1:%.*]] = mul nsw i8 [[X]], 12125; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]126; CHECK-NEXT: ret i8 [[R]]127;128 %BO0 = mul nuw nsw i8 %X, 3129 %BO1 = mul nsw i8 %X, 12130 %r = urem i8 %BO0, %BO1131 ret i8 %r132}133 134define i8 @urem_XY_XZ_with_CY_gt_CZ(i8 %X) {135; CHECK-LABEL: @urem_XY_XZ_with_CY_gt_CZ(136; CHECK-NEXT: [[R:%.*]] = mul nuw nsw i8 [[X:%.*]], 3137; CHECK-NEXT: ret i8 [[R]]138;139 %BO0 = mul nuw i8 %X, 21140 %BO1 = mul i8 %X, 6141 %r = urem i8 %BO0, %BO1142 ret i8 %r143}144 145define i8 @urem_XY_XZ_with_CY_gt_CZ_fail_missing_flag(i8 %X) {146; CHECK-LABEL: @urem_XY_XZ_with_CY_gt_CZ_fail_missing_flag(147; CHECK-NEXT: [[BO0:%.*]] = mul nsw i8 [[X:%.*]], 21148; CHECK-NEXT: [[BO1:%.*]] = mul nuw nsw i8 [[X]], 6149; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]150; CHECK-NEXT: ret i8 [[R]]151;152 %BO0 = mul nsw i8 %X, 21153 %BO1 = mul nsw nuw i8 %X, 6154 %r = urem i8 %BO0, %BO1155 ret i8 %r156}157 158define i8 @urem_XY_XZ_with_Y_Z_is_mul_X_RemYZ(i8 %X, i8 %Y, i8 %Z) {159; CHECK-LABEL: @urem_XY_XZ_with_Y_Z_is_mul_X_RemYZ(160; CHECK-NEXT: [[BO0:%.*]] = mul nuw i8 [[X:%.*]], [[Y:%.*]]161; CHECK-NEXT: [[BO1:%.*]] = mul nuw i8 [[Z:%.*]], [[X]]162; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]163; CHECK-NEXT: ret i8 [[R]]164;165 %BO0 = mul nuw i8 %X, %Y166 %BO1 = mul nuw i8 %Z, %X167 %r = urem i8 %BO0, %BO1168 ret i8 %r169}170 171define i8 @urem_XY_XZ_with_CX_Y_Z_is_mul_X_RemYZ(i8 %Y, i8 %Z) {172; CHECK-LABEL: @urem_XY_XZ_with_CX_Y_Z_is_mul_X_RemYZ(173; CHECK-NEXT: [[BO0:%.*]] = mul nuw i8 [[Y:%.*]], 10174; CHECK-NEXT: [[BO1:%.*]] = shl nuw i8 10, [[Z:%.*]]175; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]176; CHECK-NEXT: ret i8 [[R]]177;178 %BO0 = mul nuw i8 10, %Y179 %BO1 = shl nuw i8 10, %Z180 %r = urem i8 %BO0, %BO1181 ret i8 %r182}183 184define i8 @urem_XY_XZ_with_Y_Z_is_mul_X_RemYZ_with_nsw_out1(i8 %X, i8 %Y, i8 %Z) {185; CHECK-LABEL: @urem_XY_XZ_with_Y_Z_is_mul_X_RemYZ_with_nsw_out1(186; CHECK-NEXT: [[BO0:%.*]] = mul nuw nsw i8 [[X:%.*]], [[Y:%.*]]187; CHECK-NEXT: [[BO1:%.*]] = shl nuw i8 [[X]], [[Z:%.*]]188; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]189; CHECK-NEXT: ret i8 [[R]]190;191 %BO0 = mul nuw nsw i8 %X, %Y192 %BO1 = shl nuw i8 %X, %Z193 %r = urem i8 %BO0, %BO1194 ret i8 %r195}196 197define <2 x i8> @urem_XY_XZ_with_Y_Z_is_mul_X_RemYZ_with_nsw_out2(<2 x i8> %X, <2 x i8> %Y, <2 x i8> %Z) {198; CHECK-LABEL: @urem_XY_XZ_with_Y_Z_is_mul_X_RemYZ_with_nsw_out2(199; CHECK-NEXT: [[BO0:%.*]] = shl nuw <2 x i8> [[Y:%.*]], [[X:%.*]]200; CHECK-NEXT: [[BO1:%.*]] = shl nuw nsw <2 x i8> [[Z:%.*]], [[X]]201; CHECK-NEXT: [[R:%.*]] = urem <2 x i8> [[BO0]], [[BO1]]202; CHECK-NEXT: ret <2 x i8> [[R]]203;204 %BO0 = shl nuw <2 x i8> %Y, %X205 %BO1 = shl nuw nsw <2 x i8> %Z, %X206 %r = urem <2 x i8> %BO0, %BO1207 ret <2 x i8> %r208}209 210define i8 @urem_XY_XZ_with_Y_Z_is_mul_X_RemYZ_fail_reused1(i8 %X, i8 %Y, i8 %Z) {211; CHECK-LABEL: @urem_XY_XZ_with_Y_Z_is_mul_X_RemYZ_fail_reused1(212; CHECK-NEXT: [[BO0:%.*]] = mul nuw nsw i8 [[X:%.*]], [[Y:%.*]]213; CHECK-NEXT: [[BO1:%.*]] = mul nuw nsw i8 [[X]], [[Z:%.*]]214; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]215; CHECK-NEXT: call void @use8(i8 [[BO0]])216; CHECK-NEXT: ret i8 [[R]]217;218 %BO0 = mul nsw nuw i8 %X, %Y219 %BO1 = mul nsw nuw i8 %X, %Z220 %r = urem i8 %BO0, %BO1221 call void @use8(i8 %BO0)222 ret i8 %r223}224 225define <2 x i8> @urem_XY_XZ_with_Y_Z_is_mul_X_RemYZ_fail_missing_flags1(<2 x i8> %X, <2 x i8> %Y, <2 x i8> %Z) {226; CHECK-LABEL: @urem_XY_XZ_with_Y_Z_is_mul_X_RemYZ_fail_missing_flags1(227; CHECK-NEXT: [[BO0:%.*]] = mul nsw <2 x i8> [[X:%.*]], [[Y:%.*]]228; CHECK-NEXT: [[BO1:%.*]] = mul nuw nsw <2 x i8> [[X]], [[Z:%.*]]229; CHECK-NEXT: [[R:%.*]] = urem <2 x i8> [[BO0]], [[BO1]]230; CHECK-NEXT: ret <2 x i8> [[R]]231;232 %BO0 = mul nsw <2 x i8> %X, %Y233 %BO1 = mul nsw nuw <2 x i8> %X, %Z234 %r = urem <2 x i8> %BO0, %BO1235 ret <2 x i8> %r236}237 238define i8 @urem_XY_XZ_with_Y_Z_is_mul_X_RemYZ_fail_missing_flags2(i8 %X, i8 %Y, i8 %Z) {239; CHECK-LABEL: @urem_XY_XZ_with_Y_Z_is_mul_X_RemYZ_fail_missing_flags2(240; CHECK-NEXT: [[BO0:%.*]] = mul nuw nsw i8 [[X:%.*]], [[Y:%.*]]241; CHECK-NEXT: [[BO1:%.*]] = shl nsw i8 [[X]], [[Z:%.*]]242; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]243; CHECK-NEXT: ret i8 [[R]]244;245 %BO0 = mul nsw nuw i8 %X, %Y246 %BO1 = shl nsw i8 %X, %Z247 %r = urem i8 %BO0, %BO1248 ret i8 %r249}250 251;; Signed Verions252define <vscale x 16 x i8> @srem_XY_XZ_with_CY_rem_CZ_eq_0_scalable(<vscale x 16 x i8> %X) {253; CHECK-LABEL: @srem_XY_XZ_with_CY_rem_CZ_eq_0_scalable(254; CHECK-NEXT: ret <vscale x 16 x i8> zeroinitializer255;256 %BO0 = mul nsw <vscale x 16 x i8> %X, splat (i8 15)257 %BO1 = mul <vscale x 16 x i8> %X, splat (i8 5)258 %r = srem <vscale x 16 x i8> %BO0, %BO1259 ret <vscale x 16 x i8> %r260}261 262define i8 @srem_XY_XZ_with_CY_rem_CZ_eq_0(i8 %X) {263; CHECK-LABEL: @srem_XY_XZ_with_CY_rem_CZ_eq_0(264; CHECK-NEXT: ret i8 0265;266 %BO0 = mul nsw i8 %X, 9267 %BO1 = mul i8 %X, 3268 %r = srem i8 %BO0, %BO1269 ret i8 %r270}271 272define i8 @srem_XY_XZ_with_CY_rem_CZ_eq_0_fail_missing_flag(i8 %X) {273; CHECK-LABEL: @srem_XY_XZ_with_CY_rem_CZ_eq_0_fail_missing_flag(274; CHECK-NEXT: [[BO0:%.*]] = mul nuw i8 [[X:%.*]], 9275; CHECK-NEXT: [[BO1:%.*]] = mul nuw nsw i8 [[X]], 3276; CHECK-NEXT: [[R:%.*]] = srem i8 [[BO0]], [[BO1]]277; CHECK-NEXT: ret i8 [[R]]278;279 %BO0 = mul nuw i8 %X, 9280 %BO1 = mul nsw nuw i8 %X, 3281 %r = srem i8 %BO0, %BO1282 ret i8 %r283}284 285define <2 x i8> @srem_XY_XZ_with_CY_lt_CZ(<2 x i8> %X) {286; CHECK-LABEL: @srem_XY_XZ_with_CY_lt_CZ(287; CHECK-NEXT: [[R:%.*]] = shl nsw <2 x i8> [[X:%.*]], splat (i8 3)288; CHECK-NEXT: ret <2 x i8> [[R]]289;290 %BO0 = shl <2 x i8> %X, <i8 3, i8 3>291 %BO1 = mul nsw <2 x i8> %X, <i8 15, i8 15>292 %r = srem <2 x i8> %BO0, %BO1293 ret <2 x i8> %r294}295 296define i8 @srem_XY_XZ_with_CY_lt_CZ_with_nuw_out(i8 %X) {297; CHECK-LABEL: @srem_XY_XZ_with_CY_lt_CZ_with_nuw_out(298; CHECK-NEXT: [[R:%.*]] = mul nuw nsw i8 [[X:%.*]], 5299; CHECK-NEXT: ret i8 [[R]]300;301 %BO0 = mul nuw i8 %X, 5302 %BO1 = mul nsw i8 %X, 15303 %r = srem i8 %BO0, %BO1304 ret i8 %r305}306 307define <2 x i8> @srem_XY_XZ_with_CY_lt_CZ_with_nuw_out_with_shl(<2 x i8> %X) {308; CHECK-LABEL: @srem_XY_XZ_with_CY_lt_CZ_with_nuw_out_with_shl(309; CHECK-NEXT: [[R:%.*]] = shl nuw nsw <2 x i8> splat (i8 3), [[X:%.*]]310; CHECK-NEXT: ret <2 x i8> [[R]]311;312 %BO0 = shl nuw <2 x i8> <i8 3, i8 3>, %X313 %BO1 = shl nsw <2 x i8> <i8 15, i8 15>, %X314 %r = srem <2 x i8> %BO0, %BO1315 ret <2 x i8> %r316}317 318define i8 @srem_XY_XZ_with_CY_lt_CZ_no_nsw_out(i8 %X) {319; CHECK-LABEL: @srem_XY_XZ_with_CY_lt_CZ_no_nsw_out(320; CHECK-NEXT: [[R:%.*]] = mul nsw i8 [[X:%.*]], 5321; CHECK-NEXT: ret i8 [[R]]322;323 %BO0 = mul nsw i8 %X, 5324 %BO1 = shl nsw nuw i8 %X, 4325 %r = srem i8 %BO0, %BO1326 ret i8 %r327}328 329define i8 @srem_XY_XZ_with_CY_lt_CZ_fail_missing_flag(i8 %X) {330; CHECK-LABEL: @srem_XY_XZ_with_CY_lt_CZ_fail_missing_flag(331; CHECK-NEXT: [[BO0:%.*]] = mul nuw nsw i8 [[X:%.*]], 5332; CHECK-NEXT: [[BO1:%.*]] = shl nuw i8 [[X]], 4333; CHECK-NEXT: [[R:%.*]] = srem i8 [[BO0]], [[BO1]]334; CHECK-NEXT: ret i8 [[R]]335;336 %BO0 = mul nuw nsw i8 %X, 5337 %BO1 = shl nuw i8 %X, 4338 %r = srem i8 %BO0, %BO1339 ret i8 %r340}341 342define i8 @srem_XY_XZ_with_CY_gt_CZ(i8 %X) {343; CHECK-LABEL: @srem_XY_XZ_with_CY_gt_CZ(344; CHECK-NEXT: [[R:%.*]] = shl nsw i8 [[X:%.*]], 1345; CHECK-NEXT: ret i8 [[R]]346;347 %BO0 = shl nsw i8 %X, 3348 %BO1 = mul nsw i8 %X, 6349 %r = srem i8 %BO0, %BO1350 ret i8 %r351}352 353define i8 @srem_XY_XZ_with_CY_gt_CZ_with_nuw_out(i8 %X) {354; CHECK-LABEL: @srem_XY_XZ_with_CY_gt_CZ_with_nuw_out(355; CHECK-NEXT: [[R:%.*]] = shl nuw nsw i8 [[X:%.*]], 2356; CHECK-NEXT: ret i8 [[R]]357;358 %BO0 = mul nsw nuw i8 %X, 10359 %BO1 = mul nsw i8 %X, 6360 %r = srem i8 %BO0, %BO1361 ret i8 %r362}363 364define <2 x i8> @srem_XY_XZ_with_CY_gt_CZ_no_nuw_out(<2 x i8> %X) {365; CHECK-LABEL: @srem_XY_XZ_with_CY_gt_CZ_no_nuw_out(366; CHECK-NEXT: [[R:%.*]] = shl nsw <2 x i8> [[X:%.*]], splat (i8 1)367; CHECK-NEXT: ret <2 x i8> [[R]]368;369 %BO0 = mul nsw <2 x i8> %X, <i8 10, i8 10>370 %BO1 = shl nsw nuw <2 x i8> %X, <i8 3, i8 3>371 %r = srem <2 x i8> %BO0, %BO1372 ret <2 x i8> %r373}374 375define i8 @srem_XY_XZ_with_CY_gt_CZ_drop_nsw(i8 noundef %X) {376; CHECK-LABEL: @srem_XY_XZ_with_CY_gt_CZ_drop_nsw(377; CHECK-NEXT: [[BO0:%.*]] = mul nsw i8 [[X:%.*]], 127378; CHECK-NEXT: [[BO1:%.*]] = shl nsw i8 [[X]], 7379; CHECK-NEXT: [[R:%.*]] = srem i8 [[BO1]], [[BO0]]380; CHECK-NEXT: ret i8 [[R]]381;382 %BO0 = mul nsw i8 %X, 127383 %BO1 = shl nsw i8 %X, 7384 %r = srem i8 %BO1, %BO0385 ret i8 %r386}387 388define i8 @srem_XY_XZ_with_CY_gt_CZ_drop_nsw_commuted(i8 noundef %X) {389; CHECK-LABEL: @srem_XY_XZ_with_CY_gt_CZ_drop_nsw_commuted(390; CHECK-NEXT: [[BO0:%.*]] = mul nsw i8 [[X:%.*]], 127391; CHECK-NEXT: [[BO1:%.*]] = shl nsw i8 [[X]], 7392; CHECK-NEXT: [[R:%.*]] = srem i8 [[BO0]], [[BO1]]393; CHECK-NEXT: ret i8 [[R]]394;395 %BO0 = mul nsw i8 %X, 127396 %BO1 = shl nsw i8 %X, 7397 %r = srem i8 %BO0, %BO1398 ret i8 %r399}400 401define i8 @srem_XY_XZ_with_CY_gt_CZ_fail_missing_flag1(i8 %X) {402; CHECK-LABEL: @srem_XY_XZ_with_CY_gt_CZ_fail_missing_flag1(403; CHECK-NEXT: [[BO0:%.*]] = mul nuw nsw i8 [[X:%.*]], 10404; CHECK-NEXT: [[BO1:%.*]] = mul nuw i8 [[X]], 6405; CHECK-NEXT: [[R:%.*]] = srem i8 [[BO0]], [[BO1]]406; CHECK-NEXT: ret i8 [[R]]407;408 %BO0 = mul nsw nuw i8 %X, 10409 %BO1 = mul nuw i8 %X, 6410 %r = srem i8 %BO0, %BO1411 ret i8 %r412}413 414define i8 @srem_XY_XZ_with_CY_gt_CZ_fail_missing_flag2(i8 %X) {415; CHECK-LABEL: @srem_XY_XZ_with_CY_gt_CZ_fail_missing_flag2(416; CHECK-NEXT: [[BO0:%.*]] = shl nuw i8 [[X:%.*]], 4417; CHECK-NEXT: [[BO1:%.*]] = mul nuw nsw i8 [[X]], 5418; CHECK-NEXT: [[R:%.*]] = srem i8 [[BO0]], [[BO1]]419; CHECK-NEXT: ret i8 [[R]]420;421 %BO0 = shl nuw i8 %X, 4422 %BO1 = mul nsw nuw i8 %X, 5423 %r = srem i8 %BO0, %BO1424 ret i8 %r425}426 427define i8 @srem_XY_XZ_with_Y_Z_is_mul_X_RemYZ(i8 %X, i8 %Y, i8 %Z) {428; CHECK-LABEL: @srem_XY_XZ_with_Y_Z_is_mul_X_RemYZ(429; CHECK-NEXT: [[BO0:%.*]] = mul nsw i8 [[Y:%.*]], [[X:%.*]]430; CHECK-NEXT: [[BO1:%.*]] = mul nuw nsw i8 [[X]], [[Z:%.*]]431; CHECK-NEXT: [[R:%.*]] = srem i8 [[BO0]], [[BO1]]432; CHECK-NEXT: ret i8 [[R]]433;434 %BO0 = mul nsw i8 %Y, %X435 %BO1 = mul nsw nuw i8 %X, %Z436 %r = srem i8 %BO0, %BO1437 ret i8 %r438}439 440define i8 @srem_XY_XZ_with_Y_Z_is_mul_X_RemYZ_with_nuw_out(i8 %X, i8 %Y, i8 %Z) {441; CHECK-LABEL: @srem_XY_XZ_with_Y_Z_is_mul_X_RemYZ_with_nuw_out(442; CHECK-NEXT: [[BO0:%.*]] = mul nuw nsw i8 [[Y:%.*]], [[X:%.*]]443; CHECK-NEXT: [[BO1:%.*]] = mul nuw nsw i8 [[Z:%.*]], [[X]]444; CHECK-NEXT: [[R:%.*]] = srem i8 [[BO0]], [[BO1]]445; CHECK-NEXT: ret i8 [[R]]446;447 %BO0 = mul nsw nuw i8 %Y, %X448 %BO1 = mul nsw nuw i8 %Z, %X449 %r = srem i8 %BO0, %BO1450 ret i8 %r451}452 453define i8 @srem_XY_XZ_with_Y_Z_is_mul_X_RemYZ_fail_shl(i8 %X, i8 %Y, i8 %Z) {454; CHECK-LABEL: @srem_XY_XZ_with_Y_Z_is_mul_X_RemYZ_fail_shl(455; CHECK-NEXT: [[BO0:%.*]] = shl nuw nsw i8 [[X:%.*]], [[Y:%.*]]456; CHECK-NEXT: [[BO1:%.*]] = shl nuw nsw i8 [[X]], [[Z:%.*]]457; CHECK-NEXT: [[R:%.*]] = srem i8 [[BO0]], [[BO1]]458; CHECK-NEXT: ret i8 [[R]]459;460 %BO0 = shl nsw nuw i8 %X, %Y461 %BO1 = shl nsw nuw i8 %X, %Z462 %r = srem i8 %BO0, %BO1463 ret i8 %r464}465 466 467define i8 @srem_XY_XZ_with_Y_Z_is_mul_X_RemYZ_fail_missing_flags1(i8 %X, i8 %Y, i8 %Z) {468; CHECK-LABEL: @srem_XY_XZ_with_Y_Z_is_mul_X_RemYZ_fail_missing_flags1(469; CHECK-NEXT: [[BO0:%.*]] = mul nuw i8 [[X:%.*]], [[Y:%.*]]470; CHECK-NEXT: [[BO1:%.*]] = mul nuw nsw i8 [[X]], [[Z:%.*]]471; CHECK-NEXT: [[R:%.*]] = srem i8 [[BO0]], [[BO1]]472; CHECK-NEXT: ret i8 [[R]]473;474 %BO0 = mul nuw i8 %X, %Y475 %BO1 = mul nsw nuw i8 %X, %Z476 %r = srem i8 %BO0, %BO1477 ret i8 %r478}479 480define i8 @srem_XY_XZ_with_Y_Z_is_mul_X_RemYZ_fail_missing_flags2(i8 %X, i8 %Y, i8 %Z) {481; CHECK-LABEL: @srem_XY_XZ_with_Y_Z_is_mul_X_RemYZ_fail_missing_flags2(482; CHECK-NEXT: [[BO0:%.*]] = mul nuw nsw i8 [[X:%.*]], [[Y:%.*]]483; CHECK-NEXT: [[BO1:%.*]] = mul nuw i8 [[X]], [[Z:%.*]]484; CHECK-NEXT: [[R:%.*]] = srem i8 [[BO0]], [[BO1]]485; CHECK-NEXT: ret i8 [[R]]486;487 %BO0 = mul nsw nuw i8 %X, %Y488 %BO1 = mul nuw i8 %X, %Z489 %r = srem i8 %BO0, %BO1490 ret i8 %r491}492 493define i8 @urem_shl_XY_shl_ZX_fail(i8 %X, i8 %Z, i8 %Y) {494; CHECK-LABEL: @urem_shl_XY_shl_ZX_fail(495; CHECK-NEXT: [[BO0:%.*]] = shl nuw nsw i8 [[X:%.*]], [[Y:%.*]]496; CHECK-NEXT: [[BO1:%.*]] = shl nuw nsw i8 [[Z:%.*]], [[X]]497; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]498; CHECK-NEXT: ret i8 [[R]]499;500 %BO0 = shl nuw nsw i8 %X, %Y501 %BO1 = shl nuw nsw i8 %Z, %X502 %r = urem i8 %BO0, %BO1503 ret i8 %r504}505 506define i8 @urem_mul_XY_shl_ZX_fail(i8 %X, i8 %Z, i8 %Y) {507; CHECK-LABEL: @urem_mul_XY_shl_ZX_fail(508; CHECK-NEXT: [[BO0:%.*]] = mul nuw nsw i8 [[X:%.*]], [[Y:%.*]]509; CHECK-NEXT: [[BO1:%.*]] = shl nuw nsw i8 [[Z:%.*]], [[X]]510; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]511; CHECK-NEXT: ret i8 [[R]]512;513 %BO0 = mul nuw nsw i8 %X, %Y514 %BO1 = shl nuw nsw i8 %Z, %X515 %r = urem i8 %BO0, %BO1516 ret i8 %r517}518 519define i8 @urem_shl_YX_shl_XZ_fail(i8 %X, i8 %Z, i8 %Y) {520; CHECK-LABEL: @urem_shl_YX_shl_XZ_fail(521; CHECK-NEXT: [[BO0:%.*]] = shl nuw nsw i8 [[Y:%.*]], [[X:%.*]]522; CHECK-NEXT: [[BO1:%.*]] = shl nuw nsw i8 [[X]], [[Z:%.*]]523; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]524; CHECK-NEXT: ret i8 [[R]]525;526 %BO0 = shl nuw nsw i8 %Y, %X527 %BO1 = shl nuw nsw i8 %X, %Z528 %r = urem i8 %BO0, %BO1529 ret i8 %r530}531 532define i8 @urem_shl_YX_mul_XZ_fail(i8 %X, i8 %Z, i8 %Y) {533; CHECK-LABEL: @urem_shl_YX_mul_XZ_fail(534; CHECK-NEXT: [[BO0:%.*]] = shl nuw nsw i8 [[Y:%.*]], [[X:%.*]]535; CHECK-NEXT: [[BO1:%.*]] = mul nuw nsw i8 [[X]], [[Z:%.*]]536; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]537; CHECK-NEXT: ret i8 [[R]]538;539 %BO0 = shl nuw nsw i8 %Y, %X540 %BO1 = mul nuw nsw i8 %X, %Z541 %r = urem i8 %BO0, %BO1542 ret i8 %r543}544 545define i8 @urem_shl_YX_mul_ZX_fail(i8 %X, i8 %Z, i8 %Y) {546; CHECK-LABEL: @urem_shl_YX_mul_ZX_fail(547; CHECK-NEXT: [[BO0:%.*]] = shl nuw nsw i8 [[Y:%.*]], [[X:%.*]]548; CHECK-NEXT: [[BO1:%.*]] = mul nuw nsw i8 [[Z:%.*]], [[X]]549; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]550; CHECK-NEXT: ret i8 [[R]]551;552 %BO0 = shl nuw nsw i8 %Y, %X553 %BO1 = mul nuw nsw i8 %Z, %X554 %r = urem i8 %BO0, %BO1555 ret i8 %r556}557 558define i8 @urem_mul_YX_shl_ZX_fail(i8 %X, i8 %Z, i8 %Y) {559; CHECK-LABEL: @urem_mul_YX_shl_ZX_fail(560; CHECK-NEXT: [[BO0:%.*]] = mul nuw nsw i8 [[Y:%.*]], [[X:%.*]]561; CHECK-NEXT: [[BO1:%.*]] = shl nuw nsw i8 [[Z:%.*]], [[X]]562; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]563; CHECK-NEXT: ret i8 [[R]]564;565 %BO0 = mul nuw nsw i8 %Y, %X566 %BO1 = shl nuw nsw i8 %Z, %X567 %r = urem i8 %BO0, %BO1568 ret i8 %r569}570 571define i8 @urem_shl_CXY_shl_ZCX_fail(i8 %Z, i8 %Y) {572; CHECK-LABEL: @urem_shl_CXY_shl_ZCX_fail(573; CHECK-NEXT: [[BO0:%.*]] = shl nuw nsw i8 3, [[Y:%.*]]574; CHECK-NEXT: [[BO1:%.*]] = shl nuw nsw i8 [[Z:%.*]], 3575; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]576; CHECK-NEXT: ret i8 [[R]]577;578 %BO0 = shl nuw nsw i8 3, %Y579 %BO1 = shl nuw nsw i8 %Z, 3580 %r = urem i8 %BO0, %BO1581 ret i8 %r582}583 584define i8 @urem_shl_YCX_shl_CXZ_fail(i8 %Z, i8 %Y) {585; CHECK-LABEL: @urem_shl_YCX_shl_CXZ_fail(586; CHECK-NEXT: [[BO0:%.*]] = shl nuw nsw i8 [[Y:%.*]], 3587; CHECK-NEXT: [[BO1:%.*]] = shl nuw nsw i8 3, [[Z:%.*]]588; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]589; CHECK-NEXT: ret i8 [[R]]590;591 %BO0 = shl nuw nsw i8 %Y, 3592 %BO1 = shl nuw nsw i8 3, %Z593 %r = urem i8 %BO0, %BO1594 ret i8 %r595}596 597define i8 @urem_shl_YCX_mul_ZCX_fail(i8 %Z, i8 %Y) {598; CHECK-LABEL: @urem_shl_YCX_mul_ZCX_fail(599; CHECK-NEXT: [[BO0:%.*]] = shl nuw nsw i8 [[Y:%.*]], 3600; CHECK-NEXT: [[BO1:%.*]] = mul nuw nsw i8 [[Z:%.*]], 10601; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]602; CHECK-NEXT: ret i8 [[R]]603;604 %BO0 = shl nuw nsw i8 %Y, 3605 %BO1 = mul nuw nsw i8 %Z, 10606 %r = urem i8 %BO0, %BO1607 ret i8 %r608}609 610define i8 @urem_mul_YCX_shl_ZCX_fail(i8 %Z, i8 %Y) {611; CHECK-LABEL: @urem_mul_YCX_shl_ZCX_fail(612; CHECK-NEXT: [[BO0:%.*]] = mul nuw nsw i8 [[Y:%.*]], 3613; CHECK-NEXT: [[BO1:%.*]] = shl nuw nsw i8 [[Z:%.*]], 3614; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]615; CHECK-NEXT: ret i8 [[R]]616;617 %BO0 = mul nuw nsw i8 %Y, 3618 %BO1 = shl nuw nsw i8 %Z, 3619 %r = urem i8 %BO0, %BO1620 ret i8 %r621}622 623define i8 @urem_shl_XCY_shl_CZX_fail(i8 %X) {624; CHECK-LABEL: @urem_shl_XCY_shl_CZX_fail(625; CHECK-NEXT: [[BO0:%.*]] = shl nuw nsw i8 [[X:%.*]], 3626; CHECK-NEXT: [[BO1:%.*]] = shl nuw nsw i8 6, [[X]]627; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]628; CHECK-NEXT: ret i8 [[R]]629;630 %BO0 = shl nuw nsw i8 %X, 3631 %BO1 = shl nuw nsw i8 6, %X632 %r = urem i8 %BO0, %BO1633 ret i8 %r634}635 636define i8 @urem_mul_XCY_shl_CZX_fail(i8 %X) {637; CHECK-LABEL: @urem_mul_XCY_shl_CZX_fail(638; CHECK-NEXT: [[BO0:%.*]] = mul nuw nsw i8 [[X:%.*]], 6639; CHECK-NEXT: [[BO1:%.*]] = shl nuw nsw i8 3, [[X]]640; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]641; CHECK-NEXT: ret i8 [[R]]642;643 %BO0 = mul nuw nsw i8 %X, 6644 %BO1 = shl nuw nsw i8 3, %X645 %r = urem i8 %BO0, %BO1646 ret i8 %r647}648 649define i8 @urem_shl_CYX_shl_XCZ_fail(i8 %X) {650; CHECK-LABEL: @urem_shl_CYX_shl_XCZ_fail(651; CHECK-NEXT: [[BO0:%.*]] = shl nuw nsw i8 3, [[X:%.*]]652; CHECK-NEXT: [[BO1:%.*]] = shl nuw nsw i8 [[X]], 6653; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]654; CHECK-NEXT: ret i8 [[R]]655;656 %BO0 = shl nuw nsw i8 3, %X657 %BO1 = shl nuw nsw i8 %X, 6658 %r = urem i8 %BO0, %BO1659 ret i8 %r660}661 662define i8 @urem_shl_CYX_mul_XCZ_fail(i8 %X) {663; CHECK-LABEL: @urem_shl_CYX_mul_XCZ_fail(664; CHECK-NEXT: [[BO0:%.*]] = shl nuw nsw i8 3, [[X:%.*]]665; CHECK-NEXT: [[BO1:%.*]] = mul nuw nsw i8 [[X]], 10666; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]667; CHECK-NEXT: ret i8 [[R]]668;669 %BO0 = shl nuw nsw i8 3, %X670 %BO1 = mul nuw nsw i8 %X, 10671 %r = urem i8 %BO0, %BO1672 ret i8 %r673}674 675define i8 @urem_shl_XX_shl_ZX(i8 %X, i8 %Z) {676; CHECK-LABEL: @urem_shl_XX_shl_ZX(677; CHECK-NEXT: [[BO0:%.*]] = shl nuw nsw i8 [[X:%.*]], [[X]]678; CHECK-NEXT: [[BO1:%.*]] = shl nuw nsw i8 [[Z:%.*]], [[X]]679; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]680; CHECK-NEXT: ret i8 [[R]]681;682 %BO0 = shl nuw nsw i8 %X, %X683 %BO1 = shl nuw nsw i8 %Z, %X684 %r = urem i8 %BO0, %BO1685 ret i8 %r686}687 688define i8 @urem_shl_YX_shl_XX(i8 %X, i8 %Y) {689; CHECK-LABEL: @urem_shl_YX_shl_XX(690; CHECK-NEXT: [[BO0:%.*]] = shl nuw nsw i8 [[Y:%.*]], [[X:%.*]]691; CHECK-NEXT: [[BO1:%.*]] = shl nuw nsw i8 [[X]], [[X]]692; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]693; CHECK-NEXT: ret i8 [[R]]694;695 %BO0 = shl nuw nsw i8 %Y, %X696 %BO1 = shl nuw nsw i8 %X, %X697 %r = urem i8 %BO0, %BO1698 ret i8 %r699}700 701define i8 @urem_shl_XX_shl_XZ(i8 %X, i8 %Z) {702; CHECK-LABEL: @urem_shl_XX_shl_XZ(703; CHECK-NEXT: [[BO0:%.*]] = shl nuw nsw i8 [[X:%.*]], [[X]]704; CHECK-NEXT: [[BO1:%.*]] = shl nuw nsw i8 [[X]], [[Z:%.*]]705; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]706; CHECK-NEXT: ret i8 [[R]]707;708 %BO0 = shl nuw nsw i8 %X, %X709 %BO1 = shl nuw nsw i8 %X, %Z710 %r = urem i8 %BO0, %BO1711 ret i8 %r712}713 714define i8 @urem_shl_XY_shl_XX(i8 %X, i8 %Y) {715; CHECK-LABEL: @urem_shl_XY_shl_XX(716; CHECK-NEXT: [[BO0:%.*]] = shl nuw nsw i8 [[X:%.*]], [[Y:%.*]]717; CHECK-NEXT: [[BO1:%.*]] = shl nuw nsw i8 [[X]], [[X]]718; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]719; CHECK-NEXT: ret i8 [[R]]720;721 %BO0 = shl nuw nsw i8 %X, %Y722 %BO1 = shl nuw nsw i8 %X, %X723 %r = urem i8 %BO0, %BO1724 ret i8 %r725}726 727define i8 @urem_mul_XX_shl_ZX(i8 %X, i8 %Z) {728; CHECK-LABEL: @urem_mul_XX_shl_ZX(729; CHECK-NEXT: [[BO0:%.*]] = mul nuw nsw i8 [[X:%.*]], [[X]]730; CHECK-NEXT: [[BO1:%.*]] = shl nuw nsw i8 [[Z:%.*]], [[X]]731; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]732; CHECK-NEXT: ret i8 [[R]]733;734 %BO0 = mul nuw nsw i8 %X, %X735 %BO1 = shl nuw nsw i8 %Z, %X736 %r = urem i8 %BO0, %BO1737 ret i8 %r738}739 740define i8 @urem_mul_YX_shl_XX(i8 %X, i8 %Y) {741; CHECK-LABEL: @urem_mul_YX_shl_XX(742; CHECK-NEXT: [[BO0:%.*]] = mul nuw nsw i8 [[Y:%.*]], [[X:%.*]]743; CHECK-NEXT: [[BO1:%.*]] = shl nuw nsw i8 [[X]], [[X]]744; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]745; CHECK-NEXT: ret i8 [[R]]746;747 %BO0 = mul nuw nsw i8 %Y, %X748 %BO1 = shl nuw nsw i8 %X, %X749 %r = urem i8 %BO0, %BO1750 ret i8 %r751}752 753define i8 @urem_mul_XX_shl_XZ(i8 %X, i8 %Z) {754; CHECK-LABEL: @urem_mul_XX_shl_XZ(755; CHECK-NEXT: [[BO0:%.*]] = mul nuw nsw i8 [[X:%.*]], [[X]]756; CHECK-NEXT: [[BO1:%.*]] = shl nuw nsw i8 [[X]], [[Z:%.*]]757; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]758; CHECK-NEXT: ret i8 [[R]]759;760 %BO0 = mul nuw nsw i8 %X, %X761 %BO1 = shl nuw nsw i8 %X, %Z762 %r = urem i8 %BO0, %BO1763 ret i8 %r764}765 766define i8 @urem_mul_XY_shl_XX(i8 %X, i8 %Y) {767; CHECK-LABEL: @urem_mul_XY_shl_XX(768; CHECK-NEXT: [[BO0:%.*]] = mul nuw nsw i8 [[X:%.*]], [[Y:%.*]]769; CHECK-NEXT: [[BO1:%.*]] = shl nuw nsw i8 [[X]], [[X]]770; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]771; CHECK-NEXT: ret i8 [[R]]772;773 %BO0 = mul nuw nsw i8 %X, %Y774 %BO1 = shl nuw nsw i8 %X, %X775 %r = urem i8 %BO0, %BO1776 ret i8 %r777}778 779define i8 @urem_shl_XX_mul_ZX(i8 %X, i8 %Z) {780; CHECK-LABEL: @urem_shl_XX_mul_ZX(781; CHECK-NEXT: [[BO0:%.*]] = shl nuw nsw i8 [[X:%.*]], [[X]]782; CHECK-NEXT: [[BO1:%.*]] = mul nuw nsw i8 [[Z:%.*]], [[X]]783; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]784; CHECK-NEXT: ret i8 [[R]]785;786 %BO0 = shl nuw nsw i8 %X, %X787 %BO1 = mul nuw nsw i8 %Z, %X788 %r = urem i8 %BO0, %BO1789 ret i8 %r790}791 792define i8 @urem_shl_YX_mul_XX(i8 %X, i8 %Y) {793; CHECK-LABEL: @urem_shl_YX_mul_XX(794; CHECK-NEXT: [[BO0:%.*]] = shl nuw nsw i8 [[Y:%.*]], [[X:%.*]]795; CHECK-NEXT: [[BO1:%.*]] = mul nuw nsw i8 [[X]], [[X]]796; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]797; CHECK-NEXT: ret i8 [[R]]798;799 %BO0 = shl nuw nsw i8 %Y, %X800 %BO1 = mul nuw nsw i8 %X, %X801 %r = urem i8 %BO0, %BO1802 ret i8 %r803}804 805define i8 @urem_shl_XX_mul_XZ(i8 %X, i8 %Z) {806; CHECK-LABEL: @urem_shl_XX_mul_XZ(807; CHECK-NEXT: [[BO0:%.*]] = shl nuw nsw i8 [[X:%.*]], [[X]]808; CHECK-NEXT: [[BO1:%.*]] = mul nuw nsw i8 [[X]], [[Z:%.*]]809; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]810; CHECK-NEXT: ret i8 [[R]]811;812 %BO0 = shl nuw nsw i8 %X, %X813 %BO1 = mul nuw nsw i8 %X, %Z814 %r = urem i8 %BO0, %BO1815 ret i8 %r816}817 818define i8 @urem_shl_XY_mul_XX(i8 %X, i8 %Y) {819; CHECK-LABEL: @urem_shl_XY_mul_XX(820; CHECK-NEXT: [[BO0:%.*]] = shl nuw nsw i8 [[X:%.*]], [[Y:%.*]]821; CHECK-NEXT: [[BO1:%.*]] = mul nuw nsw i8 [[X]], [[X]]822; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]823; CHECK-NEXT: ret i8 [[R]]824;825 %BO0 = shl nuw nsw i8 %X, %Y826 %BO1 = mul nuw nsw i8 %X, %X827 %r = urem i8 %BO0, %BO1828 ret i8 %r829}830 831define i8 @urem_mul_XX_shl_XX(i8 %X) {832; CHECK-LABEL: @urem_mul_XX_shl_XX(833; CHECK-NEXT: [[BO0:%.*]] = mul nuw nsw i8 [[X:%.*]], [[X]]834; CHECK-NEXT: [[BO1:%.*]] = shl nuw nsw i8 [[X]], [[X]]835; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]836; CHECK-NEXT: ret i8 [[R]]837;838 %BO0 = mul nuw nsw i8 %X, %X839 %BO1 = shl nuw nsw i8 %X, %X840 %r = urem i8 %BO0, %BO1841 ret i8 %r842}843 844define i8 @urem_shl_XX_mul_XX(i8 %X) {845; CHECK-LABEL: @urem_shl_XX_mul_XX(846; CHECK-NEXT: [[BO0:%.*]] = shl nuw nsw i8 [[X:%.*]], [[X]]847; CHECK-NEXT: [[BO1:%.*]] = mul nuw nsw i8 [[X]], [[X]]848; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]849; CHECK-NEXT: ret i8 [[R]]850;851 %BO0 = shl nuw nsw i8 %X, %X852 %BO1 = mul nuw nsw i8 %X, %X853 %r = urem i8 %BO0, %BO1854 ret i8 %r855}856 857; Negative test: No attribute vscale_range to indicate range858define i64 @urem_shl_vscale() {859; CHECK-LABEL: @urem_shl_vscale(860; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()861; CHECK-NEXT: [[SHIFT:%.*]] = shl nuw nsw i64 [[VSCALE]], 2862; CHECK-NEXT: [[REM:%.*]] = urem i64 1024, [[SHIFT]]863; CHECK-NEXT: ret i64 [[REM]]864;865 %vscale = call i64 @llvm.vscale.i64()866 %shift = shl nuw nsw i64 %vscale, 2867 %rem = urem i64 1024, %shift868 ret i64 %rem869}870 871define i64 @urem_shl_vscale_range() vscale_range(1,16) {872; CHECK-LABEL: @urem_shl_vscale_range(873; CHECK-NEXT: ret i64 0874;875 %vscale = call i64 @llvm.vscale.i64()876 %shift = shl nuw nsw i64 %vscale, 2877 %rem = urem i64 1024, %shift878 ret i64 %rem879}880 881define i64 @urem_vscale_range() vscale_range(1,16) {882; CHECK-LABEL: @urem_vscale_range(883; CHECK-NEXT: ret i64 0884;885 %vscale = call i64 @llvm.vscale.i64()886 %shift = shl nuw nsw i64 %vscale, 6887 %rem = urem i64 1024, %shift888 ret i64 %rem889}890 891define i64 @urem_shl_vscale_out_of_range() vscale_range(1,16) {892; CHECK-LABEL: @urem_shl_vscale_out_of_range(893; CHECK-NEXT: ret i64 1024894;895 %vscale = call i64 @llvm.vscale.i64()896 %shift = shl nuw nsw i64 %vscale, 11897 %rem = urem i64 1024, %shift898 ret i64 %rem899}900 901; Negative test: The min value 1 << 10 is overlap to 1024902define i64 @urem_shl_vscale_overlap() vscale_range(1,16) {903; CHECK-LABEL: @urem_shl_vscale_overlap(904; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()905; CHECK-NEXT: [[SHIFT:%.*]] = shl nuw nsw i64 [[VSCALE]], 10906; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[SHIFT]], 2047907; CHECK-NEXT: [[REM:%.*]] = and i64 [[TMP1]], 1024908; CHECK-NEXT: ret i64 [[REM]]909;910 %vscale = call i64 @llvm.vscale.i64()911 %shift = shl nuw nsw i64 %vscale, 10912 %rem = urem i64 1024, %shift913 ret i64 %rem914}915 916define i64 @and_add_vscale_range_low() vscale_range(1,16) {917; CHECK-LABEL: @and_add_vscale_range_low(918; CHECK-NEXT: ret i64 0919;920 %vscale = call i64 @llvm.vscale.i64()921 %shift = shl nuw nsw i64 %vscale, 6922 %add = add i64 %shift, -1923 %rem = and i64 1024, %add924 ret i64 %rem925}926 927; TODO: have no bits that may be part of the mask set,928; but now expect the const is a power of two929define i64 @and_add_shl_vscale_not_power2() vscale_range(1,16) {930; CHECK-LABEL: @and_add_shl_vscale_not_power2(931; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()932; CHECK-NEXT: [[SHIFT:%.*]] = shl nuw nsw i64 [[VSCALE]], 6933; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i64 [[SHIFT]], 4095934; CHECK-NEXT: [[REM:%.*]] = and i64 [[ADD]], 3072935; CHECK-NEXT: ret i64 [[REM]]936;937 %vscale = call i64 @llvm.vscale.i64()938 %shift = shl nuw nsw i64 %vscale, 6939 %add = add i64 %shift, -1940 %rem = and i64 3072, %add941 ret i64 %rem942}943 944; Allow for INT_MIN, https://alive2.llvm.org/ce/z/yZ_I2a945define i32 @and_add_shl_vscale_not_power2_negative() vscale_range(1,16) {946; CHECK-LABEL: @and_add_shl_vscale_not_power2_negative(947; CHECK-NEXT: ret i32 0948;949 %vscale = call i32 @llvm.vscale.i32()950 %shift = shl nuw nsw i32 %vscale, 6951 %add = add i32 %shift, -1952 %rem = and i32 -2147483648, %add953 ret i32 %rem954}955 956; Negative test: the %sign may be 0, https://alive2.llvm.org/ce/z/WU_j4a957define i32 @and_add_and (i32 %x) {958; CHECK-LABEL: @and_add_and(959; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 24960; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -2147483648961; CHECK-NEXT: [[AND:%.*]] = xor i32 [[TMP2]], -2147483648962; CHECK-NEXT: ret i32 [[AND]]963;964 %x1 = lshr i32 %x, 7965 %sign = and i32 %x1, 1 ; %sign = (%x >> 7) & 1966 %add = add i32 %sign, -1967 %and = and i32 %add, 2147483648968 ret i32 %and969}970 971