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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 22; RUN: opt -passes=instcombine -S < %s 2>&1 | FileCheck %s3 4%struct.test = type { <vscale x 1 x i32>, <vscale x 1 x i32> }5 6define <vscale x 1 x i32> @load(ptr %x) {7; CHECK-LABEL: define <vscale x 1 x i32> @load8; CHECK-SAME: (ptr [[X:%.*]]) {9; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()10; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i64 [[TMP1]], 211; CHECK-NEXT: [[A_ELT1:%.*]] = getelementptr inbounds i8, ptr [[X]], i64 [[TMP2]]12; CHECK-NEXT: [[A_UNPACK2:%.*]] = load <vscale x 1 x i32>, ptr [[A_ELT1]], align 413; CHECK-NEXT: ret <vscale x 1 x i32> [[A_UNPACK2]]14;15 %a = load %struct.test, ptr %x16 %b = extractvalue %struct.test %a, 117 ret <vscale x 1 x i32> %b18}19 20define void @store(ptr %x, <vscale x 1 x i32> %y, <vscale x 1 x i32> %z) {21; CHECK-LABEL: define void @store22; CHECK-SAME: (ptr [[X:%.*]], <vscale x 1 x i32> [[Y:%.*]], <vscale x 1 x i32> [[Z:%.*]]) {23; CHECK-NEXT: store <vscale x 1 x i32> [[Y]], ptr [[X]], align 424; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()25; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i64 [[TMP1]], 226; CHECK-NEXT: [[X_REPACK1:%.*]] = getelementptr inbounds i8, ptr [[X]], i64 [[TMP2]]27; CHECK-NEXT: store <vscale x 1 x i32> [[Z]], ptr [[X_REPACK1]], align 428; CHECK-NEXT: ret void29;30 %a = insertvalue %struct.test undef, <vscale x 1 x i32> %y, 031 %b = insertvalue %struct.test %a, <vscale x 1 x i32> %z, 132 store %struct.test %b, ptr %x33 ret void34}35 36define {<vscale x 16 x i8>, <vscale x 16 x i8>} @split_load(ptr %p) nounwind {37; CHECK-LABEL: define { <vscale x 16 x i8>, <vscale x 16 x i8> } @split_load38; CHECK-SAME: (ptr [[P:%.*]]) #[[ATTR0:[0-9]+]] {39; CHECK-NEXT: entry:40; CHECK-NEXT: [[R_UNPACK:%.*]] = load <vscale x 16 x i8>, ptr [[P]], align 1641; CHECK-NEXT: [[TMP0:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> [[R_UNPACK]], 042; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()43; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i64 [[TMP1]], 444; CHECK-NEXT: [[R_ELT1:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 [[TMP2]]45; CHECK-NEXT: [[R_UNPACK2:%.*]] = load <vscale x 16 x i8>, ptr [[R_ELT1]], align 1646; CHECK-NEXT: [[R3:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP0]], <vscale x 16 x i8> [[R_UNPACK2]], 147; CHECK-NEXT: ret { <vscale x 16 x i8>, <vscale x 16 x i8> } [[R3]]48;49entry:50 %r = load {<vscale x 16 x i8>, <vscale x 16 x i8>}, ptr %p51 ret {<vscale x 16 x i8>, <vscale x 16 x i8>} %r52}53 54define {<vscale x 16 x i8>} @split_load_one(ptr %p) nounwind {55; CHECK-LABEL: define { <vscale x 16 x i8> } @split_load_one56; CHECK-SAME: (ptr [[P:%.*]]) #[[ATTR0]] {57; CHECK-NEXT: entry:58; CHECK-NEXT: [[R_UNPACK:%.*]] = load <vscale x 16 x i8>, ptr [[P]], align 1659; CHECK-NEXT: [[R1:%.*]] = insertvalue { <vscale x 16 x i8> } poison, <vscale x 16 x i8> [[R_UNPACK]], 060; CHECK-NEXT: ret { <vscale x 16 x i8> } [[R1]]61;62entry:63 %r = load {<vscale x 16 x i8>}, ptr %p64 ret {<vscale x 16 x i8>} %r65}66 67define void @split_store({<vscale x 4 x i32>, <vscale x 4 x i32>} %x, ptr %p) nounwind {68; CHECK-LABEL: define void @split_store69; CHECK-SAME: ({ <vscale x 4 x i32>, <vscale x 4 x i32> } [[X:%.*]], ptr [[P:%.*]]) #[[ATTR0]] {70; CHECK-NEXT: entry:71; CHECK-NEXT: [[X_ELT:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[X]], 072; CHECK-NEXT: store <vscale x 4 x i32> [[X_ELT]], ptr [[P]], align 1673; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()74; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 475; CHECK-NEXT: [[P_REPACK1:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 [[TMP1]]76; CHECK-NEXT: [[X_ELT2:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[X]], 177; CHECK-NEXT: store <vscale x 4 x i32> [[X_ELT2]], ptr [[P_REPACK1]], align 1678; CHECK-NEXT: ret void79;80entry:81 store {<vscale x 4 x i32>, <vscale x 4 x i32>} %x, ptr %p82 ret void83}84 85define void @split_store_one({<vscale x 4 x i32>} %x, ptr %p) nounwind {86; CHECK-LABEL: define void @split_store_one87; CHECK-SAME: ({ <vscale x 4 x i32> } [[X:%.*]], ptr [[P:%.*]]) #[[ATTR0]] {88; CHECK-NEXT: entry:89; CHECK-NEXT: [[TMP0:%.*]] = extractvalue { <vscale x 4 x i32> } [[X]], 090; CHECK-NEXT: store <vscale x 4 x i32> [[TMP0]], ptr [[P]], align 1691; CHECK-NEXT: ret void92;93entry:94 store {<vscale x 4 x i32>} %x, ptr %p95 ret void96}97 98define {<16 x i8>, <16 x i8>} @check_v16i8_v4i32({<4 x i32>, <4 x i32>} %x, ptr %p) nounwind {99; CHECK-LABEL: define { <16 x i8>, <16 x i8> } @check_v16i8_v4i32100; CHECK-SAME: ({ <4 x i32>, <4 x i32> } [[X:%.*]], ptr [[P:%.*]]) #[[ATTR0]] {101; CHECK-NEXT: entry:102; CHECK-NEXT: [[X_ELT:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[X]], 0103; CHECK-NEXT: store <4 x i32> [[X_ELT]], ptr [[P]], align 16104; CHECK-NEXT: [[P_REPACK1:%.*]] = getelementptr inbounds nuw i8, ptr [[P]], i64 16105; CHECK-NEXT: [[X_ELT2:%.*]] = extractvalue { <4 x i32>, <4 x i32> } [[X]], 1106; CHECK-NEXT: store <4 x i32> [[X_ELT2]], ptr [[P_REPACK1]], align 16107; CHECK-NEXT: [[R_UNPACK_CAST:%.*]] = bitcast <4 x i32> [[X_ELT]] to <16 x i8>108; CHECK-NEXT: [[TMP0:%.*]] = insertvalue { <16 x i8>, <16 x i8> } poison, <16 x i8> [[R_UNPACK_CAST]], 0109; CHECK-NEXT: [[R_UNPACK4_CAST:%.*]] = bitcast <4 x i32> [[X_ELT2]] to <16 x i8>110; CHECK-NEXT: [[R5:%.*]] = insertvalue { <16 x i8>, <16 x i8> } [[TMP0]], <16 x i8> [[R_UNPACK4_CAST]], 1111; CHECK-NEXT: ret { <16 x i8>, <16 x i8> } [[R5]]112;113entry:114 store {<4 x i32>, <4 x i32>} %x, ptr %p115 %r = load {<16 x i8>, <16 x i8>}, ptr %p116 ret {<16 x i8>, <16 x i8>} %r117}118 119define {<vscale x 16 x i8>, <vscale x 16 x i8>} @check_nxv16i8_nxv4i32({<vscale x 4 x i32>, <vscale x 4 x i32>} %x, ptr %p) nounwind {120; CHECK-LABEL: define { <vscale x 16 x i8>, <vscale x 16 x i8> } @check_nxv16i8_nxv4i32121; CHECK-SAME: ({ <vscale x 4 x i32>, <vscale x 4 x i32> } [[X:%.*]], ptr [[P:%.*]]) #[[ATTR0]] {122; CHECK-NEXT: entry:123; CHECK-NEXT: [[X_ELT:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[X]], 0124; CHECK-NEXT: store <vscale x 4 x i32> [[X_ELT]], ptr [[P]], align 16125; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()126; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 4127; CHECK-NEXT: [[P_REPACK1:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 [[TMP1]]128; CHECK-NEXT: [[X_ELT2:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[X]], 1129; CHECK-NEXT: store <vscale x 4 x i32> [[X_ELT2]], ptr [[P_REPACK1]], align 16130; CHECK-NEXT: [[R_UNPACK:%.*]] = load <vscale x 16 x i8>, ptr [[P]], align 16131; CHECK-NEXT: [[TMP2:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> [[R_UNPACK]], 0132; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()133; CHECK-NEXT: [[TMP4:%.*]] = shl nuw i64 [[TMP3]], 4134; CHECK-NEXT: [[R_ELT3:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 [[TMP4]]135; CHECK-NEXT: [[R_UNPACK4:%.*]] = load <vscale x 16 x i8>, ptr [[R_ELT3]], align 16136; CHECK-NEXT: [[R5:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP2]], <vscale x 16 x i8> [[R_UNPACK4]], 1137; CHECK-NEXT: ret { <vscale x 16 x i8>, <vscale x 16 x i8> } [[R5]]138;139entry:140 store {<vscale x 4 x i32>, <vscale x 4 x i32>} %x, ptr %p141 %r = load {<vscale x 16 x i8>, <vscale x 16 x i8>}, ptr %p142 ret {<vscale x 16 x i8>, <vscale x 16 x i8>} %r143}144 145define {<vscale x 16 x i8>, <vscale x 16 x i8>} @alloca_nxv16i8_nxv4i32({<vscale x 4 x i32>, <vscale x 4 x i32>} %x) nounwind {146; CHECK-LABEL: define { <vscale x 16 x i8>, <vscale x 16 x i8> } @alloca_nxv16i8_nxv4i32147; CHECK-SAME: ({ <vscale x 4 x i32>, <vscale x 4 x i32> } [[X:%.*]]) #[[ATTR0]] {148; CHECK-NEXT: entry:149; CHECK-NEXT: [[P:%.*]] = alloca { <vscale x 4 x i32>, <vscale x 4 x i32> }, align 16150; CHECK-NEXT: [[X_ELT:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[X]], 0151; CHECK-NEXT: store <vscale x 4 x i32> [[X_ELT]], ptr [[P]], align 16152; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()153; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 4154; CHECK-NEXT: [[P_REPACK1:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 [[TMP1]]155; CHECK-NEXT: [[X_ELT2:%.*]] = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } [[X]], 1156; CHECK-NEXT: store <vscale x 4 x i32> [[X_ELT2]], ptr [[P_REPACK1]], align 16157; CHECK-NEXT: [[R_UNPACK:%.*]] = load <vscale x 16 x i8>, ptr [[P]], align 16158; CHECK-NEXT: [[TMP2:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> [[R_UNPACK]], 0159; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()160; CHECK-NEXT: [[TMP4:%.*]] = shl nuw i64 [[TMP3]], 4161; CHECK-NEXT: [[R_ELT3:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 [[TMP4]]162; CHECK-NEXT: [[R_UNPACK4:%.*]] = load <vscale x 16 x i8>, ptr [[R_ELT3]], align 16163; CHECK-NEXT: [[R5:%.*]] = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } [[TMP2]], <vscale x 16 x i8> [[R_UNPACK4]], 1164; CHECK-NEXT: ret { <vscale x 16 x i8>, <vscale x 16 x i8> } [[R5]]165;166entry:167 %p = alloca {<vscale x 4 x i32>, <vscale x 4 x i32>}168 store {<vscale x 4 x i32>, <vscale x 4 x i32>} %x, ptr %p169 %r = load {<vscale x 16 x i8>, <vscale x 16 x i8>}, ptr %p170 ret {<vscale x 16 x i8>, <vscale x 16 x i8>} %r171}172 173define { <16 x i8>, <32 x i8> } @differenttypes({ <4 x i32>, <8 x i32> } %a, ptr %p) {174; CHECK-LABEL: define { <16 x i8>, <32 x i8> } @differenttypes175; CHECK-SAME: ({ <4 x i32>, <8 x i32> } [[A:%.*]], ptr [[P:%.*]]) {176; CHECK-NEXT: entry:177; CHECK-NEXT: store { <4 x i32>, <8 x i32> } [[A]], ptr [[P]], align 16178; CHECK-NEXT: [[TMP0:%.*]] = load { <16 x i8>, <32 x i8> }, ptr [[P]], align 16179; CHECK-NEXT: ret { <16 x i8>, <32 x i8> } [[TMP0]]180;181entry:182 store { <4 x i32>, <8 x i32> } %a, ptr %p, align 16183 %2 = load { <16 x i8>, <32 x i8> }, ptr %p, align 16184 ret { <16 x i8>, <32 x i8> } %2185}186