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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -passes=instcombine < %s | FileCheck %s3 4define i64 @sel_false_val_is_a_masked_shl_of_true_val1(i32 %x, i64 %y) {5; CHECK-LABEL: @sel_false_val_is_a_masked_shl_of_true_val1(6; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 27; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 608; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i649; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]10; CHECK-NEXT: ret i64 [[TMP4]]11;12 %1 = and i32 %x, 1513 %2 = shl nuw nsw i32 %1, 214 %3 = zext i32 %2 to i6415 %4 = icmp eq i32 %1, 016 %5 = ashr i64 %y, %317 %6 = select i1 %4, i64 %y, i64 %518 ret i64 %619}20 21define i64 @sel_false_val_is_a_masked_shl_of_true_val2(i32 %x, i64 %y) {22; CHECK-LABEL: @sel_false_val_is_a_masked_shl_of_true_val2(23; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 224; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 6025; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i6426; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]27; CHECK-NEXT: ret i64 [[TMP4]]28;29 %1 = and i32 %x, 1530 %2 = shl nuw nsw i32 %1, 231 %3 = zext i32 %2 to i6432 %4 = icmp eq i32 %2, 033 %5 = ashr i64 %y, %334 %6 = select i1 %4, i64 %y, i64 %535 ret i64 %636}37 38define i64 @sel_false_val_is_a_masked_lshr_of_true_val1(i32 %x, i64 %y) {39; CHECK-LABEL: @sel_false_val_is_a_masked_lshr_of_true_val1(40; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 241; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 1542; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i6443; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]44; CHECK-NEXT: ret i64 [[TMP4]]45;46 %1 = and i32 %x, 6047 %2 = lshr i32 %1, 248 %3 = zext i32 %2 to i6449 %4 = icmp eq i32 %1, 050 %5 = ashr i64 %y, %351 %6 = select i1 %4, i64 %y, i64 %552 ret i64 %653}54 55define i64 @sel_false_val_is_a_masked_lshr_of_true_val2(i32 %x, i64 %y) {56; CHECK-LABEL: @sel_false_val_is_a_masked_lshr_of_true_val2(57; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 258; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 1559; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i6460; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]61; CHECK-NEXT: ret i64 [[TMP4]]62;63 %1 = and i32 %x, 6064 %2 = lshr i32 %1, 265 %3 = zext i32 %2 to i6466 %4 = icmp eq i32 %2, 067 %5 = ashr i64 %y, %368 %6 = select i1 %4, i64 %y, i64 %569 ret i64 %670}71 72define i64 @sel_false_val_is_a_masked_ashr_of_true_val1(i32 %x, i64 %y) {73; CHECK-LABEL: @sel_false_val_is_a_masked_ashr_of_true_val1(74; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 275; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -53687089776; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i6477; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]78; CHECK-NEXT: ret i64 [[TMP4]]79;80 %1 = and i32 %x, -214748358881 %2 = ashr i32 %1, 282 %3 = zext i32 %2 to i6483 %4 = icmp eq i32 %1, 084 %5 = ashr i64 %y, %385 %6 = select i1 %4, i64 %y, i64 %586 ret i64 %687}88 89define i64 @sel_false_val_is_a_masked_ashr_of_true_val2(i32 %x, i64 %y) {90; CHECK-LABEL: @sel_false_val_is_a_masked_ashr_of_true_val2(91; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 292; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -53687089793; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i6494; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]95; CHECK-NEXT: ret i64 [[TMP4]]96;97 %1 = and i32 %x, -214748358898 %2 = ashr i32 %1, 299 %3 = zext i32 %2 to i64100 %4 = icmp eq i32 %2, 0101 %5 = ashr i64 %y, %3102 %6 = select i1 %4, i64 %y, i64 %5103 ret i64 %6104}105 106